1 | /*
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2 | * Copyright (c) 1999, 2000
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3 | * Intel Corporation.
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4 | * All rights reserved.
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5 | *
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6 | * Redistribution and use in source and binary forms, with or without
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7 | * modification, are permitted provided that the following conditions
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8 | * are met:
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9 | *
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10 | * 1. Redistributions of source code must retain the above copyright
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11 | * notice, this list of conditions and the following disclaimer.
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12 | *
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13 | * 2. Redistributions in binary form must reproduce the above copyright
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14 | * notice, this list of conditions and the following disclaimer in the
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15 | * documentation and/or other materials provided with the distribution.
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16 | *
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17 | * 3. All advertising materials mentioning features or use of this software
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18 | * must display the following acknowledgement:
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19 | *
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20 | * This product includes software developed by Intel Corporation and
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21 | * its contributors.
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22 | *
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23 | * 4. Neither the name of Intel Corporation or its contributors may be
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24 | * used to endorse or promote products derived from this software
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25 | * without specific prior written permission.
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26 | *
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27 | * THIS SOFTWARE IS PROVIDED BY INTEL CORPORATION AND CONTRIBUTORS ``AS IS''
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28 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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29 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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30 | * ARE DISCLAIMED. IN NO EVENT SHALL INTEL CORPORATION OR CONTRIBUTORS BE
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31 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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32 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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33 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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34 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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35 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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36 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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37 | * THE POSSIBILITY OF SUCH DAMAGE.
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38 | *
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39 | */
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40 |
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41 |
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42 | #ifndef _EFICONTEXT_H_
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43 | #define _EFICONTEXT_H_
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44 |
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45 |
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46 | //
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47 | // IA-64 processor exception types
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48 | //
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49 | #define EXCPT_ALT_DTLB 4
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50 | #define EXCPT_DNESTED_TLB 5
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51 | #define EXCPT_BREAKPOINT 11
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52 | #define EXCPT_EXTERNAL_INTERRUPT 12
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53 | #define EXCPT_GEN_EXCEPT 24
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54 | #define EXCPT_NAT_CONSUMPTION 26
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55 | #define EXCPT_DEBUG_EXCEPT 29
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56 | #define EXCPT_UNALIGNED_ACCESS 30
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57 | #define EXCPT_FP_FAULT 32
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58 | #define EXCPT_FP_TRAP 33
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59 | #define EXCPT_TAKEN_BRANCH 35
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60 | #define EXCPT_SINGLE_STEP 36
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61 |
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62 | //
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63 | // IA-64 processor context definition - must be 512 byte aligned!!!
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64 | //
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65 | typedef
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66 | struct {
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67 | UINT64 reserved; // necessary to preserve alignment for the correct bits in UNAT and to insure F2 is 16 byte aligned...
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68 |
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69 | UINT64 r1;
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70 | UINT64 r2;
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71 | UINT64 r3;
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72 | UINT64 r4;
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73 | UINT64 r5;
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74 | UINT64 r6;
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75 | UINT64 r7;
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76 | UINT64 r8;
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77 | UINT64 r9;
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78 | UINT64 r10;
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79 | UINT64 r11;
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80 | UINT64 r12;
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81 | UINT64 r13;
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82 | UINT64 r14;
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83 | UINT64 r15;
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84 | UINT64 r16;
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85 | UINT64 r17;
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86 | UINT64 r18;
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87 | UINT64 r19;
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88 | UINT64 r20;
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89 | UINT64 r21;
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90 | UINT64 r22;
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91 | UINT64 r23;
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92 | UINT64 r24;
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93 | UINT64 r25;
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94 | UINT64 r26;
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95 | UINT64 r27;
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96 | UINT64 r28;
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97 | UINT64 r29;
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98 | UINT64 r30;
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99 | UINT64 r31;
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100 |
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101 | UINT64 f2[2];
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102 | UINT64 f3[2];
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103 | UINT64 f4[2];
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104 | UINT64 f5[2];
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105 | UINT64 f6[2];
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106 | UINT64 f7[2];
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107 | UINT64 f8[2];
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108 | UINT64 f9[2];
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109 | UINT64 f10[2];
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110 | UINT64 f11[2];
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111 | UINT64 f12[2];
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112 | UINT64 f13[2];
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113 | UINT64 f14[2];
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114 | UINT64 f15[2];
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115 | UINT64 f16[2];
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116 | UINT64 f17[2];
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117 | UINT64 f18[2];
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118 | UINT64 f19[2];
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119 | UINT64 f20[2];
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120 | UINT64 f21[2];
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121 | UINT64 f22[2];
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122 | UINT64 f23[2];
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123 | UINT64 f24[2];
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124 | UINT64 f25[2];
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125 | UINT64 f26[2];
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126 | UINT64 f27[2];
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127 | UINT64 f28[2];
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128 | UINT64 f29[2];
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129 | UINT64 f30[2];
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130 | UINT64 f31[2];
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131 |
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132 | UINT64 pr;
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133 |
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134 | UINT64 b0;
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135 | UINT64 b1;
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136 | UINT64 b2;
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137 | UINT64 b3;
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138 | UINT64 b4;
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139 | UINT64 b5;
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140 | UINT64 b6;
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141 | UINT64 b7;
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142 |
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143 | // application registers
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144 | UINT64 ar_rsc;
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145 | UINT64 ar_bsp;
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146 | UINT64 ar_bspstore;
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147 | UINT64 ar_rnat;
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148 |
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149 | UINT64 ar_fcr;
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150 |
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151 | UINT64 ar_eflag;
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152 | UINT64 ar_csd;
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153 | UINT64 ar_ssd;
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154 | UINT64 ar_cflg;
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155 | UINT64 ar_fsr;
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156 | UINT64 ar_fir;
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157 | UINT64 ar_fdr;
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158 |
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159 | UINT64 ar_ccv;
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160 |
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161 | UINT64 ar_unat;
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162 |
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163 | UINT64 ar_fpsr;
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164 |
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165 | UINT64 ar_pfs;
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166 | UINT64 ar_lc;
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167 | UINT64 ar_ec;
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168 |
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169 | // control registers
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170 | UINT64 cr_dcr;
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171 | UINT64 cr_itm;
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172 | UINT64 cr_iva;
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173 | UINT64 cr_pta;
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174 | UINT64 cr_ipsr;
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175 | UINT64 cr_isr;
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176 | UINT64 cr_iip;
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177 | UINT64 cr_ifa;
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178 | UINT64 cr_itir;
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179 | UINT64 cr_iipa;
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180 | UINT64 cr_ifs;
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181 | UINT64 cr_iim;
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182 | UINT64 cr_iha;
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183 |
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184 | // debug registers
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185 | UINT64 dbr0;
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186 | UINT64 dbr1;
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187 | UINT64 dbr2;
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188 | UINT64 dbr3;
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189 | UINT64 dbr4;
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190 | UINT64 dbr5;
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191 | UINT64 dbr6;
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192 | UINT64 dbr7;
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193 |
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194 | UINT64 ibr0;
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195 | UINT64 ibr1;
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196 | UINT64 ibr2;
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197 | UINT64 ibr3;
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198 | UINT64 ibr4;
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199 | UINT64 ibr5;
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200 | UINT64 ibr6;
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201 | UINT64 ibr7;
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202 |
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203 | // virtual registers
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204 | UINT64 int_nat; // nat bits for R1-R31
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205 |
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206 | } SYSTEM_CONTEXT;
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207 |
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208 | #endif /* _EFI_CONTEXT_H_ */
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