| [e16e8f2] | 1 | FILE_LICENCE ( GPL2_OR_LATER ); |
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| 2 | |
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| 3 | #include <stdint.h> |
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| 4 | #include <gpxe/pci.h> |
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| 5 | |
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| 6 | /** |
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| 7 | * Look for a PCI capability |
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| 8 | * |
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| 9 | * @v pci PCI device to query |
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| 10 | * @v cap Capability code |
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| 11 | * @ret address Address of capability, or 0 if not found |
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| 12 | * |
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| 13 | * Determine whether or not a device supports a given PCI capability. |
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| 14 | * Returns the address of the requested capability structure within |
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| 15 | * the device's PCI configuration space, or 0 if the device does not |
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| 16 | * support it. |
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| 17 | */ |
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| 18 | int pci_find_capability ( struct pci_device *pci, int cap ) { |
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| 19 | uint16_t status; |
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| 20 | uint8_t pos, id; |
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| 21 | uint8_t hdr_type; |
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| 22 | int ttl = 48; |
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| 23 | |
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| 24 | pci_read_config_word ( pci, PCI_STATUS, &status ); |
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| 25 | if ( ! ( status & PCI_STATUS_CAP_LIST ) ) |
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| 26 | return 0; |
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| 27 | |
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| 28 | pci_read_config_byte ( pci, PCI_HEADER_TYPE, &hdr_type ); |
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| 29 | switch ( hdr_type & 0x7F ) { |
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| 30 | case PCI_HEADER_TYPE_NORMAL: |
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| 31 | case PCI_HEADER_TYPE_BRIDGE: |
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| 32 | default: |
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| 33 | pci_read_config_byte ( pci, PCI_CAPABILITY_LIST, &pos ); |
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| 34 | break; |
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| 35 | case PCI_HEADER_TYPE_CARDBUS: |
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| 36 | pci_read_config_byte ( pci, PCI_CB_CAPABILITY_LIST, &pos ); |
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| 37 | break; |
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| 38 | } |
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| 39 | while ( ttl-- && pos >= 0x40 ) { |
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| 40 | pos &= ~3; |
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| 41 | pci_read_config_byte ( pci, pos + PCI_CAP_LIST_ID, &id ); |
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| 42 | DBG ( "PCI Capability: %d\n", id ); |
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| 43 | if ( id == 0xff ) |
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| 44 | break; |
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| 45 | if ( id == cap ) |
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| 46 | return pos; |
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| 47 | pci_read_config_byte ( pci, pos + PCI_CAP_LIST_NEXT, &pos ); |
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| 48 | } |
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| 49 | return 0; |
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| 50 | } |
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| 51 | |
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| 52 | /** |
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| 53 | * Find the size of a PCI BAR |
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| 54 | * |
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| 55 | * @v pci PCI device |
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| 56 | * @v reg PCI register number |
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| 57 | * @ret size BAR size |
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| 58 | * |
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| 59 | * It should not be necessary for any Etherboot code to call this |
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| 60 | * function. |
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| 61 | */ |
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| 62 | unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg ) { |
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| 63 | uint16_t cmd; |
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| 64 | uint32_t start, size; |
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| 65 | |
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| 66 | /* Save the original command register */ |
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| 67 | pci_read_config_word ( pci, PCI_COMMAND, &cmd ); |
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| 68 | /* Save the original bar */ |
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| 69 | pci_read_config_dword ( pci, reg, &start ); |
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| 70 | /* Compute which bits can be set */ |
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| 71 | pci_write_config_dword ( pci, reg, ~0 ); |
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| 72 | pci_read_config_dword ( pci, reg, &size ); |
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| 73 | /* Restore the original size */ |
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| 74 | pci_write_config_dword ( pci, reg, start ); |
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| 75 | /* Find the significant bits */ |
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| 76 | /* Restore the original command register. This reenables decoding. */ |
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| 77 | pci_write_config_word ( pci, PCI_COMMAND, cmd ); |
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| 78 | if ( start & PCI_BASE_ADDRESS_SPACE_IO ) { |
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| 79 | size &= PCI_BASE_ADDRESS_IO_MASK; |
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| 80 | } else { |
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| 81 | size &= PCI_BASE_ADDRESS_MEM_MASK; |
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| 82 | } |
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| 83 | /* Find the lowest bit set */ |
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| 84 | size = size & ~( size - 1 ); |
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| 85 | return size; |
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| 86 | } |
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