[e16e8f2] | 1 | #ifndef _HERMON_H |
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| 2 | #define _HERMON_H |
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| 3 | |
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| 4 | /** @file |
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| 5 | * |
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| 6 | * Mellanox Hermon Infiniband HCA driver |
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| 7 | * |
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| 8 | */ |
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| 9 | |
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| 10 | FILE_LICENCE ( GPL2_OR_LATER ); |
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| 11 | |
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| 12 | #include <stdint.h> |
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| 13 | #include <gpxe/uaccess.h> |
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| 14 | #include <gpxe/ib_packet.h> |
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| 15 | #include "mlx_bitops.h" |
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| 16 | #include "MT25408_PRM.h" |
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| 17 | |
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| 18 | /* |
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| 19 | * Hardware constants |
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| 20 | * |
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| 21 | */ |
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| 22 | |
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| 23 | /* Ports in existence */ |
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| 24 | #define HERMON_MAX_PORTS 2 |
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| 25 | #define HERMON_PORT_BASE 1 |
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| 26 | |
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| 27 | /* PCI BARs */ |
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| 28 | #define HERMON_PCI_CONFIG_BAR PCI_BASE_ADDRESS_0 |
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| 29 | #define HERMON_PCI_CONFIG_BAR_SIZE 0x100000 |
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| 30 | #define HERMON_PCI_UAR_BAR PCI_BASE_ADDRESS_2 |
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| 31 | |
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| 32 | /* Device reset */ |
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| 33 | #define HERMON_RESET_OFFSET 0x0f0010 |
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| 34 | #define HERMON_RESET_MAGIC 0x01000000UL |
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| 35 | #define HERMON_RESET_WAIT_TIME_MS 1000 |
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| 36 | |
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| 37 | /* Work queue entry and completion queue entry opcodes */ |
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| 38 | #define HERMON_OPCODE_NOP 0x00 |
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| 39 | #define HERMON_OPCODE_SEND 0x0a |
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| 40 | #define HERMON_OPCODE_RECV_ERROR 0xfe |
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| 41 | #define HERMON_OPCODE_SEND_ERROR 0xff |
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| 42 | |
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| 43 | /* HCA command register opcodes */ |
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| 44 | #define HERMON_HCR_QUERY_DEV_CAP 0x0003 |
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| 45 | #define HERMON_HCR_QUERY_FW 0x0004 |
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| 46 | #define HERMON_HCR_INIT_HCA 0x0007 |
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| 47 | #define HERMON_HCR_CLOSE_HCA 0x0008 |
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| 48 | #define HERMON_HCR_INIT_PORT 0x0009 |
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| 49 | #define HERMON_HCR_CLOSE_PORT 0x000a |
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| 50 | #define HERMON_HCR_SW2HW_MPT 0x000d |
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| 51 | #define HERMON_HCR_WRITE_MTT 0x0011 |
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| 52 | #define HERMON_HCR_MAP_EQ 0x0012 |
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| 53 | #define HERMON_HCR_SW2HW_EQ 0x0013 |
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| 54 | #define HERMON_HCR_HW2SW_EQ 0x0014 |
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| 55 | #define HERMON_HCR_QUERY_EQ 0x0015 |
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| 56 | #define HERMON_HCR_SW2HW_CQ 0x0016 |
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| 57 | #define HERMON_HCR_HW2SW_CQ 0x0017 |
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| 58 | #define HERMON_HCR_RST2INIT_QP 0x0019 |
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| 59 | #define HERMON_HCR_INIT2RTR_QP 0x001a |
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| 60 | #define HERMON_HCR_RTR2RTS_QP 0x001b |
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| 61 | #define HERMON_HCR_RTS2RTS_QP 0x001c |
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| 62 | #define HERMON_HCR_2RST_QP 0x0021 |
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| 63 | #define HERMON_HCR_QUERY_QP 0x0022 |
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| 64 | #define HERMON_HCR_CONF_SPECIAL_QP 0x0023 |
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| 65 | #define HERMON_HCR_MAD_IFC 0x0024 |
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| 66 | #define HERMON_HCR_READ_MCG 0x0025 |
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| 67 | #define HERMON_HCR_WRITE_MCG 0x0026 |
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| 68 | #define HERMON_HCR_MGID_HASH 0x0027 |
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| 69 | #define HERMON_HCR_SENSE_PORT 0x004d |
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| 70 | #define HERMON_HCR_RUN_FW 0x0ff6 |
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| 71 | #define HERMON_HCR_DISABLE_LAM 0x0ff7 |
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| 72 | #define HERMON_HCR_ENABLE_LAM 0x0ff8 |
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| 73 | #define HERMON_HCR_UNMAP_ICM 0x0ff9 |
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| 74 | #define HERMON_HCR_MAP_ICM 0x0ffa |
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| 75 | #define HERMON_HCR_UNMAP_ICM_AUX 0x0ffb |
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| 76 | #define HERMON_HCR_MAP_ICM_AUX 0x0ffc |
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| 77 | #define HERMON_HCR_SET_ICM_SIZE 0x0ffd |
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| 78 | #define HERMON_HCR_UNMAP_FA 0x0ffe |
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| 79 | #define HERMON_HCR_MAP_FA 0x0fff |
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| 80 | |
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| 81 | /* Service types */ |
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| 82 | #define HERMON_ST_RC 0x00 |
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| 83 | #define HERMON_ST_UD 0x03 |
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| 84 | #define HERMON_ST_MLX 0x07 |
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| 85 | |
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| 86 | /* MTUs */ |
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| 87 | #define HERMON_MTU_2048 0x04 |
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| 88 | |
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| 89 | #define HERMON_INVALID_LKEY 0x00000100UL |
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| 90 | |
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| 91 | #define HERMON_PAGE_SIZE 4096 |
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| 92 | |
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| 93 | #define HERMON_DB_POST_SND_OFFSET 0x14 |
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| 94 | #define HERMON_DB_EQ_OFFSET(_eqn) \ |
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| 95 | ( 0x800 + HERMON_PAGE_SIZE * ( (_eqn) / 4 ) + 0x08 * ( (_eqn) % 4 ) ) |
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| 96 | |
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| 97 | #define HERMON_QP_OPT_PARAM_PM_STATE 0x00000400UL |
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| 98 | #define HERMON_QP_OPT_PARAM_QKEY 0x00000020UL |
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| 99 | #define HERMON_QP_OPT_PARAM_ALT_PATH 0x00000001UL |
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| 100 | |
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| 101 | #define HERMON_MAP_EQ ( 0UL << 31 ) |
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| 102 | #define HERMON_UNMAP_EQ ( 1UL << 31 ) |
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| 103 | |
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| 104 | #define HERMON_EV_PORT_STATE_CHANGE 0x09 |
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| 105 | |
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| 106 | #define HERMON_SCHED_QP0 0x3f |
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| 107 | #define HERMON_SCHED_DEFAULT 0x83 |
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| 108 | |
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| 109 | #define HERMON_PM_STATE_ARMED 0x00 |
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| 110 | #define HERMON_PM_STATE_REARM 0x01 |
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| 111 | #define HERMON_PM_STATE_MIGRATED 0x03 |
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| 112 | |
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| 113 | #define HERMON_RETRY_MAX 0x07 |
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| 114 | |
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| 115 | /* |
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| 116 | * Datatypes that seem to be missing from the autogenerated documentation |
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| 117 | * |
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| 118 | */ |
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| 119 | struct hermonprm_mgm_hash_st { |
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| 120 | pseudo_bit_t reserved0[0x00020]; |
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| 121 | /* -------------- */ |
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| 122 | pseudo_bit_t hash[0x00010]; |
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| 123 | pseudo_bit_t reserved1[0x00010]; |
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| 124 | } __attribute__ (( packed )); |
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| 125 | |
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| 126 | struct hermonprm_mcg_entry_st { |
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| 127 | struct hermonprm_mcg_hdr_st hdr; |
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| 128 | struct hermonprm_mcg_qp_dw_st qp[8]; |
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| 129 | } __attribute__ (( packed )); |
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| 130 | |
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| 131 | struct hermonprm_cq_db_record_st { |
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| 132 | pseudo_bit_t update_ci[0x00018]; |
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| 133 | pseudo_bit_t reserved0[0x00008]; |
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| 134 | /* -------------- */ |
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| 135 | pseudo_bit_t arm_ci[0x00018]; |
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| 136 | pseudo_bit_t cmd[0x00003]; |
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| 137 | pseudo_bit_t reserved1[0x00001]; |
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| 138 | pseudo_bit_t cmd_sn[0x00002]; |
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| 139 | pseudo_bit_t reserved2[0x00002]; |
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| 140 | } __attribute__ (( packed )); |
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| 141 | |
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| 142 | struct hermonprm_send_db_register_st { |
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| 143 | pseudo_bit_t reserved[0x00008]; |
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| 144 | pseudo_bit_t qn[0x00018]; |
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| 145 | } __attribute__ (( packed )); |
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| 146 | |
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| 147 | struct hermonprm_event_db_register_st { |
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| 148 | pseudo_bit_t ci[0x00018]; |
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| 149 | pseudo_bit_t reserver[0x00007]; |
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| 150 | pseudo_bit_t a[0x00001]; |
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| 151 | } __attribute__ (( packed )); |
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| 152 | |
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| 153 | struct hermonprm_scalar_parameter_st { |
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| 154 | pseudo_bit_t value_hi[0x00020]; |
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| 155 | /* -------------- */ |
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| 156 | pseudo_bit_t value[0x00020]; |
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| 157 | } __attribute__ (( packed )); |
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| 158 | |
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| 159 | struct hermonprm_event_mask_st { |
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| 160 | pseudo_bit_t reserved0[0x00020]; |
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| 161 | /* -------------- */ |
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| 162 | pseudo_bit_t completion[0x00001]; |
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| 163 | pseudo_bit_t reserved1[0x0008]; |
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| 164 | pseudo_bit_t port_state_change[0x00001]; |
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| 165 | pseudo_bit_t reserved2[0x00016]; |
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| 166 | } __attribute__ (( packed )); |
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| 167 | |
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| 168 | struct hermonprm_port_state_change_event_st { |
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| 169 | pseudo_bit_t reserved[0x00020]; |
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| 170 | struct hermonprm_port_state_change_st data; |
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| 171 | } __attribute__ (( packed )); |
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| 172 | |
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| 173 | /** Hermon sense port */ |
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| 174 | struct hermonprm_sense_port_st { |
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| 175 | pseudo_bit_t port_type[0x00020]; |
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| 176 | /* -------------- */ |
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| 177 | pseudo_bit_t reserved[0x00020]; |
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| 178 | }; |
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| 179 | #define HERMON_PORT_TYPE_IB 1 |
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| 180 | |
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| 181 | /* |
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| 182 | * Wrapper structures for hardware datatypes |
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| 183 | * |
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| 184 | */ |
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| 185 | |
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| 186 | struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_context ); |
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| 187 | struct MLX_DECLARE_STRUCT ( hermonprm_completion_queue_entry ); |
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| 188 | struct MLX_DECLARE_STRUCT ( hermonprm_completion_with_error ); |
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| 189 | struct MLX_DECLARE_STRUCT ( hermonprm_cq_db_record ); |
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| 190 | struct MLX_DECLARE_STRUCT ( hermonprm_eqc ); |
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| 191 | struct MLX_DECLARE_STRUCT ( hermonprm_event_db_register ); |
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| 192 | struct MLX_DECLARE_STRUCT ( hermonprm_event_mask ); |
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| 193 | struct MLX_DECLARE_STRUCT ( hermonprm_event_queue_entry ); |
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| 194 | struct MLX_DECLARE_STRUCT ( hermonprm_hca_command_register ); |
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| 195 | struct MLX_DECLARE_STRUCT ( hermonprm_init_hca ); |
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| 196 | struct MLX_DECLARE_STRUCT ( hermonprm_init_port ); |
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| 197 | struct MLX_DECLARE_STRUCT ( hermonprm_mad_ifc ); |
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| 198 | struct MLX_DECLARE_STRUCT ( hermonprm_mcg_entry ); |
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| 199 | struct MLX_DECLARE_STRUCT ( hermonprm_mgm_hash ); |
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| 200 | struct MLX_DECLARE_STRUCT ( hermonprm_mpt ); |
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| 201 | struct MLX_DECLARE_STRUCT ( hermonprm_mtt ); |
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| 202 | struct MLX_DECLARE_STRUCT ( hermonprm_port_state_change_event ); |
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| 203 | struct MLX_DECLARE_STRUCT ( hermonprm_qp_db_record ); |
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| 204 | struct MLX_DECLARE_STRUCT ( hermonprm_qp_ee_state_transitions ); |
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| 205 | struct MLX_DECLARE_STRUCT ( hermonprm_query_dev_cap ); |
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| 206 | struct MLX_DECLARE_STRUCT ( hermonprm_query_fw ); |
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| 207 | struct MLX_DECLARE_STRUCT ( hermonprm_queue_pair_ee_context_entry ); |
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| 208 | struct MLX_DECLARE_STRUCT ( hermonprm_scalar_parameter ); |
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| 209 | struct MLX_DECLARE_STRUCT ( hermonprm_sense_port ); |
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| 210 | struct MLX_DECLARE_STRUCT ( hermonprm_send_db_register ); |
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| 211 | struct MLX_DECLARE_STRUCT ( hermonprm_ud_address_vector ); |
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| 212 | struct MLX_DECLARE_STRUCT ( hermonprm_virtual_physical_mapping ); |
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| 213 | struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ctrl_mlx ); |
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| 214 | struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ctrl_send ); |
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| 215 | struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_data_ptr ); |
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| 216 | struct MLX_DECLARE_STRUCT ( hermonprm_wqe_segment_ud ); |
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| 217 | |
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| 218 | /* |
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| 219 | * Composite hardware datatypes |
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| 220 | * |
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| 221 | */ |
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| 222 | |
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| 223 | struct hermonprm_write_mtt { |
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| 224 | struct hermonprm_scalar_parameter mtt_base_addr; |
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| 225 | struct hermonprm_scalar_parameter reserved; |
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| 226 | struct hermonprm_mtt mtt; |
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| 227 | } __attribute__ (( packed )); |
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| 228 | |
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| 229 | #define HERMON_MAX_GATHER 2 |
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| 230 | |
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| 231 | struct hermonprm_ud_send_wqe { |
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| 232 | struct hermonprm_wqe_segment_ctrl_send ctrl; |
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| 233 | struct hermonprm_wqe_segment_ud ud; |
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| 234 | struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; |
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| 235 | } __attribute__ (( packed )); |
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| 236 | |
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| 237 | struct hermonprm_mlx_send_wqe { |
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| 238 | struct hermonprm_wqe_segment_ctrl_mlx ctrl; |
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| 239 | struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; |
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| 240 | uint8_t headers[IB_MAX_HEADER_SIZE]; |
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| 241 | } __attribute__ (( packed )); |
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| 242 | |
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| 243 | struct hermonprm_rc_send_wqe { |
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| 244 | struct hermonprm_wqe_segment_ctrl_send ctrl; |
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| 245 | struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_GATHER]; |
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| 246 | } __attribute__ (( packed )); |
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| 247 | |
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| 248 | #define HERMON_MAX_SCATTER 1 |
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| 249 | |
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| 250 | struct hermonprm_recv_wqe { |
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| 251 | struct hermonprm_wqe_segment_data_ptr data[HERMON_MAX_SCATTER]; |
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| 252 | } __attribute__ (( packed )); |
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| 253 | |
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| 254 | union hermonprm_completion_entry { |
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| 255 | struct hermonprm_completion_queue_entry normal; |
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| 256 | struct hermonprm_completion_with_error error; |
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| 257 | } __attribute__ (( packed )); |
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| 258 | |
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| 259 | union hermonprm_event_entry { |
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| 260 | struct hermonprm_event_queue_entry generic; |
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| 261 | struct hermonprm_port_state_change_event port_state_change; |
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| 262 | } __attribute__ (( packed )); |
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| 263 | |
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| 264 | union hermonprm_doorbell_register { |
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| 265 | struct hermonprm_send_db_register send; |
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| 266 | struct hermonprm_event_db_register event; |
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| 267 | uint32_t dword[1]; |
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| 268 | } __attribute__ (( packed )); |
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| 269 | |
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| 270 | union hermonprm_mad { |
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| 271 | struct hermonprm_mad_ifc ifc; |
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| 272 | union ib_mad mad; |
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| 273 | } __attribute__ (( packed )); |
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| 274 | |
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| 275 | /* |
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| 276 | * gPXE-specific definitions |
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| 277 | * |
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| 278 | */ |
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| 279 | |
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| 280 | /** Hermon device capabilitiess */ |
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| 281 | struct hermon_dev_cap { |
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| 282 | /** CMPT entry size */ |
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| 283 | size_t cmpt_entry_size; |
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| 284 | /** Number of reserved QPs */ |
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| 285 | unsigned int reserved_qps; |
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| 286 | /** QP context entry size */ |
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| 287 | size_t qpc_entry_size; |
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| 288 | /** Alternate path context entry size */ |
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| 289 | size_t altc_entry_size; |
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| 290 | /** Auxiliary context entry size */ |
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| 291 | size_t auxc_entry_size; |
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| 292 | /** Number of reserved SRQs */ |
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| 293 | unsigned int reserved_srqs; |
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| 294 | /** SRQ context entry size */ |
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| 295 | size_t srqc_entry_size; |
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| 296 | /** Number of reserved CQs */ |
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| 297 | unsigned int reserved_cqs; |
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| 298 | /** CQ context entry size */ |
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| 299 | size_t cqc_entry_size; |
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| 300 | /** Number of reserved EQs */ |
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| 301 | unsigned int reserved_eqs; |
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| 302 | /** EQ context entry size */ |
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| 303 | size_t eqc_entry_size; |
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| 304 | /** Number of reserved MTTs */ |
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| 305 | unsigned int reserved_mtts; |
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| 306 | /** MTT entry size */ |
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| 307 | size_t mtt_entry_size; |
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| 308 | /** Number of reserved MRWs */ |
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| 309 | unsigned int reserved_mrws; |
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| 310 | /** DMPT entry size */ |
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| 311 | size_t dmpt_entry_size; |
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| 312 | /** Number of reserved UARs */ |
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| 313 | unsigned int reserved_uars; |
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| 314 | /** Number of ports */ |
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| 315 | unsigned int num_ports; |
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| 316 | /** Dual-port different protocol */ |
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| 317 | int dpdp; |
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| 318 | }; |
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| 319 | |
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| 320 | /** Number of cMPT entries of each type */ |
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| 321 | #define HERMON_CMPT_MAX_ENTRIES ( 1 << 24 ) |
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| 322 | |
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| 323 | /** Hermon ICM memory map entry */ |
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| 324 | struct hermon_icm_map { |
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| 325 | /** Offset (virtual address within ICM) */ |
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| 326 | uint64_t offset; |
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| 327 | /** Length */ |
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| 328 | size_t len; |
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| 329 | }; |
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| 330 | |
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| 331 | /** Discontiguous regions within Hermon ICM */ |
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| 332 | enum hermon_icm_map_regions { |
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| 333 | HERMON_ICM_QP_CMPT = 0, |
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| 334 | HERMON_ICM_SRQ_CMPT, |
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| 335 | HERMON_ICM_CQ_CMPT, |
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| 336 | HERMON_ICM_EQ_CMPT, |
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| 337 | HERMON_ICM_OTHER, |
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| 338 | HERMON_ICM_NUM_REGIONS |
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| 339 | }; |
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| 340 | |
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| 341 | /** UAR page for doorbell accesses |
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| 342 | * |
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| 343 | * Pages 0-127 are reserved for event queue doorbells only, so we use |
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| 344 | * page 128. |
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| 345 | */ |
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| 346 | #define HERMON_UAR_NON_EQ_PAGE 128 |
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| 347 | |
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| 348 | /** Maximum number of allocatable MTT entries |
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| 349 | * |
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| 350 | * This is a policy decision, not a device limit. |
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| 351 | */ |
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| 352 | #define HERMON_MAX_MTTS 64 |
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| 353 | |
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| 354 | /** A Hermon MTT descriptor */ |
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| 355 | struct hermon_mtt { |
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| 356 | /** MTT offset */ |
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| 357 | unsigned int mtt_offset; |
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| 358 | /** Number of pages */ |
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| 359 | unsigned int num_pages; |
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| 360 | /** MTT base address */ |
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| 361 | unsigned int mtt_base_addr; |
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| 362 | /** Offset within page */ |
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| 363 | unsigned int page_offset; |
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| 364 | }; |
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| 365 | |
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| 366 | /** Alignment of Hermon send work queue entries */ |
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| 367 | #define HERMON_SEND_WQE_ALIGN 128 |
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| 368 | |
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| 369 | /** A Hermon send work queue entry */ |
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| 370 | union hermon_send_wqe { |
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| 371 | struct hermonprm_wqe_segment_ctrl_send ctrl; |
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| 372 | struct hermonprm_ud_send_wqe ud; |
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| 373 | struct hermonprm_mlx_send_wqe mlx; |
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| 374 | struct hermonprm_rc_send_wqe rc; |
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| 375 | uint8_t force_align[HERMON_SEND_WQE_ALIGN]; |
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| 376 | } __attribute__ (( packed )); |
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| 377 | |
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| 378 | /** A Hermon send work queue */ |
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| 379 | struct hermon_send_work_queue { |
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| 380 | /** Number of work queue entries, including headroom |
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| 381 | * |
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| 382 | * Hermon requires us to leave unused space within the send |
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| 383 | * WQ, so we create a send WQ with more entries than are |
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| 384 | * requested in the create_qp() call. |
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| 385 | */ |
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| 386 | unsigned int num_wqes; |
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| 387 | /** Work queue entries */ |
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| 388 | union hermon_send_wqe *wqe; |
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| 389 | /** Size of work queue */ |
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| 390 | size_t wqe_size; |
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| 391 | /** Doorbell register */ |
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| 392 | void *doorbell; |
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| 393 | }; |
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| 394 | |
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| 395 | /** Alignment of Hermon receive work queue entries */ |
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| 396 | #define HERMON_RECV_WQE_ALIGN 16 |
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| 397 | |
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| 398 | /** A Hermon receive work queue entry */ |
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| 399 | union hermon_recv_wqe { |
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| 400 | struct hermonprm_recv_wqe recv; |
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| 401 | uint8_t force_align[HERMON_RECV_WQE_ALIGN]; |
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| 402 | } __attribute__ (( packed )); |
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| 403 | |
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| 404 | /** A Hermon receive work queue */ |
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| 405 | struct hermon_recv_work_queue { |
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| 406 | /** Work queue entries */ |
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| 407 | union hermon_recv_wqe *wqe; |
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| 408 | /** Size of work queue */ |
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| 409 | size_t wqe_size; |
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| 410 | /** Doorbell */ |
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| 411 | struct hermonprm_qp_db_record doorbell __attribute__ (( aligned (4) )); |
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| 412 | }; |
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| 413 | |
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| 414 | /** Number of special queue pairs */ |
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| 415 | #define HERMON_NUM_SPECIAL_QPS 8 |
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| 416 | |
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| 417 | /** Number of queue pairs reserved for the "special QP" block |
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| 418 | * |
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| 419 | * The special QPs must be within a contiguous block aligned on its |
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| 420 | * own size. |
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| 421 | */ |
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| 422 | #define HERMON_RSVD_SPECIAL_QPS ( ( HERMON_NUM_SPECIAL_QPS << 1 ) - 1 ) |
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| 423 | |
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| 424 | /** Maximum number of allocatable queue pairs |
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| 425 | * |
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| 426 | * This is a policy decision, not a device limit. |
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| 427 | */ |
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| 428 | #define HERMON_MAX_QPS 8 |
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| 429 | |
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| 430 | /** Queue pair number randomisation mask */ |
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| 431 | #define HERMON_QPN_RANDOM_MASK 0xfff000 |
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| 432 | |
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| 433 | /** Hermon queue pair state */ |
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| 434 | enum hermon_queue_pair_state { |
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| 435 | HERMON_QP_ST_RST = 0, |
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| 436 | HERMON_QP_ST_INIT, |
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| 437 | HERMON_QP_ST_RTR, |
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| 438 | HERMON_QP_ST_RTS, |
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| 439 | }; |
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| 440 | |
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| 441 | /** A Hermon queue pair */ |
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| 442 | struct hermon_queue_pair { |
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| 443 | /** Work queue buffer */ |
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| 444 | void *wqe; |
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| 445 | /** Size of work queue buffer */ |
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| 446 | size_t wqe_size; |
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| 447 | /** MTT descriptor */ |
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| 448 | struct hermon_mtt mtt; |
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| 449 | /** Send work queue */ |
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| 450 | struct hermon_send_work_queue send; |
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| 451 | /** Receive work queue */ |
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| 452 | struct hermon_recv_work_queue recv; |
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| 453 | /** Queue state */ |
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| 454 | enum hermon_queue_pair_state state; |
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| 455 | }; |
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| 456 | |
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| 457 | /** Maximum number of allocatable completion queues |
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| 458 | * |
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| 459 | * This is a policy decision, not a device limit. |
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| 460 | */ |
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| 461 | #define HERMON_MAX_CQS 8 |
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| 462 | |
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| 463 | /** A Hermon completion queue */ |
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| 464 | struct hermon_completion_queue { |
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| 465 | /** Completion queue entries */ |
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| 466 | union hermonprm_completion_entry *cqe; |
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| 467 | /** Size of completion queue */ |
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| 468 | size_t cqe_size; |
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| 469 | /** MTT descriptor */ |
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| 470 | struct hermon_mtt mtt; |
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| 471 | /** Doorbell */ |
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| 472 | struct hermonprm_cq_db_record doorbell __attribute__ (( aligned (8) )); |
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| 473 | }; |
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| 474 | |
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| 475 | /** Maximum number of allocatable event queues |
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| 476 | * |
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| 477 | * This is a policy decision, not a device limit. |
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| 478 | */ |
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| 479 | #define HERMON_MAX_EQS 8 |
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| 480 | |
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| 481 | /** A Hermon event queue */ |
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| 482 | struct hermon_event_queue { |
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| 483 | /** Event queue entries */ |
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| 484 | union hermonprm_event_entry *eqe; |
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| 485 | /** Size of event queue */ |
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| 486 | size_t eqe_size; |
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| 487 | /** MTT descriptor */ |
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| 488 | struct hermon_mtt mtt; |
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| 489 | /** Event queue number */ |
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| 490 | unsigned long eqn; |
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| 491 | /** Next event queue entry index */ |
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| 492 | unsigned long next_idx; |
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| 493 | /** Doorbell register */ |
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| 494 | void *doorbell; |
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| 495 | }; |
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| 496 | |
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| 497 | /** Number of event queue entries |
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| 498 | * |
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| 499 | * This is a policy decision. |
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| 500 | */ |
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| 501 | #define HERMON_NUM_EQES 4 |
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| 502 | |
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| 503 | /** A Hermon resource bitmask */ |
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| 504 | typedef uint32_t hermon_bitmask_t; |
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| 505 | |
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| 506 | /** Size of a hermon resource bitmask */ |
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| 507 | #define HERMON_BITMASK_SIZE(max_entries) \ |
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| 508 | ( ( (max_entries) + ( 8 * sizeof ( hermon_bitmask_t ) ) - 1 ) / \ |
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| 509 | ( 8 * sizeof ( hermon_bitmask_t ) ) ) |
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| 510 | |
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| 511 | /** A Hermon device */ |
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| 512 | struct hermon { |
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| 513 | /** PCI configuration registers */ |
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| 514 | void *config; |
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| 515 | /** PCI user Access Region */ |
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| 516 | void *uar; |
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| 517 | |
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| 518 | /** Command toggle */ |
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| 519 | unsigned int toggle; |
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| 520 | /** Command input mailbox */ |
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| 521 | void *mailbox_in; |
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| 522 | /** Command output mailbox */ |
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| 523 | void *mailbox_out; |
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| 524 | |
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| 525 | /** Firmware area in external memory */ |
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| 526 | userptr_t firmware_area; |
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| 527 | /** ICM map */ |
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| 528 | struct hermon_icm_map icm_map[HERMON_ICM_NUM_REGIONS]; |
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| 529 | /** ICM area */ |
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| 530 | userptr_t icm; |
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| 531 | |
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| 532 | /** Event queue */ |
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| 533 | struct hermon_event_queue eq; |
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| 534 | /** Unrestricted LKey |
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| 535 | * |
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| 536 | * Used to get unrestricted memory access. |
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| 537 | */ |
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| 538 | unsigned long lkey; |
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| 539 | |
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| 540 | /** Completion queue in-use bitmask */ |
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| 541 | hermon_bitmask_t cq_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_CQS ) ]; |
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| 542 | /** Queue pair in-use bitmask */ |
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| 543 | hermon_bitmask_t qp_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_QPS ) ]; |
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| 544 | /** MTT entry in-use bitmask */ |
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| 545 | hermon_bitmask_t mtt_inuse[ HERMON_BITMASK_SIZE ( HERMON_MAX_MTTS ) ]; |
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| 546 | |
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| 547 | /** Device capabilities */ |
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| 548 | struct hermon_dev_cap cap; |
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| 549 | /** Special QPN base */ |
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| 550 | unsigned long special_qpn_base; |
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| 551 | /** QPN base */ |
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| 552 | unsigned long qpn_base; |
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| 553 | |
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| 554 | /** Infiniband devices */ |
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| 555 | struct ib_device *ibdev[HERMON_MAX_PORTS]; |
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| 556 | }; |
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| 557 | |
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| 558 | /** Global protection domain */ |
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| 559 | #define HERMON_GLOBAL_PD 0x123456 |
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| 560 | |
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| 561 | /** Memory key prefix */ |
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| 562 | #define HERMON_MKEY_PREFIX 0x77000000UL |
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| 563 | |
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| 564 | /* |
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| 565 | * HCA commands |
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| 566 | * |
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| 567 | */ |
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| 568 | |
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| 569 | #define HERMON_HCR_BASE 0x80680 |
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| 570 | #define HERMON_HCR_REG(x) ( HERMON_HCR_BASE + 4 * (x) ) |
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| 571 | #define HERMON_HCR_MAX_WAIT_MS 2000 |
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| 572 | #define HERMON_MBOX_ALIGN 4096 |
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| 573 | #define HERMON_MBOX_SIZE 512 |
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| 574 | |
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| 575 | /* HCA command is split into |
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| 576 | * |
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| 577 | * bits 11:0 Opcode |
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| 578 | * bit 12 Input uses mailbox |
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| 579 | * bit 13 Output uses mailbox |
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| 580 | * bits 22:14 Input parameter length (in dwords) |
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| 581 | * bits 31:23 Output parameter length (in dwords) |
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| 582 | * |
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| 583 | * Encoding the information in this way allows us to cut out several |
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| 584 | * parameters to the hermon_command() call. |
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| 585 | */ |
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| 586 | #define HERMON_HCR_IN_MBOX 0x00001000UL |
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| 587 | #define HERMON_HCR_OUT_MBOX 0x00002000UL |
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| 588 | #define HERMON_HCR_OPCODE( _command ) ( (_command) & 0xfff ) |
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| 589 | #define HERMON_HCR_IN_LEN( _command ) ( ( (_command) >> 12 ) & 0x7fc ) |
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| 590 | #define HERMON_HCR_OUT_LEN( _command ) ( ( (_command) >> 21 ) & 0x7fc ) |
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| 591 | |
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| 592 | /** Build HCR command from component parts */ |
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| 593 | #define HERMON_HCR_INOUT_CMD( _opcode, _in_mbox, _in_len, \ |
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| 594 | _out_mbox, _out_len ) \ |
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| 595 | ( (_opcode) | \ |
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| 596 | ( (_in_mbox) ? HERMON_HCR_IN_MBOX : 0 ) | \ |
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| 597 | ( ( (_in_len) / 4 ) << 14 ) | \ |
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| 598 | ( (_out_mbox) ? HERMON_HCR_OUT_MBOX : 0 ) | \ |
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| 599 | ( ( (_out_len) / 4 ) << 23 ) ) |
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| 600 | |
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| 601 | #define HERMON_HCR_IN_CMD( _opcode, _in_mbox, _in_len ) \ |
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| 602 | HERMON_HCR_INOUT_CMD ( _opcode, _in_mbox, _in_len, 0, 0 ) |
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| 603 | |
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| 604 | #define HERMON_HCR_OUT_CMD( _opcode, _out_mbox, _out_len ) \ |
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| 605 | HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, _out_mbox, _out_len ) |
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| 606 | |
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| 607 | #define HERMON_HCR_VOID_CMD( _opcode ) \ |
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| 608 | HERMON_HCR_INOUT_CMD ( _opcode, 0, 0, 0, 0 ) |
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| 609 | |
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| 610 | #endif /* _HERMON_H */ |
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