source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/ath5k/ath5k.h

Last change on this file was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago

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1/*
2 * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
3 * Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
4 *
5 * Modified for gPXE, July 2009, by Joshua Oreman <oremanj@rwcr.net>
6 * Original from Linux kernel 2.6.30.
7 *
8 * Permission to use, copy, modify, and distribute this software for any
9 * purpose with or without fee is hereby granted, provided that the above
10 * copyright notice and this permission notice appear in all copies.
11 *
12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
19 */
20
21#ifndef _ATH5K_H
22#define _ATH5K_H
23
24FILE_LICENCE ( MIT );
25
26#include <stddef.h>
27#include <byteswap.h>
28#include <gpxe/io.h>
29#include <gpxe/netdevice.h>
30#include <gpxe/net80211.h>
31#include <errno.h>
32
33/* Keep all ath5k files under one errfile ID */
34#undef ERRFILE
35#define ERRFILE ERRFILE_ath5k
36
37#define ARRAY_SIZE(a) (sizeof(a)/sizeof((a)[0]))
38
39/* RX/TX descriptor hw structs */
40#include "desc.h"
41
42/* EEPROM structs/offsets */
43#include "eeprom.h"
44
45/* PCI IDs */
46#define PCI_DEVICE_ID_ATHEROS_AR5210            0x0007 /* AR5210 */
47#define PCI_DEVICE_ID_ATHEROS_AR5311            0x0011 /* AR5311 */
48#define PCI_DEVICE_ID_ATHEROS_AR5211            0x0012 /* AR5211 */
49#define PCI_DEVICE_ID_ATHEROS_AR5212            0x0013 /* AR5212 */
50#define PCI_DEVICE_ID_3COM_3CRDAG675            0x0013 /* 3CRDAG675 (Atheros AR5212) */
51#define PCI_DEVICE_ID_3COM_2_3CRPAG175          0x0013 /* 3CRPAG175 (Atheros AR5212) */
52#define PCI_DEVICE_ID_ATHEROS_AR5210_AP         0x0207 /* AR5210 (Early) */
53#define PCI_DEVICE_ID_ATHEROS_AR5212_IBM        0x1014 /* AR5212 (IBM MiniPCI) */
54#define PCI_DEVICE_ID_ATHEROS_AR5210_DEFAULT    0x1107 /* AR5210 (no eeprom) */
55#define PCI_DEVICE_ID_ATHEROS_AR5212_DEFAULT    0x1113 /* AR5212 (no eeprom) */
56#define PCI_DEVICE_ID_ATHEROS_AR5211_DEFAULT    0x1112 /* AR5211 (no eeprom) */
57#define PCI_DEVICE_ID_ATHEROS_AR5212_FPGA       0xf013 /* AR5212 (emulation board) */
58#define PCI_DEVICE_ID_ATHEROS_AR5211_LEGACY     0xff12 /* AR5211 (emulation board) */
59#define PCI_DEVICE_ID_ATHEROS_AR5211_FPGA11B    0xf11b /* AR5211 (emulation board) */
60#define PCI_DEVICE_ID_ATHEROS_AR5312_REV2       0x0052 /* AR5312 WMAC (AP31) */
61#define PCI_DEVICE_ID_ATHEROS_AR5312_REV7       0x0057 /* AR5312 WMAC (AP30-040) */
62#define PCI_DEVICE_ID_ATHEROS_AR5312_REV8       0x0058 /* AR5312 WMAC (AP43-030) */
63#define PCI_DEVICE_ID_ATHEROS_AR5212_0014       0x0014 /* AR5212 compatible */
64#define PCI_DEVICE_ID_ATHEROS_AR5212_0015       0x0015 /* AR5212 compatible */
65#define PCI_DEVICE_ID_ATHEROS_AR5212_0016       0x0016 /* AR5212 compatible */
66#define PCI_DEVICE_ID_ATHEROS_AR5212_0017       0x0017 /* AR5212 compatible */
67#define PCI_DEVICE_ID_ATHEROS_AR5212_0018       0x0018 /* AR5212 compatible */
68#define PCI_DEVICE_ID_ATHEROS_AR5212_0019       0x0019 /* AR5212 compatible */
69#define PCI_DEVICE_ID_ATHEROS_AR2413            0x001a /* AR2413 (Griffin-lite) */
70#define PCI_DEVICE_ID_ATHEROS_AR5413            0x001b /* AR5413 (Eagle) */
71#define PCI_DEVICE_ID_ATHEROS_AR5424            0x001c /* AR5424 (Condor PCI-E) */
72#define PCI_DEVICE_ID_ATHEROS_AR5416            0x0023 /* AR5416 */
73#define PCI_DEVICE_ID_ATHEROS_AR5418            0x0024 /* AR5418 */
74
75/****************************\
76  GENERIC DRIVER DEFINITIONS
77\****************************/
78
79/*
80 * AR5K REGISTER ACCESS
81 */
82
83/* Some macros to read/write fields */
84
85/* First shift, then mask */
86#define AR5K_REG_SM(_val, _flags)                                       \
87        (((_val) << _flags##_S) & (_flags))
88
89/* First mask, then shift */
90#define AR5K_REG_MS(_val, _flags)                                       \
91        (((_val) & (_flags)) >> _flags##_S)
92
93/* Some registers can hold multiple values of interest. For this
94 * reason when we want to write to these registers we must first
95 * retrieve the values which we do not want to clear (lets call this
96 * old_data) and then set the register with this and our new_value:
97 * ( old_data | new_value) */
98#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val)                     \
99        ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
100            (((_val) << _flags##_S) & (_flags)), _reg)
101
102#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask)                   \
103        ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) &           \
104                        (_mask)) | (_flags), _reg)
105
106#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags)                          \
107        ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
108
109#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags)                 \
110        ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
111
112/* Access to PHY registers */
113#define AR5K_PHY_READ(ah, _reg)                                 \
114        ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
115
116#define AR5K_PHY_WRITE(ah, _reg, _val)                                  \
117        ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
118
119/* Access QCU registers per queue */
120#define AR5K_REG_READ_Q(ah, _reg, _queue)                               \
121        (ath5k_hw_reg_read(ah, _reg) & (1 << _queue))                   \
122
123#define AR5K_REG_WRITE_Q(ah, _reg, _queue)                              \
124        ath5k_hw_reg_write(ah, (1 << _queue), _reg)
125
126#define AR5K_Q_ENABLE_BITS(_reg, _queue) do {                           \
127        _reg |= 1 << _queue;                                            \
128} while (0)
129
130#define AR5K_Q_DISABLE_BITS(_reg, _queue) do {                          \
131        _reg &= ~(1 << _queue);                                         \
132} while (0)
133
134/* Used while writing initvals */
135#define AR5K_REG_WAIT(_i) do {                                          \
136        if (_i % 64)                                                    \
137                udelay(1);                                              \
138} while (0)
139
140/* Register dumps are done per operation mode */
141#define AR5K_INI_RFGAIN_5GHZ            0
142#define AR5K_INI_RFGAIN_2GHZ            1
143
144/* TODO: Clean this up */
145#define AR5K_INI_VAL_11A                0
146#define AR5K_INI_VAL_11A_TURBO          1
147#define AR5K_INI_VAL_11B                2
148#define AR5K_INI_VAL_11G                3
149#define AR5K_INI_VAL_11G_TURBO          4
150#define AR5K_INI_VAL_XR                 0
151#define AR5K_INI_VAL_MAX                5
152
153/* Used for BSSID etc manipulation */
154#define AR5K_LOW_ID(_a)(                                \
155(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24  \
156)
157
158#define AR5K_HIGH_ID(_a)        ((_a)[4] | (_a)[5] << 8)
159
160#define IEEE80211_MAX_LEN       2352
161
162/*
163 * Some tuneable values (these should be changeable by the user)
164 */
165#define AR5K_TUNE_DMA_BEACON_RESP               2
166#define AR5K_TUNE_SW_BEACON_RESP                10
167#define AR5K_TUNE_ADDITIONAL_SWBA_BACKOFF       0
168#define AR5K_TUNE_RADAR_ALERT                   0
169#define AR5K_TUNE_MIN_TX_FIFO_THRES             1
170#define AR5K_TUNE_MAX_TX_FIFO_THRES             ((IEEE80211_MAX_LEN / 64) + 1)
171#define AR5K_TUNE_REGISTER_TIMEOUT              20000
172/* Register for RSSI threshold has a mask of 0xff, so 255 seems to
173 * be the max value. */
174#define AR5K_TUNE_RSSI_THRES                    129
175/* This must be set when setting the RSSI threshold otherwise it can
176 * prevent a reset. If AR5K_RSSI_THR is read after writing to it
177 * the BMISS_THRES will be seen as 0, seems harware doesn't keep
178 * track of it. Max value depends on harware. For AR5210 this is just 7.
179 * For AR5211+ this seems to be up to 255. */
180#define AR5K_TUNE_BMISS_THRES                   7
181#define AR5K_TUNE_REGISTER_DWELL_TIME           20000
182#define AR5K_TUNE_BEACON_INTERVAL               100
183#define AR5K_TUNE_AIFS                          2
184#define AR5K_TUNE_AIFS_11B                      2
185#define AR5K_TUNE_AIFS_XR                       0
186#define AR5K_TUNE_CWMIN                         15
187#define AR5K_TUNE_CWMIN_11B                     31
188#define AR5K_TUNE_CWMIN_XR                      3
189#define AR5K_TUNE_CWMAX                         1023
190#define AR5K_TUNE_CWMAX_11B                     1023
191#define AR5K_TUNE_CWMAX_XR                      7
192#define AR5K_TUNE_NOISE_FLOOR                   -72
193#define AR5K_TUNE_MAX_TXPOWER                   63
194#define AR5K_TUNE_DEFAULT_TXPOWER               25
195#define AR5K_TUNE_TPC_TXPOWER                   0
196#define AR5K_TUNE_ANT_DIVERSITY                 1
197#define AR5K_TUNE_HWTXTRIES                     4
198
199#define AR5K_INIT_CARR_SENSE_EN                 1
200
201/*Swap RX/TX Descriptor for big endian archs*/
202#if __BYTE_ORDER == __BIG_ENDIAN
203#define AR5K_INIT_CFG   (               \
204        AR5K_CFG_SWTD | AR5K_CFG_SWRD   \
205)
206#else
207#define AR5K_INIT_CFG   0x00000000
208#endif
209
210/* Initial values */
211#define AR5K_INIT_CYCRSSI_THR1                  2
212#define AR5K_INIT_TX_LATENCY                    502
213#define AR5K_INIT_USEC                          39
214#define AR5K_INIT_USEC_TURBO                    79
215#define AR5K_INIT_USEC_32                       31
216#define AR5K_INIT_SLOT_TIME                     396
217#define AR5K_INIT_SLOT_TIME_TURBO               480
218#define AR5K_INIT_ACK_CTS_TIMEOUT               1024
219#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO         0x08000800
220#define AR5K_INIT_PROG_IFS                      920
221#define AR5K_INIT_PROG_IFS_TURBO                960
222#define AR5K_INIT_EIFS                          3440
223#define AR5K_INIT_EIFS_TURBO                    6880
224#define AR5K_INIT_SIFS                          560
225#define AR5K_INIT_SIFS_TURBO                    480
226#define AR5K_INIT_SH_RETRY                      10
227#define AR5K_INIT_LG_RETRY                      AR5K_INIT_SH_RETRY
228#define AR5K_INIT_SSH_RETRY                     32
229#define AR5K_INIT_SLG_RETRY                     AR5K_INIT_SSH_RETRY
230#define AR5K_INIT_TX_RETRY                      10
231
232#define AR5K_INIT_TRANSMIT_LATENCY              (                       \
233        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
234        (AR5K_INIT_USEC)                                                \
235)
236#define AR5K_INIT_TRANSMIT_LATENCY_TURBO        (                       \
237        (AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) |       \
238        (AR5K_INIT_USEC_TURBO)                                          \
239)
240#define AR5K_INIT_PROTO_TIME_CNTRL              (                       \
241        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) |      \
242        (AR5K_INIT_PROG_IFS)                                            \
243)
244#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO        (                       \
245        (AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
246        (AR5K_INIT_PROG_IFS_TURBO)                                      \
247)
248
249/* token to use for aifs, cwmin, cwmax in MadWiFi */
250#define AR5K_TXQ_USEDEFAULT     ((u32) -1)
251
252/* GENERIC CHIPSET DEFINITIONS */
253
254/* MAC Chips */
255enum ath5k_version {
256        AR5K_AR5210     = 0,
257        AR5K_AR5211     = 1,
258        AR5K_AR5212     = 2,
259};
260
261/* PHY Chips */
262enum ath5k_radio {
263        AR5K_RF5110     = 0,
264        AR5K_RF5111     = 1,
265        AR5K_RF5112     = 2,
266        AR5K_RF2413     = 3,
267        AR5K_RF5413     = 4,
268        AR5K_RF2316     = 5,
269        AR5K_RF2317     = 6,
270        AR5K_RF2425     = 7,
271};
272
273/*
274 * Common silicon revision/version values
275 */
276
277enum ath5k_srev_type {
278        AR5K_VERSION_MAC,
279        AR5K_VERSION_RAD,
280};
281
282struct ath5k_srev_name {
283        const char              *sr_name;
284        enum ath5k_srev_type    sr_type;
285        unsigned                sr_val;
286};
287
288#define AR5K_SREV_UNKNOWN       0xffff
289
290#define AR5K_SREV_AR5210        0x00 /* Crete */
291#define AR5K_SREV_AR5311        0x10 /* Maui 1 */
292#define AR5K_SREV_AR5311A       0x20 /* Maui 2 */
293#define AR5K_SREV_AR5311B       0x30 /* Spirit */
294#define AR5K_SREV_AR5211        0x40 /* Oahu */
295#define AR5K_SREV_AR5212        0x50 /* Venice */
296#define AR5K_SREV_AR5213        0x55 /* ??? */
297#define AR5K_SREV_AR5213A       0x59 /* Hainan */
298#define AR5K_SREV_AR2413        0x78 /* Griffin lite */
299#define AR5K_SREV_AR2414        0x70 /* Griffin */
300#define AR5K_SREV_AR5424        0x90 /* Condor */
301#define AR5K_SREV_AR5413        0xa4 /* Eagle lite */
302#define AR5K_SREV_AR5414        0xa0 /* Eagle */
303#define AR5K_SREV_AR2415        0xb0 /* Talon */
304#define AR5K_SREV_AR5416        0xc0 /* PCI-E */
305#define AR5K_SREV_AR5418        0xca /* PCI-E */
306#define AR5K_SREV_AR2425        0xe0 /* Swan */
307#define AR5K_SREV_AR2417        0xf0 /* Nala */
308
309#define AR5K_SREV_RAD_5110      0x00
310#define AR5K_SREV_RAD_5111      0x10
311#define AR5K_SREV_RAD_5111A     0x15
312#define AR5K_SREV_RAD_2111      0x20
313#define AR5K_SREV_RAD_5112      0x30
314#define AR5K_SREV_RAD_5112A     0x35
315#define AR5K_SREV_RAD_5112B     0x36
316#define AR5K_SREV_RAD_2112      0x40
317#define AR5K_SREV_RAD_2112A     0x45
318#define AR5K_SREV_RAD_2112B     0x46
319#define AR5K_SREV_RAD_2413      0x50
320#define AR5K_SREV_RAD_5413      0x60
321#define AR5K_SREV_RAD_2316      0x70 /* Cobra SoC */
322#define AR5K_SREV_RAD_2317      0x80
323#define AR5K_SREV_RAD_5424      0xa0 /* Mostly same as 5413 */
324#define AR5K_SREV_RAD_2425      0xa2
325#define AR5K_SREV_RAD_5133      0xc0
326
327#define AR5K_SREV_PHY_5211      0x30
328#define AR5K_SREV_PHY_5212      0x41
329#define AR5K_SREV_PHY_5212A     0x42
330#define AR5K_SREV_PHY_5212B     0x43
331#define AR5K_SREV_PHY_2413      0x45
332#define AR5K_SREV_PHY_5413      0x61
333#define AR5K_SREV_PHY_2425      0x70
334
335/*
336 * Some of this information is based on Documentation from:
337 *
338 * http://madwifi.org/wiki/ChipsetFeatures/SuperAG
339 *
340 * Modulation for Atheros' eXtended Range - range enhancing extension that is
341 * supposed to double the distance an Atheros client device can keep a
342 * connection with an Atheros access point. This is achieved by increasing
343 * the receiver sensitivity up to, -105dBm, which is about 20dB above what
344 * the 802.11 specifications demand. In addition, new (proprietary) data rates
345 * are introduced: 3, 2, 1, 0.5 and 0.25 MBit/s.
346 *
347 * Please note that can you either use XR or TURBO but you cannot use both,
348 * they are exclusive.
349 *
350 */
351#define MODULATION_XR           0x00000200
352
353/*
354 * Modulation for Atheros' Turbo G and Turbo A, its supposed to provide a
355 * throughput transmission speed up to 40Mbit/s-60Mbit/s at a 108Mbit/s
356 * signaling rate achieved through the bonding of two 54Mbit/s 802.11g
357 * channels. To use this feature your Access Point must also suport it.
358 * There is also a distinction between "static" and "dynamic" turbo modes:
359 *
360 * - Static: is the dumb version: devices set to this mode stick to it until
361 *     the mode is turned off.
362 * - Dynamic: is the intelligent version, the network decides itself if it
363 *     is ok to use turbo. As soon as traffic is detected on adjacent channels
364 *     (which would get used in turbo mode), or when a non-turbo station joins
365 *     the network, turbo mode won't be used until the situation changes again.
366 *     Dynamic mode is achieved by Atheros' Adaptive Radio (AR) feature which
367 *     monitors the used radio band in order to decide whether turbo mode may
368 *     be used or not.
369 *
370 * This article claims Super G sticks to bonding of channels 5 and 6 for
371 * USA:
372 *
373 * http://www.pcworld.com/article/id,113428-page,1/article.html
374 *
375 * The channel bonding seems to be driver specific though. In addition to
376 * deciding what channels will be used, these "Turbo" modes are accomplished
377 * by also enabling the following features:
378 *
379 * - Bursting: allows multiple frames to be sent at once, rather than pausing
380 *     after each frame. Bursting is a standards-compliant feature that can be
381 *     used with any Access Point.
382 * - Fast frames: increases the amount of information that can be sent per
383 *     frame, also resulting in a reduction of transmission overhead. It is a
384 *     proprietary feature that needs to be supported by the Access Point.
385 * - Compression: data frames are compressed in real time using a Lempel Ziv
386 *     algorithm. This is done transparently. Once this feature is enabled,
387 *     compression and decompression takes place inside the chipset, without
388 *     putting additional load on the host CPU.
389 *
390 */
391#define MODULATION_TURBO        0x00000080
392
393enum ath5k_driver_mode {
394        AR5K_MODE_11A           = 0,
395        AR5K_MODE_11A_TURBO     = 1,
396        AR5K_MODE_11B           = 2,
397        AR5K_MODE_11G           = 3,
398        AR5K_MODE_11G_TURBO     = 4,
399        AR5K_MODE_XR            = 5,
400};
401
402enum {
403        AR5K_MODE_BIT_11A       = (1 << AR5K_MODE_11A),
404        AR5K_MODE_BIT_11A_TURBO = (1 << AR5K_MODE_11A_TURBO),
405        AR5K_MODE_BIT_11B       = (1 << AR5K_MODE_11B),
406        AR5K_MODE_BIT_11G       = (1 << AR5K_MODE_11G),
407        AR5K_MODE_BIT_11G_TURBO = (1 << AR5K_MODE_11G_TURBO),
408        AR5K_MODE_BIT_XR        = (1 << AR5K_MODE_XR),
409};
410
411/****************\
412  TX DEFINITIONS
413\****************/
414
415/*
416 * TX Status descriptor
417 */
418struct ath5k_tx_status {
419        u16     ts_seqnum;
420        u16     ts_tstamp;
421        u8      ts_status;
422        u8      ts_rate[4];
423        u8      ts_retry[4];
424        u8      ts_final_idx;
425        s8      ts_rssi;
426        u8      ts_shortretry;
427        u8      ts_longretry;
428        u8      ts_virtcol;
429        u8      ts_antenna;
430} __attribute__ ((packed));
431
432#define AR5K_TXSTAT_ALTRATE     0x80
433#define AR5K_TXERR_XRETRY       0x01
434#define AR5K_TXERR_FILT         0x02
435#define AR5K_TXERR_FIFO         0x04
436
437/**
438 * enum ath5k_tx_queue - Queue types used to classify tx queues.
439 * @AR5K_TX_QUEUE_INACTIVE: q is unused -- see ath5k_hw_release_tx_queue
440 * @AR5K_TX_QUEUE_DATA: A normal data queue
441 * @AR5K_TX_QUEUE_XR_DATA: An XR-data queue
442 * @AR5K_TX_QUEUE_BEACON: The beacon queue
443 * @AR5K_TX_QUEUE_CAB: The after-beacon queue
444 * @AR5K_TX_QUEUE_UAPSD: Unscheduled Automatic Power Save Delivery queue
445 */
446enum ath5k_tx_queue {
447        AR5K_TX_QUEUE_INACTIVE = 0,
448        AR5K_TX_QUEUE_DATA,
449        AR5K_TX_QUEUE_XR_DATA,
450        AR5K_TX_QUEUE_BEACON,
451        AR5K_TX_QUEUE_CAB,
452        AR5K_TX_QUEUE_UAPSD,
453};
454
455/*
456 * Queue syb-types to classify normal data queues.
457 * These are the 4 Access Categories as defined in
458 * WME spec. 0 is the lowest priority and 4 is the
459 * highest. Normal data that hasn't been classified
460 * goes to the Best Effort AC.
461 */
462enum ath5k_tx_queue_subtype {
463        AR5K_WME_AC_BK = 0,     /*Background traffic*/
464        AR5K_WME_AC_BE,         /*Best-effort (normal) traffic)*/
465        AR5K_WME_AC_VI,         /*Video traffic*/
466        AR5K_WME_AC_VO,         /*Voice traffic*/
467};
468
469/*
470 * Queue ID numbers as returned by the hw functions, each number
471 * represents a hw queue. If hw does not support hw queues
472 * (eg 5210) all data goes in one queue. These match
473 * d80211 definitions (net80211/MadWiFi don't use them).
474 */
475enum ath5k_tx_queue_id {
476        AR5K_TX_QUEUE_ID_NOQCU_DATA     = 0,
477        AR5K_TX_QUEUE_ID_NOQCU_BEACON   = 1,
478        AR5K_TX_QUEUE_ID_DATA_MIN       = 0, /*IEEE80211_TX_QUEUE_DATA0*/
479        AR5K_TX_QUEUE_ID_DATA_MAX       = 4, /*IEEE80211_TX_QUEUE_DATA4*/
480        AR5K_TX_QUEUE_ID_DATA_SVP       = 5, /*IEEE80211_TX_QUEUE_SVP - Spectralink Voice Protocol*/
481        AR5K_TX_QUEUE_ID_CAB            = 6, /*IEEE80211_TX_QUEUE_AFTER_BEACON*/
482        AR5K_TX_QUEUE_ID_BEACON         = 7, /*IEEE80211_TX_QUEUE_BEACON*/
483        AR5K_TX_QUEUE_ID_UAPSD          = 8,
484        AR5K_TX_QUEUE_ID_XR_DATA        = 9,
485};
486
487/*
488 * Flags to set hw queue's parameters...
489 */
490#define AR5K_TXQ_FLAG_TXOKINT_ENABLE            0x0001  /* Enable TXOK interrupt */
491#define AR5K_TXQ_FLAG_TXERRINT_ENABLE           0x0002  /* Enable TXERR interrupt */
492#define AR5K_TXQ_FLAG_TXEOLINT_ENABLE           0x0004  /* Enable TXEOL interrupt -not used- */
493#define AR5K_TXQ_FLAG_TXDESCINT_ENABLE          0x0008  /* Enable TXDESC interrupt -not used- */
494#define AR5K_TXQ_FLAG_TXURNINT_ENABLE           0x0010  /* Enable TXURN interrupt */
495#define AR5K_TXQ_FLAG_CBRORNINT_ENABLE          0x0020  /* Enable CBRORN interrupt */
496#define AR5K_TXQ_FLAG_CBRURNINT_ENABLE          0x0040  /* Enable CBRURN interrupt */
497#define AR5K_TXQ_FLAG_QTRIGINT_ENABLE           0x0080  /* Enable QTRIG interrupt */
498#define AR5K_TXQ_FLAG_TXNOFRMINT_ENABLE         0x0100  /* Enable TXNOFRM interrupt */
499#define AR5K_TXQ_FLAG_BACKOFF_DISABLE           0x0200  /* Disable random post-backoff */
500#define AR5K_TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE 0x0300  /* Enable ready time expiry policy (?)*/
501#define AR5K_TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE 0x0800  /* Enable backoff while bursting */
502#define AR5K_TXQ_FLAG_POST_FR_BKOFF_DIS         0x1000  /* Disable backoff while bursting */
503#define AR5K_TXQ_FLAG_COMPRESSION_ENABLE        0x2000  /* Enable hw compression -not implemented-*/
504
505/*
506 * A struct to hold tx queue's parameters
507 */
508struct ath5k_txq_info {
509        enum ath5k_tx_queue tqi_type;
510        enum ath5k_tx_queue_subtype tqi_subtype;
511        u16     tqi_flags;      /* Tx queue flags (see above) */
512        u32     tqi_aifs;       /* Arbitrated Interframe Space */
513        s32     tqi_cw_min;     /* Minimum Contention Window */
514        s32     tqi_cw_max;     /* Maximum Contention Window */
515        u32     tqi_cbr_period; /* Constant bit rate period */
516        u32     tqi_cbr_overflow_limit;
517        u32     tqi_burst_time;
518        u32     tqi_ready_time; /* Not used */
519};
520
521/*
522 * Transmit packet types.
523 * used on tx control descriptor
524 * TODO: Use them inside base.c corectly
525 */
526enum ath5k_pkt_type {
527        AR5K_PKT_TYPE_NORMAL            = 0,
528        AR5K_PKT_TYPE_ATIM              = 1,
529        AR5K_PKT_TYPE_PSPOLL            = 2,
530        AR5K_PKT_TYPE_BEACON            = 3,
531        AR5K_PKT_TYPE_PROBE_RESP        = 4,
532        AR5K_PKT_TYPE_PIFS              = 5,
533};
534
535/*
536 * TX power and TPC settings
537 */
538#define AR5K_TXPOWER_OFDM(_r, _v)       (                       \
539        ((0 & 1) << ((_v) + 6)) |                               \
540        (((ah->ah_txpower.txp_rates_power_table[(_r)]) & 0x3f) << (_v)) \
541)
542
543#define AR5K_TXPOWER_CCK(_r, _v)        (                       \
544        (ah->ah_txpower.txp_rates_power_table[(_r)] & 0x3f) << (_v)     \
545)
546
547/*
548 * DMA size definitions (2^n+2)
549 */
550enum ath5k_dmasize {
551        AR5K_DMASIZE_4B = 0,
552        AR5K_DMASIZE_8B,
553        AR5K_DMASIZE_16B,
554        AR5K_DMASIZE_32B,
555        AR5K_DMASIZE_64B,
556        AR5K_DMASIZE_128B,
557        AR5K_DMASIZE_256B,
558        AR5K_DMASIZE_512B
559};
560
561
562/****************\
563  RX DEFINITIONS
564\****************/
565
566/*
567 * RX Status descriptor
568 */
569struct ath5k_rx_status {
570        u16     rs_datalen;
571        u16     rs_tstamp;
572        u8      rs_status;
573        u8      rs_phyerr;
574        s8      rs_rssi;
575        u8      rs_keyix;
576        u8      rs_rate;
577        u8      rs_antenna;
578        u8      rs_more;
579};
580
581#define AR5K_RXERR_CRC          0x01
582#define AR5K_RXERR_PHY          0x02
583#define AR5K_RXERR_FIFO         0x04
584#define AR5K_RXERR_DECRYPT      0x08
585#define AR5K_RXERR_MIC          0x10
586#define AR5K_RXKEYIX_INVALID    ((u8) - 1)
587#define AR5K_TXKEYIX_INVALID    ((u32) - 1)
588
589
590/*
591 * TSF to TU conversion:
592 *
593 * TSF is a 64bit value in usec (microseconds).
594 * TU is a 32bit value and defined by IEEE802.11 (page 6) as "A measurement of
595 * time equal to 1024 usec", so it's roughly milliseconds (usec / 1024).
596 */
597#define TSF_TO_TU(_tsf) (u32)((_tsf) >> 10)
598
599
600/*******************************\
601  GAIN OPTIMIZATION DEFINITIONS
602\*******************************/
603
604enum ath5k_rfgain {
605        AR5K_RFGAIN_INACTIVE = 0,
606        AR5K_RFGAIN_ACTIVE,
607        AR5K_RFGAIN_READ_REQUESTED,
608        AR5K_RFGAIN_NEED_CHANGE,
609};
610
611struct ath5k_gain {
612        u8                      g_step_idx;
613        u8                      g_current;
614        u8                      g_target;
615        u8                      g_low;
616        u8                      g_high;
617        u8                      g_f_corr;
618        u8                      g_state;
619};
620
621/********************\
622  COMMON DEFINITIONS
623\********************/
624
625#define AR5K_SLOT_TIME_9        396
626#define AR5K_SLOT_TIME_20       880
627#define AR5K_SLOT_TIME_MAX      0xffff
628
629/* channel_flags */
630#define CHANNEL_CW_INT  0x0008  /* Contention Window interference detected */
631#define CHANNEL_TURBO   0x0010  /* Turbo Channel */
632#define CHANNEL_CCK     0x0020  /* CCK channel */
633#define CHANNEL_OFDM    0x0040  /* OFDM channel */
634#define CHANNEL_2GHZ    0x0080  /* 2GHz channel. */
635#define CHANNEL_5GHZ    0x0100  /* 5GHz channel */
636#define CHANNEL_PASSIVE 0x0200  /* Only passive scan allowed */
637#define CHANNEL_DYN     0x0400  /* Dynamic CCK-OFDM channel (for g operation) */
638#define CHANNEL_XR      0x0800  /* XR channel */
639
640#define CHANNEL_A       (CHANNEL_5GHZ|CHANNEL_OFDM)
641#define CHANNEL_B       (CHANNEL_2GHZ|CHANNEL_CCK)
642#define CHANNEL_G       (CHANNEL_2GHZ|CHANNEL_OFDM)
643#define CHANNEL_T       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
644#define CHANNEL_TG      (CHANNEL_2GHZ|CHANNEL_OFDM|CHANNEL_TURBO)
645#define CHANNEL_108A    CHANNEL_T
646#define CHANNEL_108G    CHANNEL_TG
647#define CHANNEL_X       (CHANNEL_5GHZ|CHANNEL_OFDM|CHANNEL_XR)
648
649#define CHANNEL_ALL     (CHANNEL_OFDM|CHANNEL_CCK|CHANNEL_2GHZ|CHANNEL_5GHZ| \
650                CHANNEL_TURBO)
651
652#define CHANNEL_ALL_NOTURBO     (CHANNEL_ALL & ~CHANNEL_TURBO)
653#define CHANNEL_MODES           CHANNEL_ALL
654
655/*
656 * Used internaly for reset_tx_queue).
657 * Also see struct struct net80211_channel.
658 */
659#define IS_CHAN_XR(_c)  ((_c->hw_value & CHANNEL_XR) != 0)
660#define IS_CHAN_B(_c)   ((_c->hw_value & CHANNEL_B) != 0)
661
662/*
663 * The following structure is used to map 2GHz channels to
664 * 5GHz Atheros channels.
665 * TODO: Clean up
666 */
667struct ath5k_athchan_2ghz {
668        u32     a2_flags;
669        u16     a2_athchan;
670};
671
672
673/******************\
674  RATE DEFINITIONS
675\******************/
676
677/**
678 * Seems the ar5xxx harware supports up to 32 rates, indexed by 1-32.
679 *
680 * The rate code is used to get the RX rate or set the TX rate on the
681 * hardware descriptors. It is also used for internal modulation control
682 * and settings.
683 *
684 * This is the hardware rate map we are aware of:
685 *
686 * rate_code   0x01    0x02    0x03    0x04    0x05    0x06    0x07    0x08
687 * rate_kbps   3000    1000    ?       ?       ?       2000    500     48000
688 *
689 * rate_code   0x09    0x0A    0x0B    0x0C    0x0D    0x0E    0x0F    0x10
690 * rate_kbps   24000   12000   6000    54000   36000   18000   9000    ?
691 *
692 * rate_code   17      18      19      20      21      22      23      24
693 * rate_kbps   ?       ?       ?       ?       ?       ?       ?       11000
694 *
695 * rate_code   25      26      27      28      29      30      31      32
696 * rate_kbps   5500    2000    1000    11000S  5500S   2000S   ?       ?
697 *
698 * "S" indicates CCK rates with short preamble.
699 *
700 * AR5211 has different rate codes for CCK (802.11B) rates. It only uses the
701 * lowest 4 bits, so they are the same as below with a 0xF mask.
702 * (0xB, 0xA, 0x9 and 0x8 for 1M, 2M, 5.5M and 11M).
703 * We handle this in ath5k_setup_bands().
704 */
705#define AR5K_MAX_RATES 32
706
707/* B */
708#define ATH5K_RATE_CODE_1M      0x1B
709#define ATH5K_RATE_CODE_2M      0x1A
710#define ATH5K_RATE_CODE_5_5M    0x19
711#define ATH5K_RATE_CODE_11M     0x18
712/* A and G */
713#define ATH5K_RATE_CODE_6M      0x0B
714#define ATH5K_RATE_CODE_9M      0x0F
715#define ATH5K_RATE_CODE_12M     0x0A
716#define ATH5K_RATE_CODE_18M     0x0E
717#define ATH5K_RATE_CODE_24M     0x09
718#define ATH5K_RATE_CODE_36M     0x0D
719#define ATH5K_RATE_CODE_48M     0x08
720#define ATH5K_RATE_CODE_54M     0x0C
721/* XR */
722#define ATH5K_RATE_CODE_XR_500K 0x07
723#define ATH5K_RATE_CODE_XR_1M   0x02
724#define ATH5K_RATE_CODE_XR_2M   0x06
725#define ATH5K_RATE_CODE_XR_3M   0x01
726
727/* adding this flag to rate_code enables short preamble */
728#define AR5K_SET_SHORT_PREAMBLE 0x04
729
730/*
731 * Crypto definitions
732 */
733
734#define AR5K_KEYCACHE_SIZE      8
735
736/***********************\
737 HW RELATED DEFINITIONS
738\***********************/
739
740/*
741 * Misc definitions
742 */
743#define AR5K_RSSI_EP_MULTIPLIER (1<<7)
744
745#define AR5K_ASSERT_ENTRY(_e, _s) do {          \
746        if (_e >= _s)                           \
747                return 0;                       \
748} while (0)
749
750/*
751 * Hardware interrupt abstraction
752 */
753
754/**
755 * enum ath5k_int - Hardware interrupt masks helpers
756 *
757 * @AR5K_INT_RX: mask to identify received frame interrupts, of type
758 *      AR5K_ISR_RXOK or AR5K_ISR_RXERR
759 * @AR5K_INT_RXDESC: Request RX descriptor/Read RX descriptor (?)
760 * @AR5K_INT_RXNOFRM: No frame received (?)
761 * @AR5K_INT_RXEOL: received End Of List for VEOL (Virtual End Of List). The
762 *      Queue Control Unit (QCU) signals an EOL interrupt only if a descriptor's
763 *      LinkPtr is NULL. For more details, refer to:
764 *      http://www.freepatentsonline.com/20030225739.html
765 * @AR5K_INT_RXORN: Indicates we got RX overrun (eg. no more descriptors).
766 *      Note that Rx overrun is not always fatal, on some chips we can continue
767 *      operation without reseting the card, that's why int_fatal is not
768 *      common for all chips.
769 * @AR5K_INT_TX: mask to identify received frame interrupts, of type
770 *      AR5K_ISR_TXOK or AR5K_ISR_TXERR
771 * @AR5K_INT_TXDESC: Request TX descriptor/Read TX status descriptor (?)
772 * @AR5K_INT_TXURN: received when we should increase the TX trigger threshold
773 *      We currently do increments on interrupt by
774 *      (AR5K_TUNE_MAX_TX_FIFO_THRES - current_trigger_level) / 2
775 * @AR5K_INT_MIB: Indicates the Management Information Base counters should be
776 *      checked. We should do this with ath5k_hw_update_mib_counters() but
777 *      it seems we should also then do some noise immunity work.
778 * @AR5K_INT_RXPHY: RX PHY Error
779 * @AR5K_INT_RXKCM: RX Key cache miss
780 * @AR5K_INT_SWBA: SoftWare Beacon Alert - indicates its time to send a
781 *      beacon that must be handled in software. The alternative is if you
782 *      have VEOL support, in that case you let the hardware deal with things.
783 * @AR5K_INT_BMISS: If in STA mode this indicates we have stopped seeing
784 *      beacons from the AP have associated with, we should probably try to
785 *      reassociate. When in IBSS mode this might mean we have not received
786 *      any beacons from any local stations. Note that every station in an
787 *      IBSS schedules to send beacons at the Target Beacon Transmission Time
788 *      (TBTT) with a random backoff.
789 * @AR5K_INT_BNR: Beacon Not Ready interrupt - ??
790 * @AR5K_INT_GPIO: GPIO interrupt is used for RF Kill, disabled for now
791 *      until properly handled
792 * @AR5K_INT_FATAL: Fatal errors were encountered, typically caused by DMA
793 *      errors. These types of errors we can enable seem to be of type
794 *      AR5K_SIMR2_MCABT, AR5K_SIMR2_SSERR and AR5K_SIMR2_DPERR.
795 * @AR5K_INT_GLOBAL: Used to clear and set the IER
796 * @AR5K_INT_NOCARD: signals the card has been removed
797 * @AR5K_INT_COMMON: common interrupts shared amogst MACs with the same
798 *      bit value
799 *
800 * These are mapped to take advantage of some common bits
801 * between the MACs, to be able to set intr properties
802 * easier. Some of them are not used yet inside hw.c. Most map
803 * to the respective hw interrupt value as they are common amogst different
804 * MACs.
805 */
806enum ath5k_int {
807        AR5K_INT_RXOK   = 0x00000001,
808        AR5K_INT_RXDESC = 0x00000002,
809        AR5K_INT_RXERR  = 0x00000004,
810        AR5K_INT_RXNOFRM = 0x00000008,
811        AR5K_INT_RXEOL  = 0x00000010,
812        AR5K_INT_RXORN  = 0x00000020,
813        AR5K_INT_TXOK   = 0x00000040,
814        AR5K_INT_TXDESC = 0x00000080,
815        AR5K_INT_TXERR  = 0x00000100,
816        AR5K_INT_TXNOFRM = 0x00000200,
817        AR5K_INT_TXEOL  = 0x00000400,
818        AR5K_INT_TXURN  = 0x00000800,
819        AR5K_INT_MIB    = 0x00001000,
820        AR5K_INT_SWI    = 0x00002000,
821        AR5K_INT_RXPHY  = 0x00004000,
822        AR5K_INT_RXKCM  = 0x00008000,
823        AR5K_INT_SWBA   = 0x00010000,
824        AR5K_INT_BRSSI  = 0x00020000,
825        AR5K_INT_BMISS  = 0x00040000,
826        AR5K_INT_FATAL  = 0x00080000, /* Non common */
827        AR5K_INT_BNR    = 0x00100000, /* Non common */
828        AR5K_INT_TIM    = 0x00200000, /* Non common */
829        AR5K_INT_DTIM   = 0x00400000, /* Non common */
830        AR5K_INT_DTIM_SYNC =    0x00800000, /* Non common */
831        AR5K_INT_GPIO   =       0x01000000,
832        AR5K_INT_BCN_TIMEOUT =  0x02000000, /* Non common */
833        AR5K_INT_CAB_TIMEOUT =  0x04000000, /* Non common */
834        AR5K_INT_RX_DOPPLER =   0x08000000, /* Non common */
835        AR5K_INT_QCBRORN =      0x10000000, /* Non common */
836        AR5K_INT_QCBRURN =      0x20000000, /* Non common */
837        AR5K_INT_QTRIG  =       0x40000000, /* Non common */
838        AR5K_INT_GLOBAL =       0x80000000,
839
840        AR5K_INT_COMMON  = AR5K_INT_RXOK
841                | AR5K_INT_RXDESC
842                | AR5K_INT_RXERR
843                | AR5K_INT_RXNOFRM
844                | AR5K_INT_RXEOL
845                | AR5K_INT_RXORN
846                | AR5K_INT_TXOK
847                | AR5K_INT_TXDESC
848                | AR5K_INT_TXERR
849                | AR5K_INT_TXNOFRM
850                | AR5K_INT_TXEOL
851                | AR5K_INT_TXURN
852                | AR5K_INT_MIB
853                | AR5K_INT_SWI
854                | AR5K_INT_RXPHY
855                | AR5K_INT_RXKCM
856                | AR5K_INT_SWBA
857                | AR5K_INT_BRSSI
858                | AR5K_INT_BMISS
859                | AR5K_INT_GPIO
860                | AR5K_INT_GLOBAL,
861
862        AR5K_INT_NOCARD = 0xffffffff
863};
864
865/*
866 * Power management
867 */
868enum ath5k_power_mode {
869        AR5K_PM_UNDEFINED = 0,
870        AR5K_PM_AUTO,
871        AR5K_PM_AWAKE,
872        AR5K_PM_FULL_SLEEP,
873        AR5K_PM_NETWORK_SLEEP,
874};
875
876/* GPIO-controlled software LED */
877#define AR5K_SOFTLED_PIN        0
878#define AR5K_SOFTLED_ON         0
879#define AR5K_SOFTLED_OFF        1
880
881/*
882 * Chipset capabilities -see ath5k_hw_get_capability-
883 * get_capability function is not yet fully implemented
884 * in ath5k so most of these don't work yet...
885 * TODO: Implement these & merge with _TUNE_ stuff above
886 */
887enum ath5k_capability_type {
888        AR5K_CAP_REG_DMN                = 0,    /* Used to get current reg. domain id */
889        AR5K_CAP_TKIP_MIC               = 2,    /* Can handle TKIP MIC in hardware */
890        AR5K_CAP_TKIP_SPLIT             = 3,    /* TKIP uses split keys */
891        AR5K_CAP_PHYCOUNTERS            = 4,    /* PHY error counters */
892        AR5K_CAP_DIVERSITY              = 5,    /* Supports fast diversity */
893        AR5K_CAP_NUM_TXQUEUES           = 6,    /* Used to get max number of hw txqueues */
894        AR5K_CAP_VEOL                   = 7,    /* Supports virtual EOL */
895        AR5K_CAP_COMPRESSION            = 8,    /* Supports compression */
896        AR5K_CAP_BURST                  = 9,    /* Supports packet bursting */
897        AR5K_CAP_FASTFRAME              = 10,   /* Supports fast frames */
898        AR5K_CAP_TXPOW                  = 11,   /* Used to get global tx power limit */
899        AR5K_CAP_TPC                    = 12,   /* Can do per-packet tx power control (needed for 802.11a) */
900        AR5K_CAP_BSSIDMASK              = 13,   /* Supports bssid mask */
901        AR5K_CAP_MCAST_KEYSRCH          = 14,   /* Supports multicast key search */
902        AR5K_CAP_TSF_ADJUST             = 15,   /* Supports beacon tsf adjust */
903        AR5K_CAP_XR                     = 16,   /* Supports XR mode */
904        AR5K_CAP_WME_TKIPMIC            = 17,   /* Supports TKIP MIC when using WMM */
905        AR5K_CAP_CHAN_HALFRATE          = 18,   /* Supports half rate channels */
906        AR5K_CAP_CHAN_QUARTERRATE       = 19,   /* Supports quarter rate channels */
907        AR5K_CAP_RFSILENT               = 20,   /* Supports RFsilent */
908};
909
910
911/* XXX: we *may* move cap_range stuff to struct wiphy */
912struct ath5k_capabilities {
913        /*
914         * Supported PHY modes
915         * (ie. CHANNEL_A, CHANNEL_B, ...)
916         */
917        u16 cap_mode;
918
919        /*
920         * Frequency range (without regulation restrictions)
921         */
922        struct {
923                u16     range_2ghz_min;
924                u16     range_2ghz_max;
925                u16     range_5ghz_min;
926                u16     range_5ghz_max;
927        } cap_range;
928
929        /*
930         * Values stored in the EEPROM (some of them...)
931         */
932        struct ath5k_eeprom_info        cap_eeprom;
933
934        /*
935         * Queue information
936         */
937        struct {
938                u8      q_tx_num;
939        } cap_queues;
940};
941
942
943/***************************************\
944  HARDWARE ABSTRACTION LAYER STRUCTURE
945\***************************************/
946
947/*
948 * Misc defines
949 */
950
951#define AR5K_MAX_GPIO           10
952#define AR5K_MAX_RF_BANKS       8
953
954/* TODO: Clean up and merge with ath5k_softc */
955struct ath5k_hw {
956        struct ath5k_softc      *ah_sc;
957        void                    *ah_iobase;
958
959        enum ath5k_int          ah_imr;
960        int                     ah_ier;
961
962        struct net80211_channel *ah_current_channel;
963        int                     ah_turbo;
964        int                     ah_calibration;
965        int                     ah_running;
966        int                     ah_single_chip;
967        int                     ah_combined_mic;
968
969        u32                     ah_mac_srev;
970        u16                     ah_mac_version;
971        u16                     ah_mac_revision;
972        u16                     ah_phy_revision;
973        u16                     ah_radio_5ghz_revision;
974        u16                     ah_radio_2ghz_revision;
975
976        enum ath5k_version      ah_version;
977        enum ath5k_radio        ah_radio;
978        u32                     ah_phy;
979
980        int                     ah_5ghz;
981        int                     ah_2ghz;
982
983#define ah_regdomain            ah_capabilities.cap_regdomain.reg_current
984#define ah_regdomain_hw         ah_capabilities.cap_regdomain.reg_hw
985#define ah_modes                ah_capabilities.cap_mode
986#define ah_ee_version           ah_capabilities.cap_eeprom.ee_version
987
988        u32                     ah_atim_window;
989        u32                     ah_aifs;
990        u32                     ah_cw_min;
991        u32                     ah_cw_max;
992        int                     ah_software_retry;
993        u32                     ah_limit_tx_retries;
994
995        u32                     ah_antenna[AR5K_EEPROM_N_MODES][AR5K_ANT_MAX];
996        int                     ah_ant_diversity;
997
998        u8                      ah_sta_id[ETH_ALEN];
999
1000        /* Current BSSID we are trying to assoc to / create.
1001         * This is passed by mac80211 on config_interface() and cached here for
1002         * use in resets */
1003        u8                      ah_bssid[ETH_ALEN];
1004        u8                      ah_bssid_mask[ETH_ALEN];
1005
1006        u32                     ah_gpio[AR5K_MAX_GPIO];
1007        int                     ah_gpio_npins;
1008
1009        struct ath5k_capabilities ah_capabilities;
1010
1011        struct ath5k_txq_info   ah_txq;
1012        u32                     ah_txq_status;
1013        u32                     ah_txq_imr_txok;
1014        u32                     ah_txq_imr_txerr;
1015        u32                     ah_txq_imr_txurn;
1016        u32                     ah_txq_imr_txdesc;
1017        u32                     ah_txq_imr_txeol;
1018        u32                     ah_txq_imr_cbrorn;
1019        u32                     ah_txq_imr_cbrurn;
1020        u32                     ah_txq_imr_qtrig;
1021        u32                     ah_txq_imr_nofrm;
1022        u32                     ah_txq_isr;
1023        u32                     *ah_rf_banks;
1024        size_t                  ah_rf_banks_size;
1025        size_t                  ah_rf_regs_count;
1026        struct ath5k_gain       ah_gain;
1027        u8                      ah_offset[AR5K_MAX_RF_BANKS];
1028
1029
1030        struct {
1031                /* Temporary tables used for interpolation */
1032                u8              tmpL[AR5K_EEPROM_N_PD_GAINS]
1033                                        [AR5K_EEPROM_POWER_TABLE_SIZE];
1034                u8              tmpR[AR5K_EEPROM_N_PD_GAINS]
1035                                        [AR5K_EEPROM_POWER_TABLE_SIZE];
1036                u8              txp_pd_table[AR5K_EEPROM_POWER_TABLE_SIZE * 2];
1037                u16             txp_rates_power_table[AR5K_MAX_RATES];
1038                u8              txp_min_idx;
1039                int             txp_tpc;
1040                /* Values in 0.25dB units */
1041                s16             txp_min_pwr;
1042                s16             txp_max_pwr;
1043                s16             txp_offset;
1044                s16             txp_ofdm;
1045                /* Values in dB units */
1046                s16             txp_cck_ofdm_pwr_delta;
1047                s16             txp_cck_ofdm_gainf_delta;
1048        } ah_txpower;
1049
1050        /* noise floor from last periodic calibration */
1051        s32                     ah_noise_floor;
1052
1053        /*
1054         * Function pointers
1055         */
1056        int (*ah_setup_rx_desc)(struct ath5k_hw *ah, struct ath5k_desc *desc,
1057                                u32 size, unsigned int flags);
1058        int (*ah_setup_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1059                unsigned int, unsigned int, enum ath5k_pkt_type, unsigned int,
1060                unsigned int, unsigned int, unsigned int, unsigned int,
1061                unsigned int, unsigned int, unsigned int);
1062        int (*ah_proc_tx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1063                struct ath5k_tx_status *);
1064        int (*ah_proc_rx_desc)(struct ath5k_hw *, struct ath5k_desc *,
1065                struct ath5k_rx_status *);
1066};
1067
1068/*
1069 * Prototypes
1070 */
1071
1072extern int ath5k_bitrate_to_hw_rix(int bitrate);
1073
1074/* Attach/Detach Functions */
1075extern int ath5k_hw_attach(struct ath5k_softc *sc, u8 mac_version, struct ath5k_hw **ah);
1076extern void ath5k_hw_detach(struct ath5k_hw *ah);
1077
1078/* LED functions */
1079extern int ath5k_init_leds(struct ath5k_softc *sc);
1080extern void ath5k_led_enable(struct ath5k_softc *sc);
1081extern void ath5k_led_off(struct ath5k_softc *sc);
1082extern void ath5k_unregister_leds(struct ath5k_softc *sc);
1083
1084/* Reset Functions */
1085extern int ath5k_hw_nic_wakeup(struct ath5k_hw *ah, int flags, int initial);
1086extern int ath5k_hw_reset(struct ath5k_hw *ah, struct net80211_channel *channel, int change_channel);
1087/* Power management functions */
1088extern int ath5k_hw_set_power(struct ath5k_hw *ah, enum ath5k_power_mode mode, int set_chip, u16 sleep_duration);
1089
1090/* DMA Related Functions */
1091extern void ath5k_hw_start_rx_dma(struct ath5k_hw *ah);
1092extern int ath5k_hw_stop_rx_dma(struct ath5k_hw *ah);
1093extern u32 ath5k_hw_get_rxdp(struct ath5k_hw *ah);
1094extern void ath5k_hw_set_rxdp(struct ath5k_hw *ah, u32 phys_addr);
1095extern int ath5k_hw_start_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1096extern int ath5k_hw_stop_tx_dma(struct ath5k_hw *ah, unsigned int queue);
1097extern u32 ath5k_hw_get_txdp(struct ath5k_hw *ah, unsigned int queue);
1098extern int ath5k_hw_set_txdp(struct ath5k_hw *ah, unsigned int queue,
1099                                u32 phys_addr);
1100extern int ath5k_hw_update_tx_triglevel(struct ath5k_hw *ah, int increase);
1101/* Interrupt handling */
1102extern int ath5k_hw_is_intr_pending(struct ath5k_hw *ah);
1103extern int ath5k_hw_get_isr(struct ath5k_hw *ah, enum ath5k_int *interrupt_mask);
1104extern enum ath5k_int ath5k_hw_set_imr(struct ath5k_hw *ah, enum ath5k_int new_mask);
1105
1106/* EEPROM access functions */
1107extern int ath5k_eeprom_init(struct ath5k_hw *ah);
1108extern void ath5k_eeprom_detach(struct ath5k_hw *ah);
1109extern int ath5k_eeprom_read_mac(struct ath5k_hw *ah, u8 *mac);
1110extern int ath5k_eeprom_is_hb63(struct ath5k_hw *ah);
1111
1112/* Protocol Control Unit Functions */
1113extern int ath5k_hw_set_opmode(struct ath5k_hw *ah);
1114/* BSSID Functions */
1115extern void ath5k_hw_get_lladdr(struct ath5k_hw *ah, u8 *mac);
1116extern int ath5k_hw_set_lladdr(struct ath5k_hw *ah, const u8 *mac);
1117extern void ath5k_hw_set_associd(struct ath5k_hw *ah, const u8 *bssid, u16 assoc_id);
1118extern int ath5k_hw_set_bssid_mask(struct ath5k_hw *ah, const u8 *mask);
1119/* Receive start/stop functions */
1120extern void ath5k_hw_start_rx_pcu(struct ath5k_hw *ah);
1121extern void ath5k_hw_stop_rx_pcu(struct ath5k_hw *ah);
1122/* RX Filter functions */
1123extern void ath5k_hw_set_mcast_filter(struct ath5k_hw *ah, u32 filter0, u32 filter1);
1124extern u32 ath5k_hw_get_rx_filter(struct ath5k_hw *ah);
1125extern void ath5k_hw_set_rx_filter(struct ath5k_hw *ah, u32 filter);
1126/* ACK bit rate */
1127void ath5k_hw_set_ack_bitrate_high(struct ath5k_hw *ah, int high);
1128/* ACK/CTS Timeouts */
1129extern int ath5k_hw_set_ack_timeout(struct ath5k_hw *ah, unsigned int timeout);
1130extern unsigned int ath5k_hw_get_ack_timeout(struct ath5k_hw *ah);
1131extern int ath5k_hw_set_cts_timeout(struct ath5k_hw *ah, unsigned int timeout);
1132extern unsigned int ath5k_hw_get_cts_timeout(struct ath5k_hw *ah);
1133/* Key table (WEP) functions */
1134extern int ath5k_hw_reset_key(struct ath5k_hw *ah, u16 entry);
1135
1136/* Queue Control Unit, DFS Control Unit Functions */
1137extern int ath5k_hw_set_tx_queueprops(struct ath5k_hw *ah, const struct ath5k_txq_info *queue_info);
1138extern int ath5k_hw_setup_tx_queue(struct ath5k_hw *ah,
1139                                enum ath5k_tx_queue queue_type,
1140                                struct ath5k_txq_info *queue_info);
1141extern u32 ath5k_hw_num_tx_pending(struct ath5k_hw *ah);
1142extern void ath5k_hw_release_tx_queue(struct ath5k_hw *ah);
1143extern int ath5k_hw_reset_tx_queue(struct ath5k_hw *ah);
1144extern int ath5k_hw_set_slot_time(struct ath5k_hw *ah, unsigned int slot_time);
1145
1146/* Hardware Descriptor Functions */
1147extern int ath5k_hw_init_desc_functions(struct ath5k_hw *ah);
1148
1149/* GPIO Functions */
1150extern int ath5k_hw_set_gpio_input(struct ath5k_hw *ah, u32 gpio);
1151extern int ath5k_hw_set_gpio_output(struct ath5k_hw *ah, u32 gpio);
1152extern u32 ath5k_hw_get_gpio(struct ath5k_hw *ah, u32 gpio);
1153extern int ath5k_hw_set_gpio(struct ath5k_hw *ah, u32 gpio, u32 val);
1154extern void ath5k_hw_set_gpio_intr(struct ath5k_hw *ah, unsigned int gpio, u32 interrupt_level);
1155
1156/* rfkill Functions */
1157extern void ath5k_rfkill_hw_start(struct ath5k_hw *ah);
1158extern void ath5k_rfkill_hw_stop(struct ath5k_hw *ah);
1159
1160/* Misc functions */
1161int ath5k_hw_set_capabilities(struct ath5k_hw *ah);
1162extern int ath5k_hw_get_capability(struct ath5k_hw *ah, enum ath5k_capability_type cap_type, u32 capability, u32 *result);
1163extern int ath5k_hw_enable_pspoll(struct ath5k_hw *ah, u8 *bssid, u16 assoc_id);
1164extern int ath5k_hw_disable_pspoll(struct ath5k_hw *ah);
1165
1166/* Initial register settings functions */
1167extern int ath5k_hw_write_initvals(struct ath5k_hw *ah, u8 mode, int change_channel);
1168
1169/* Initialize RF */
1170extern int ath5k_hw_rfregs_init(struct ath5k_hw *ah,
1171                                struct net80211_channel *channel,
1172                                unsigned int mode);
1173extern int ath5k_hw_rfgain_init(struct ath5k_hw *ah, unsigned int freq);
1174extern enum ath5k_rfgain ath5k_hw_gainf_calibrate(struct ath5k_hw *ah);
1175extern int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah);
1176/* PHY/RF channel functions */
1177extern int ath5k_channel_ok(struct ath5k_hw *ah, u16 freq, unsigned int flags);
1178extern int ath5k_hw_channel(struct ath5k_hw *ah, struct net80211_channel *channel);
1179/* PHY calibration */
1180extern int ath5k_hw_phy_calibrate(struct ath5k_hw *ah, struct net80211_channel *channel);
1181extern int ath5k_hw_noise_floor_calibration(struct ath5k_hw *ah, short freq);
1182/* Misc PHY functions */
1183extern u16 ath5k_hw_radio_revision(struct ath5k_hw *ah, unsigned int chan);
1184extern void ath5k_hw_set_def_antenna(struct ath5k_hw *ah, unsigned int ant);
1185extern unsigned int ath5k_hw_get_def_antenna(struct ath5k_hw *ah);
1186extern int ath5k_hw_phy_disable(struct ath5k_hw *ah);
1187/* TX power setup */
1188extern int ath5k_hw_txpower(struct ath5k_hw *ah, struct net80211_channel *channel, u8 ee_mode, u8 txpower);
1189extern int ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 ee_mode, u8 txpower);
1190
1191/*
1192 * Functions used internaly
1193 */
1194
1195/*
1196 * Translate usec to hw clock units
1197 * TODO: Half/quarter rate
1198 */
1199static inline unsigned int ath5k_hw_htoclock(unsigned int usec, int turbo)
1200{
1201        return turbo ? (usec * 80) : (usec * 40);
1202}
1203
1204/*
1205 * Translate hw clock units to usec
1206 * TODO: Half/quarter rate
1207 */
1208static inline unsigned int ath5k_hw_clocktoh(unsigned int clock, int turbo)
1209{
1210        return turbo ? (clock / 80) : (clock / 40);
1211}
1212
1213/*
1214 * Read from a register
1215 */
1216static inline u32 ath5k_hw_reg_read(struct ath5k_hw *ah, u16 reg)
1217{
1218        return readl(ah->ah_iobase + reg);
1219}
1220
1221/*
1222 * Write to a register
1223 */
1224static inline void ath5k_hw_reg_write(struct ath5k_hw *ah, u32 val, u16 reg)
1225{
1226        writel(val, ah->ah_iobase + reg);
1227}
1228
1229#if defined(_ATH5K_RESET) || defined(_ATH5K_PHY)
1230/*
1231 * Check if a register write has been completed
1232 */
1233static int ath5k_hw_register_timeout(struct ath5k_hw *ah, u32 reg, u32 flag,
1234                u32 val, int is_set)
1235{
1236        int i;
1237        u32 data;
1238
1239        for (i = AR5K_TUNE_REGISTER_TIMEOUT; i > 0; i--) {
1240                data = ath5k_hw_reg_read(ah, reg);
1241                if (is_set && (data & flag))
1242                        break;
1243                else if ((data & flag) == val)
1244                        break;
1245                udelay(15);
1246        }
1247
1248        return (i <= 0) ? -EAGAIN : 0;
1249}
1250
1251/*
1252 * Convert channel frequency to channel number
1253 */
1254static inline int ath5k_freq_to_channel(int freq)
1255{
1256        if (freq == 2484)
1257                return 14;
1258
1259        if (freq < 2484)
1260                return (freq - 2407) / 5;
1261
1262        return freq/5 - 1000;
1263}
1264
1265#endif
1266
1267static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
1268{
1269        u32 retval = 0, bit, i;
1270
1271        for (i = 0; i < bits; i++) {
1272                bit = (val >> i) & 1;
1273                retval = (retval << 1) | bit;
1274        }
1275
1276        return retval;
1277}
1278
1279#endif
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