| 1 | /* |
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| 2 | * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org> |
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| 3 | * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com> |
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| 4 | * |
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| 5 | * Permission to use, copy, modify, and distribute this software for any |
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| 6 | * purpose with or without fee is hereby granted, provided that the above |
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| 7 | * copyright notice and this permission notice appear in all copies. |
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| 8 | * |
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| 9 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
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| 10 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
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| 11 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
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| 12 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
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| 13 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
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| 14 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
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| 15 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
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| 16 | * |
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| 17 | */ |
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| 18 | |
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| 19 | /* |
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| 20 | * Internal RX/TX descriptor structures |
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| 21 | * (rX: reserved fields possibily used by future versions of the ar5k chipset) |
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| 22 | */ |
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| 23 | |
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| 24 | /* |
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| 25 | * common hardware RX control descriptor |
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| 26 | */ |
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| 27 | struct ath5k_hw_rx_ctl { |
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| 28 | u32 rx_control_0; /* RX control word 0 */ |
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| 29 | u32 rx_control_1; /* RX control word 1 */ |
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| 30 | } __attribute__ ((packed)); |
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| 31 | |
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| 32 | /* RX control word 0 field/sflags */ |
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| 33 | #define AR5K_DESC_RX_CTL0 0x00000000 |
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| 34 | |
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| 35 | /* RX control word 1 fields/flags */ |
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| 36 | #define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff |
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| 37 | #define AR5K_DESC_RX_CTL1_INTREQ 0x00002000 |
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| 38 | |
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| 39 | /* |
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| 40 | * common hardware RX status descriptor |
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| 41 | * 5210/11 and 5212 differ only in the flags defined below |
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| 42 | */ |
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| 43 | struct ath5k_hw_rx_status { |
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| 44 | u32 rx_status_0; /* RX status word 0 */ |
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| 45 | u32 rx_status_1; /* RX status word 1 */ |
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| 46 | } __attribute__ ((packed)); |
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| 47 | |
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| 48 | /* 5210/5211 */ |
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| 49 | /* RX status word 0 fields/flags */ |
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| 50 | #define AR5K_5210_RX_DESC_STATUS0_DATA_LEN 0x00000fff |
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| 51 | #define AR5K_5210_RX_DESC_STATUS0_MORE 0x00001000 |
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| 52 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000 |
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| 53 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_RATE_S 15 |
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| 54 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000 |
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| 55 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19 |
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| 56 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000 |
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| 57 | #define AR5K_5210_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27 |
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| 58 | |
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| 59 | /* RX status word 1 fields/flags */ |
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| 60 | #define AR5K_5210_RX_DESC_STATUS1_DONE 0x00000001 |
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| 61 | #define AR5K_5210_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 |
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| 62 | #define AR5K_5210_RX_DESC_STATUS1_CRC_ERROR 0x00000004 |
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| 63 | #define AR5K_5210_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008 |
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| 64 | #define AR5K_5210_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010 |
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| 65 | #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR 0x000000e0 |
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| 66 | #define AR5K_5210_RX_DESC_STATUS1_PHY_ERROR_S 5 |
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| 67 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 |
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| 68 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX 0x00007e00 |
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| 69 | #define AR5K_5210_RX_DESC_STATUS1_KEY_INDEX_S 9 |
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| 70 | #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000 |
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| 71 | #define AR5K_5210_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15 |
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| 72 | #define AR5K_5210_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000 |
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| 73 | |
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| 74 | /* 5212 */ |
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| 75 | /* RX status word 0 fields/flags */ |
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| 76 | #define AR5K_5212_RX_DESC_STATUS0_DATA_LEN 0x00000fff |
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| 77 | #define AR5K_5212_RX_DESC_STATUS0_MORE 0x00001000 |
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| 78 | #define AR5K_5212_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000 |
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| 79 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000 |
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| 80 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_RATE_S 15 |
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| 81 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000 |
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| 82 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20 |
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| 83 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000 |
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| 84 | #define AR5K_5212_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28 |
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| 85 | |
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| 86 | /* RX status word 1 fields/flags */ |
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| 87 | #define AR5K_5212_RX_DESC_STATUS1_DONE 0x00000001 |
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| 88 | #define AR5K_5212_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002 |
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| 89 | #define AR5K_5212_RX_DESC_STATUS1_CRC_ERROR 0x00000004 |
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| 90 | #define AR5K_5212_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008 |
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| 91 | #define AR5K_5212_RX_DESC_STATUS1_PHY_ERROR 0x00000010 |
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| 92 | #define AR5K_5212_RX_DESC_STATUS1_MIC_ERROR 0x00000020 |
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| 93 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100 |
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| 94 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00 |
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| 95 | #define AR5K_5212_RX_DESC_STATUS1_KEY_INDEX_S 9 |
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| 96 | #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000 |
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| 97 | #define AR5K_5212_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16 |
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| 98 | #define AR5K_5212_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000 |
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| 99 | |
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| 100 | /* |
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| 101 | * common hardware RX error descriptor |
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| 102 | */ |
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| 103 | struct ath5k_hw_rx_error { |
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| 104 | u32 rx_error_0; /* RX status word 0 */ |
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| 105 | u32 rx_error_1; /* RX status word 1 */ |
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| 106 | } __attribute__ ((packed)); |
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| 107 | |
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| 108 | /* RX error word 0 fields/flags */ |
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| 109 | #define AR5K_RX_DESC_ERROR0 0x00000000 |
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| 110 | |
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| 111 | /* RX error word 1 fields/flags */ |
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| 112 | #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00 |
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| 113 | #define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8 |
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| 114 | |
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| 115 | /* PHY Error codes */ |
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| 116 | #define AR5K_DESC_RX_PHY_ERROR_NONE 0x00 |
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| 117 | #define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20 |
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| 118 | #define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40 |
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| 119 | #define AR5K_DESC_RX_PHY_ERROR_RATE 0x60 |
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| 120 | #define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80 |
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| 121 | #define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0 |
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| 122 | #define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0 |
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| 123 | #define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0 |
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| 124 | |
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| 125 | /* |
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| 126 | * 5210/5211 hardware 2-word TX control descriptor |
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| 127 | */ |
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| 128 | struct ath5k_hw_2w_tx_ctl { |
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| 129 | u32 tx_control_0; /* TX control word 0 */ |
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| 130 | u32 tx_control_1; /* TX control word 1 */ |
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| 131 | } __attribute__ ((packed)); |
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| 132 | |
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| 133 | /* TX control word 0 fields/flags */ |
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| 134 | #define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff |
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| 135 | #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/ |
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| 136 | #define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12 |
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| 137 | #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000 |
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| 138 | #define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18 |
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| 139 | #define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000 |
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| 140 | #define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000 |
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| 141 | #define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/ |
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| 142 | #define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/ |
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| 143 | #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/ |
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| 144 | #define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26 |
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| 145 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000 |
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| 146 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000 |
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| 147 | |
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| 148 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT \ |
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| 149 | (ah->ah_version == AR5K_AR5210 ? \ |
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| 150 | AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \ |
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| 151 | AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211) |
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| 152 | |
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| 153 | #define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 |
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| 154 | #define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000 |
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| 155 | #define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 |
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| 156 | |
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| 157 | /* TX control word 1 fields/flags */ |
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| 158 | #define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff |
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| 159 | #define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000 |
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| 160 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000 |
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| 161 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000 |
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| 162 | |
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| 163 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX \ |
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| 164 | (ah->ah_version == AR5K_AR5210 ? \ |
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| 165 | AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \ |
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| 166 | AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211) |
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| 167 | |
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| 168 | #define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 |
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| 169 | #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/ |
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| 170 | #define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20 |
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| 171 | #define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/ |
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| 172 | #define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/ |
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| 173 | |
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| 174 | /* Frame types */ |
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| 175 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00 |
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| 176 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04 |
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| 177 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08 |
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| 178 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c |
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| 179 | #define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10 |
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| 180 | |
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| 181 | /* |
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| 182 | * 5212 hardware 4-word TX control descriptor |
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| 183 | */ |
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| 184 | struct ath5k_hw_4w_tx_ctl { |
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| 185 | u32 tx_control_0; /* TX control word 0 */ |
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| 186 | |
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| 187 | #define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff |
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| 188 | #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000 |
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| 189 | #define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16 |
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| 190 | #define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000 |
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| 191 | #define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000 |
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| 192 | #define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000 |
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| 193 | #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000 |
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| 194 | #define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25 |
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| 195 | #define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000 |
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| 196 | #define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000 |
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| 197 | #define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000 |
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| 198 | |
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| 199 | u32 tx_control_1; /* TX control word 1 */ |
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| 200 | |
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| 201 | #define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff |
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| 202 | #define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000 |
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| 203 | #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000 |
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| 204 | #define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13 |
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| 205 | #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000 |
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| 206 | #define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20 |
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| 207 | #define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000 |
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| 208 | #define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000 |
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| 209 | #define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25 |
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| 210 | #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000 |
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| 211 | #define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27 |
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| 212 | #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000 |
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| 213 | #define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29 |
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| 214 | |
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| 215 | u32 tx_control_2; /* TX control word 2 */ |
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| 216 | |
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| 217 | #define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff |
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| 218 | #define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000 |
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| 219 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000 |
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| 220 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16 |
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| 221 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000 |
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| 222 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20 |
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| 223 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000 |
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| 224 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24 |
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| 225 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000 |
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| 226 | #define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28 |
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| 227 | |
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| 228 | u32 tx_control_3; /* TX control word 3 */ |
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| 229 | |
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| 230 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f |
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| 231 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0 |
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| 232 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5 |
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| 233 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00 |
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| 234 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10 |
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| 235 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000 |
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| 236 | #define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15 |
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| 237 | #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000 |
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| 238 | #define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20 |
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| 239 | } __attribute__ ((packed)); |
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| 240 | |
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| 241 | /* |
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| 242 | * Common TX status descriptor |
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| 243 | */ |
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| 244 | struct ath5k_hw_tx_status { |
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| 245 | u32 tx_status_0; /* TX status word 0 */ |
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| 246 | u32 tx_status_1; /* TX status word 1 */ |
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| 247 | } __attribute__ ((packed)); |
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| 248 | |
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| 249 | /* TX status word 0 fields/flags */ |
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| 250 | #define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001 |
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| 251 | #define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002 |
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| 252 | #define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004 |
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| 253 | #define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008 |
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| 254 | /*??? |
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| 255 | #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0 |
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| 256 | #define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4 |
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| 257 | */ |
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| 258 | #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0 |
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| 259 | #define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4 |
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| 260 | /*??? |
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| 261 | #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00 |
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| 262 | #define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8 |
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| 263 | */ |
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| 264 | #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00 |
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| 265 | #define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8 |
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| 266 | #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000 |
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| 267 | #define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12 |
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| 268 | #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000 |
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| 269 | #define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16 |
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| 270 | |
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| 271 | /* TX status word 1 fields/flags */ |
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| 272 | #define AR5K_DESC_TX_STATUS1_DONE 0x00000001 |
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| 273 | #define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe |
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| 274 | #define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1 |
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| 275 | #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000 |
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| 276 | #define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13 |
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| 277 | #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000 |
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| 278 | #define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21 |
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| 279 | #define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000 |
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| 280 | #define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000 |
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| 281 | |
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| 282 | /* |
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| 283 | * 5210/5211 hardware TX descriptor |
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| 284 | */ |
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| 285 | struct ath5k_hw_5210_tx_desc { |
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| 286 | struct ath5k_hw_2w_tx_ctl tx_ctl; |
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| 287 | struct ath5k_hw_tx_status tx_stat; |
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| 288 | } __attribute__ ((packed)); |
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| 289 | |
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| 290 | /* |
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| 291 | * 5212 hardware TX descriptor |
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| 292 | */ |
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| 293 | struct ath5k_hw_5212_tx_desc { |
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| 294 | struct ath5k_hw_4w_tx_ctl tx_ctl; |
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| 295 | struct ath5k_hw_tx_status tx_stat; |
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| 296 | } __attribute__ ((packed)); |
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| 297 | |
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| 298 | /* |
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| 299 | * common hardware RX descriptor |
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| 300 | */ |
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| 301 | struct ath5k_hw_all_rx_desc { |
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| 302 | struct ath5k_hw_rx_ctl rx_ctl; |
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| 303 | union { |
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| 304 | struct ath5k_hw_rx_status rx_stat; |
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| 305 | struct ath5k_hw_rx_error rx_err; |
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| 306 | } u; |
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| 307 | } __attribute__ ((packed)); |
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| 308 | |
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| 309 | /* |
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| 310 | * Atheros hardware descriptor |
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| 311 | * This is read and written to by the hardware |
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| 312 | */ |
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| 313 | struct ath5k_desc { |
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| 314 | u32 ds_link; /* physical address of the next descriptor */ |
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| 315 | u32 ds_data; /* physical address of data buffer (skb) */ |
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| 316 | |
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| 317 | union { |
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| 318 | struct ath5k_hw_5210_tx_desc ds_tx5210; |
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| 319 | struct ath5k_hw_5212_tx_desc ds_tx5212; |
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| 320 | struct ath5k_hw_all_rx_desc ds_rx; |
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| 321 | } ud; |
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| 322 | } __attribute__ ((packed)); |
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| 323 | |
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| 324 | #define AR5K_RXDESC_INTREQ 0x0020 |
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| 325 | |
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| 326 | #define AR5K_TXDESC_CLRDMASK 0x0001 |
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| 327 | #define AR5K_TXDESC_NOACK 0x0002 /*[5211+]*/ |
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| 328 | #define AR5K_TXDESC_RTSENA 0x0004 |
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| 329 | #define AR5K_TXDESC_CTSENA 0x0008 |
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| 330 | #define AR5K_TXDESC_INTREQ 0x0010 |
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| 331 | #define AR5K_TXDESC_VEOL 0x0020 /*[5211+]*/ |
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| 332 | |
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