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source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/atl1e.c @ e16e8f2

Last change on this file since e16e8f2 was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago
bootstuff
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File size: 45.0 KB

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1	/*
2	* Copyright(c) 2007 Atheros Corporation. All rights reserved.
3	*
4	* Derived from Intel e1000 driver
5	* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
6	*
7	* Modified for gPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>.
8	*
9	* This program is free software; you can redistribute it and/or modify it
10	* under the terms of the GNU General Public License as published by the Free
11	* Software Foundation; either version 2 of the License, or (at your option)
12	* any later version.
13	*
14	* This program is distributed in the hope that it will be useful, but WITHOUT
15	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17	* more details.
18	*
19	* You should have received a copy of the GNU General Public License along with
20	* this program; if not, write to the Free Software Foundation, Inc., 59
21	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22	*/
23
24	FILE_LICENCE ( GPL2_OR_LATER );
25
26	#include "atl1e.h"
27
28	/* User-tweakable parameters: */
29	#define TX_DESC_COUNT 32 /* TX descriptors, minimum 32 */
30	#define RX_MEM_SIZE 8192 /* RX area size, minimum 8kb */
31	#define MAX_FRAME_SIZE 1500 /* Maximum MTU supported, minimum 1500 */
32
33	/* Arcane parameters: */
34	#define PREAMBLE_LEN 7
35	#define RX_JUMBO_THRESH ((MAX_FRAME_SIZE + ETH_HLEN + \
36	VLAN_HLEN + ETH_FCS_LEN + 7) >> 3)
37	#define IMT_VAL 100 /* interrupt moderator timer, us */
38	#define ICT_VAL 50000 /* interrupt clear timer, us */
39	#define SMB_TIMER 200000
40	#define RRD_THRESH 1 /* packets to queue before interrupt */
41	#define TPD_BURST 5
42	#define TPD_THRESH (TX_DESC_COUNT / 2)
43	#define RX_COUNT_DOWN 4
44	#define TX_COUNT_DOWN (IMT_VAL * 4 / 3)
45	#define DMAR_DLY_CNT 15
46	#define DMAW_DLY_CNT 4
47
48	#define PCI_DEVICE_ID_ATTANSIC_L1E 0x1026
49
50	/*
51	* atl1e_pci_tbl - PCI Device ID Table
52	*
53	* Wildcard entries (PCI_ANY_ID) should come last
54	* Last entry must be all 0s
55	*
56	* { Vendor ID, Device ID, SubVendor ID, SubDevice ID,
57	* Class, Class Mask, private data (not used) }
58	*/
59	static struct pci_device_id atl1e_pci_tbl[] = {
60	PCI_ROM(0x1969, 0x1026, "atl1e_26", "Attansic L1E 0x1026", 0),
61	PCI_ROM(0x1969, 0x1066, "atl1e_66", "Attansic L1E 0x1066", 0),
62	};
63
64	static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter);
65
66	static const u16
67	atl1e_rx_page_vld_regs[AT_PAGE_NUM_PER_QUEUE] =
68	{
69	REG_HOST_RXF0_PAGE0_VLD, REG_HOST_RXF0_PAGE1_VLD
70	};
71
72	static const u16
73	atl1e_rx_page_lo_addr_regs[AT_PAGE_NUM_PER_QUEUE] =
74	{
75	REG_HOST_RXF0_PAGE0_LO, REG_HOST_RXF0_PAGE1_LO
76	};
77
78	static const u16
79	atl1e_rx_page_write_offset_regs[AT_PAGE_NUM_PER_QUEUE] =
80	{
81	REG_HOST_RXF0_MB0_LO, REG_HOST_RXF0_MB1_LO
82	};
83
84	static const u16 atl1e_pay_load_size[] = {
85	128, 256, 512, 1024, 2048, 4096,
86	};
87
88	/*
89	* atl1e_irq_enable - Enable default interrupt generation settings
90	* @adapter: board private structure
91	*/
92	static inline void atl1e_irq_enable(struct atl1e_adapter *adapter)
93	{
94	AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
95	AT_WRITE_REG(&adapter->hw, REG_IMR, IMR_NORMAL_MASK);
96	AT_WRITE_FLUSH(&adapter->hw);
97	}
98
99	/*
100	* atl1e_irq_disable - Mask off interrupt generation on the NIC
101	* @adapter: board private structure
102	*/
103	static inline void atl1e_irq_disable(struct atl1e_adapter *adapter)
104	{
105	AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
106	AT_WRITE_FLUSH(&adapter->hw);
107	}
108
109	/*
110	* atl1e_irq_reset - reset interrupt confiure on the NIC
111	* @adapter: board private structure
112	*/
113	static inline void atl1e_irq_reset(struct atl1e_adapter *adapter)
114	{
115	AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
116	AT_WRITE_REG(&adapter->hw, REG_IMR, 0);
117	AT_WRITE_FLUSH(&adapter->hw);
118	}
119
120	static void atl1e_reset(struct atl1e_adapter *adapter)
121	{
122	atl1e_down(adapter);
123	atl1e_up(adapter);
124	}
125
126	static int atl1e_check_link(struct atl1e_adapter *adapter)
127	{
128	struct atl1e_hw *hw = &adapter->hw;
129	struct net_device *netdev = adapter->netdev;
130	int err = 0;
131	u16 speed, duplex, phy_data;
132
133	/* MII_BMSR must read twise */
134	atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
135	atl1e_read_phy_reg(hw, MII_BMSR, &phy_data);
136
137	if ((phy_data & BMSR_LSTATUS) == 0) {
138	/* link down */
139	if (netdev_link_ok(netdev)) { /* old link state: Up */
140	u32 value;
141	/* disable rx */
142	value = AT_READ_REG(hw, REG_MAC_CTRL);
143	value &= ~MAC_CTRL_RX_EN;
144	AT_WRITE_REG(hw, REG_MAC_CTRL, value);
145	adapter->link_speed = SPEED_0;
146
147	DBG("atl1e: %s link is down\n", netdev->name);
148	netdev_link_down(netdev);
149	}
150	} else {
151	/* Link Up */
152	err = atl1e_get_speed_and_duplex(hw, &speed, &duplex);
153	if (err)
154	return err;
155
156	/* link result is our setting */
157	if (adapter->link_speed != speed \|\|
158	adapter->link_duplex != duplex) {
159	adapter->link_speed = speed;
160	adapter->link_duplex = duplex;
161	atl1e_setup_mac_ctrl(adapter);
162
163	DBG("atl1e: %s link is up, %d Mbps, %s duplex\n",
164	netdev->name, adapter->link_speed,
165	adapter->link_duplex == FULL_DUPLEX ?
166	"full" : "half");
167	netdev_link_up(netdev);
168	}
169	}
170	return 0;
171	}
172
173	static int atl1e_mdio_read(struct net_device *netdev, int phy_id __unused,
174	int reg_num)
175	{
176	struct atl1e_adapter *adapter = netdev_priv(netdev);
177	u16 result;
178
179	atl1e_read_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, &result);
180	return result;
181	}
182
183	static void atl1e_mdio_write(struct net_device *netdev, int phy_id __unused,
184	int reg_num, int val)
185	{
186	struct atl1e_adapter *adapter = netdev_priv(netdev);
187
188	atl1e_write_phy_reg(&adapter->hw, reg_num & MDIO_REG_ADDR_MASK, val);
189	}
190
191	static void atl1e_setup_pcicmd(struct pci_device *pdev)
192	{
193	u16 cmd;
194
195	pci_read_config_word(pdev, PCI_COMMAND, &cmd);
196	cmd \|= (PCI_COMMAND_MEM \| PCI_COMMAND_MASTER);
197	pci_write_config_word(pdev, PCI_COMMAND, cmd);
198
199	/*
200	* some motherboards BIOS(PXE/EFI) driver may set PME
201	* while they transfer control to OS (Windows/Linux)
202	* so we should clear this bit before NIC work normally
203	*/
204	pci_write_config_dword(pdev, REG_PM_CTRLSTAT, 0);
205	mdelay(1);
206	}
207
208	/*
209	* atl1e_sw_init - Initialize general software structures (struct atl1e_adapter)
210	* @adapter: board private structure to initialize
211	*
212	* atl1e_sw_init initializes the Adapter private data structure.
213	* Fields are initialized based on PCI device information and
214	* OS network device settings (MTU size).
215	*/
216	static int atl1e_sw_init(struct atl1e_adapter *adapter)
217	{
218	struct atl1e_hw *hw = &adapter->hw;
219	struct pci_device *pdev = adapter->pdev;
220	u32 phy_status_data = 0;
221	u8 rev_id = 0;
222
223	adapter->link_speed = SPEED_0; /* hardware init */
224	adapter->link_duplex = FULL_DUPLEX;
225
226	/* PCI config space info */
227	pci_read_config_byte(pdev, PCI_REVISION_ID, &rev_id);
228
229	phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
230	/* nic type */
231	if (rev_id >= 0xF0) {
232	hw->nic_type = athr_l2e_revB;
233	} else {
234	if (phy_status_data & PHY_STATUS_100M)
235	hw->nic_type = athr_l1e;
236	else
237	hw->nic_type = athr_l2e_revA;
238	}
239
240	phy_status_data = AT_READ_REG(hw, REG_PHY_STATUS);
241
242	hw->emi_ca = !!(phy_status_data & PHY_STATUS_EMI_CA);
243
244	hw->phy_configured = 0;
245
246	/* need confirm */
247
248	hw->dmar_block = atl1e_dma_req_1024;
249	hw->dmaw_block = atl1e_dma_req_1024;
250
251	netdev_link_down(adapter->netdev);
252
253	return 0;
254	}
255
256	/*
257	* atl1e_clean_tx_ring - free all Tx buffers for device close
258	* @adapter: board private structure
259	*/
260	static void atl1e_clean_tx_ring(struct atl1e_adapter *adapter)
261	{
262	struct atl1e_tx_ring tx_ring = (struct atl1e_tx_ring )
263	&adapter->tx_ring;
264	struct atl1e_tx_buffer *tx_buffer = NULL;
265	u16 index, ring_count = tx_ring->count;
266
267	if (tx_ring->desc == NULL \|\| tx_ring->tx_buffer == NULL)
268	return;
269
270	for (index = 0; index < ring_count; index++) {
271	tx_buffer = &tx_ring->tx_buffer[index];
272	if (tx_buffer->iob) {
273	netdev_tx_complete(adapter->netdev, tx_buffer->iob);
274	tx_buffer->dma = 0;
275	tx_buffer->iob = NULL;
276	}
277	}
278
279	/* Zero out Tx-buffers */
280	memset(tx_ring->desc, 0, sizeof(struct atl1e_tpd_desc) *
281	ring_count);
282	memset(tx_ring->tx_buffer, 0, sizeof(struct atl1e_tx_buffer) *
283	ring_count);
284	}
285
286	/*
287	* atl1e_clean_rx_ring - Free rx-reservation iobs
288	* @adapter: board private structure
289	*/
290	static void atl1e_clean_rx_ring(struct atl1e_adapter *adapter)
291	{
292	struct atl1e_rx_ring *rx_ring =
293	(struct atl1e_rx_ring *)&adapter->rx_ring;
294	struct atl1e_rx_page_desc *rx_page_desc = &rx_ring->rx_page_desc;
295	u16 j;
296
297	if (adapter->ring_vir_addr == NULL)
298	return;
299
300	/* Zero out the descriptor ring */
301	for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
302	if (rx_page_desc->rx_page[j].addr != NULL) {
303	memset(rx_page_desc->rx_page[j].addr, 0,
304	rx_ring->real_page_size);
305	}
306	}
307	}
308
309	static void atl1e_cal_ring_size(struct atl1e_adapter adapter, u32 ring_size)
310	{
311	ring_size = ((u32)(adapter->tx_ring.count
312	sizeof(struct atl1e_tpd_desc) + 7
313	/* tx ring, qword align */
314	+ adapter->rx_ring.real_page_size * AT_PAGE_NUM_PER_QUEUE
315	+ 31
316	/* rx ring, 32 bytes align */
317	+ (1 + AT_PAGE_NUM_PER_QUEUE) *
318	sizeof(u32) + 3));
319	/* tx, rx cmd, dword align */
320	}
321
322	static void atl1e_init_ring_resources(struct atl1e_adapter *adapter)
323	{
324	struct atl1e_tx_ring *tx_ring = NULL;
325	struct atl1e_rx_ring *rx_ring = NULL;
326
327	tx_ring = &adapter->tx_ring;
328	rx_ring = &adapter->rx_ring;
329
330	rx_ring->real_page_size = adapter->rx_ring.page_size
331	+ MAX_FRAME_SIZE
332	+ ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
333	rx_ring->real_page_size = (rx_ring->real_page_size + 31) & ~31;
334	atl1e_cal_ring_size(adapter, &adapter->ring_size);
335
336	adapter->ring_vir_addr = NULL;
337	adapter->rx_ring.desc = NULL;
338
339	return;
340	}
341
342	/*
343	* Read / Write Ptr Initialize:
344	*/
345	static void atl1e_init_ring_ptrs(struct atl1e_adapter *adapter)
346	{
347	struct atl1e_tx_ring *tx_ring = NULL;
348	struct atl1e_rx_ring *rx_ring = NULL;
349	struct atl1e_rx_page_desc *rx_page_desc = NULL;
350	int j;
351
352	tx_ring = &adapter->tx_ring;
353	rx_ring = &adapter->rx_ring;
354	rx_page_desc = &rx_ring->rx_page_desc;
355
356	tx_ring->next_to_use = 0;
357	tx_ring->next_to_clean = 0;
358
359	rx_page_desc->rx_using = 0;
360	rx_page_desc->rx_nxseq = 0;
361	for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
362	*rx_page_desc->rx_page[j].write_offset_addr = 0;
363	rx_page_desc->rx_page[j].read_offset = 0;
364	}
365	}
366
367	/*
368	* atl1e_free_ring_resources - Free Tx / RX descriptor Resources
369	* @adapter: board private structure
370	*
371	* Free all transmit software resources
372	*/
373	static void atl1e_free_ring_resources(struct atl1e_adapter *adapter)
374	{
375	atl1e_clean_tx_ring(adapter);
376	atl1e_clean_rx_ring(adapter);
377
378	if (adapter->ring_vir_addr) {
379	free_dma(adapter->ring_vir_addr, adapter->ring_size);
380	adapter->ring_vir_addr = NULL;
381	adapter->ring_dma = 0;
382	}
383
384	if (adapter->tx_ring.tx_buffer) {
385	free(adapter->tx_ring.tx_buffer);
386	adapter->tx_ring.tx_buffer = NULL;
387	}
388	}
389
390	/*
391	* atl1e_setup_mem_resources - allocate Tx / RX descriptor resources
392	* @adapter: board private structure
393	*
394	* Return 0 on success, negative on failure
395	*/
396	static int atl1e_setup_ring_resources(struct atl1e_adapter *adapter)
397	{
398	struct atl1e_tx_ring *tx_ring;
399	struct atl1e_rx_ring *rx_ring;
400	struct atl1e_rx_page_desc *rx_page_desc;
401	int size, j;
402	u32 offset = 0;
403	int err = 0;
404
405	if (adapter->ring_vir_addr != NULL)
406	return 0; /* alloced already */
407
408	tx_ring = &adapter->tx_ring;
409	rx_ring = &adapter->rx_ring;
410
411	/* real ring DMA buffer */
412
413	size = adapter->ring_size;
414	adapter->ring_vir_addr = malloc_dma(adapter->ring_size, 32);
415
416	if (adapter->ring_vir_addr == NULL) {
417	DBG("atl1e: out of memory allocating %d bytes for %s ring\n",
418	adapter->ring_size, adapter->netdev->name);
419	return -ENOMEM;
420	}
421
422	adapter->ring_dma = virt_to_bus(adapter->ring_vir_addr);
423	memset(adapter->ring_vir_addr, 0, adapter->ring_size);
424
425	rx_page_desc = &rx_ring->rx_page_desc;
426
427	/* Init TPD Ring */
428	tx_ring->dma = (adapter->ring_dma + 7) & ~7;
429	offset = tx_ring->dma - adapter->ring_dma;
430	tx_ring->desc = (struct atl1e_tpd_desc *)
431	(adapter->ring_vir_addr + offset);
432	size = sizeof(struct atl1e_tx_buffer) * (tx_ring->count);
433	tx_ring->tx_buffer = zalloc(size);
434	if (tx_ring->tx_buffer == NULL) {
435	DBG("atl1e: out of memory allocating %d bytes for %s txbuf\n",
436	size, adapter->netdev->name);
437	err = -ENOMEM;
438	goto failed;
439	}
440
441	/* Init RXF-Pages */
442	offset += (sizeof(struct atl1e_tpd_desc) * tx_ring->count);
443	offset = (offset + 31) & ~31;
444
445	for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
446	rx_page_desc->rx_page[j].dma =
447	adapter->ring_dma + offset;
448	rx_page_desc->rx_page[j].addr =
449	adapter->ring_vir_addr + offset;
450	offset += rx_ring->real_page_size;
451	}
452
453	/* Init CMB dma address */
454	tx_ring->cmb_dma = adapter->ring_dma + offset;
455	tx_ring->cmb = (u32 *)(adapter->ring_vir_addr + offset);
456	offset += sizeof(u32);
457
458	for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
459	rx_page_desc->rx_page[j].write_offset_dma =
460	adapter->ring_dma + offset;
461	rx_page_desc->rx_page[j].write_offset_addr =
462	adapter->ring_vir_addr + offset;
463	offset += sizeof(u32);
464	}
465
466	if (offset > adapter->ring_size) {
467	DBG("atl1e: ring miscalculation! need %d > %d bytes\n",
468	offset, adapter->ring_size);
469	err = -EINVAL;
470	goto failed;
471	}
472
473	return 0;
474	failed:
475	atl1e_free_ring_resources(adapter);
476	return err;
477	}
478
479	static inline void atl1e_configure_des_ring(const struct atl1e_adapter *adapter)
480	{
481
482	struct atl1e_hw hw = (struct atl1e_hw )&adapter->hw;
483	struct atl1e_rx_ring *rx_ring =
484	(struct atl1e_rx_ring *)&adapter->rx_ring;
485	struct atl1e_tx_ring *tx_ring =
486	(struct atl1e_tx_ring *)&adapter->tx_ring;
487	struct atl1e_rx_page_desc *rx_page_desc = NULL;
488	int j;
489
490	AT_WRITE_REG(hw, REG_DESC_BASE_ADDR_HI, 0);
491	AT_WRITE_REG(hw, REG_TPD_BASE_ADDR_LO, tx_ring->dma);
492	AT_WRITE_REG(hw, REG_TPD_RING_SIZE, (u16)(tx_ring->count));
493	AT_WRITE_REG(hw, REG_HOST_TX_CMB_LO, tx_ring->cmb_dma);
494
495	rx_page_desc = &rx_ring->rx_page_desc;
496
497	/* RXF Page Physical address / Page Length */
498	AT_WRITE_REG(hw, REG_RXF0_BASE_ADDR_HI, 0);
499
500	for (j = 0; j < AT_PAGE_NUM_PER_QUEUE; j++) {
501	u32 page_phy_addr;
502	u32 offset_phy_addr;
503
504	page_phy_addr = rx_page_desc->rx_page[j].dma;
505	offset_phy_addr = rx_page_desc->rx_page[j].write_offset_dma;
506
507	AT_WRITE_REG(hw, atl1e_rx_page_lo_addr_regs[j], page_phy_addr);
508	AT_WRITE_REG(hw, atl1e_rx_page_write_offset_regs[j],
509	offset_phy_addr);
510	AT_WRITE_REGB(hw, atl1e_rx_page_vld_regs[j], 1);
511	}
512
513	/* Page Length */
514	AT_WRITE_REG(hw, REG_HOST_RXFPAGE_SIZE, rx_ring->page_size);
515	/* Load all of base address above */
516	AT_WRITE_REG(hw, REG_LOAD_PTR, 1);
517
518	return;
519	}
520
521	static inline void atl1e_configure_tx(struct atl1e_adapter *adapter)
522	{
523	struct atl1e_hw hw = (struct atl1e_hw )&adapter->hw;
524	u32 dev_ctrl_data = 0;
525	u32 max_pay_load = 0;
526	u32 jumbo_thresh = 0;
527	u32 extra_size = 0; /* Jumbo frame threshold in QWORD unit */
528
529	/* configure TXQ param */
530	if (hw->nic_type != athr_l2e_revB) {
531	extra_size = ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN;
532	jumbo_thresh = MAX_FRAME_SIZE + extra_size;
533	AT_WRITE_REG(hw, REG_TX_EARLY_TH, (jumbo_thresh + 7) >> 3);
534	}
535
536	dev_ctrl_data = AT_READ_REG(hw, REG_DEVICE_CTRL);
537
538	max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_PAYLOAD_SHIFT)) &
539	DEVICE_CTRL_MAX_PAYLOAD_MASK;
540	if (max_pay_load < hw->dmaw_block)
541	hw->dmaw_block = max_pay_load;
542
543	max_pay_load = ((dev_ctrl_data >> DEVICE_CTRL_MAX_RREQ_SZ_SHIFT)) &
544	DEVICE_CTRL_MAX_RREQ_SZ_MASK;
545	if (max_pay_load < hw->dmar_block)
546	hw->dmar_block = max_pay_load;
547
548	if (hw->nic_type != athr_l2e_revB)
549	AT_WRITE_REGW(hw, REG_TXQ_CTRL + 2,
550	atl1e_pay_load_size[hw->dmar_block]);
551	/* enable TXQ */
552	AT_WRITE_REGW(hw, REG_TXQ_CTRL,
553	((TPD_BURST & TXQ_CTRL_NUM_TPD_BURST_MASK)
554	<< TXQ_CTRL_NUM_TPD_BURST_SHIFT)
555	\| TXQ_CTRL_ENH_MODE \| TXQ_CTRL_EN);
556	return;
557	}
558
559	static inline void atl1e_configure_rx(struct atl1e_adapter *adapter)
560	{
561	struct atl1e_hw hw = (struct atl1e_hw )&adapter->hw;
562	u32 rxf_len = 0;
563	u32 rxf_low = 0;
564	u32 rxf_high = 0;
565	u32 rxf_thresh_data = 0;
566	u32 rxq_ctrl_data = 0;
567
568	if (hw->nic_type != athr_l2e_revB) {
569	AT_WRITE_REGW(hw, REG_RXQ_JMBOSZ_RRDTIM,
570	(u16)((RX_JUMBO_THRESH & RXQ_JMBOSZ_TH_MASK) <<
571	RXQ_JMBOSZ_TH_SHIFT \|
572	(1 & RXQ_JMBO_LKAH_MASK) <<
573	RXQ_JMBO_LKAH_SHIFT));
574
575	rxf_len = AT_READ_REG(hw, REG_SRAM_RXF_LEN);
576	rxf_high = rxf_len * 4 / 5;
577	rxf_low = rxf_len / 5;
578	rxf_thresh_data = ((rxf_high & RXQ_RXF_PAUSE_TH_HI_MASK)
579	<< RXQ_RXF_PAUSE_TH_HI_SHIFT) \|
580	((rxf_low & RXQ_RXF_PAUSE_TH_LO_MASK)
581	<< RXQ_RXF_PAUSE_TH_LO_SHIFT);
582
583	AT_WRITE_REG(hw, REG_RXQ_RXF_PAUSE_THRESH, rxf_thresh_data);
584	}
585
586	/* RRS */
587	AT_WRITE_REG(hw, REG_IDT_TABLE, 0);
588	AT_WRITE_REG(hw, REG_BASE_CPU_NUMBER, 0);
589
590	rxq_ctrl_data \|= RXQ_CTRL_PBA_ALIGN_32 \|
591	RXQ_CTRL_CUT_THRU_EN \| RXQ_CTRL_EN;
592
593	AT_WRITE_REG(hw, REG_RXQ_CTRL, rxq_ctrl_data);
594	return;
595	}
596
597	static inline void atl1e_configure_dma(struct atl1e_adapter *adapter)
598	{
599	struct atl1e_hw *hw = &adapter->hw;
600	u32 dma_ctrl_data = 0;
601
602	dma_ctrl_data = DMA_CTRL_RXCMB_EN;
603	dma_ctrl_data \|= (((u32)hw->dmar_block) & DMA_CTRL_DMAR_BURST_LEN_MASK)
604	<< DMA_CTRL_DMAR_BURST_LEN_SHIFT;
605	dma_ctrl_data \|= (((u32)hw->dmaw_block) & DMA_CTRL_DMAW_BURST_LEN_MASK)
606	<< DMA_CTRL_DMAW_BURST_LEN_SHIFT;
607	dma_ctrl_data \|= DMA_CTRL_DMAR_REQ_PRI \| DMA_CTRL_DMAR_OUT_ORDER;
608	dma_ctrl_data \|= (DMAR_DLY_CNT & DMA_CTRL_DMAR_DLY_CNT_MASK)
609	<< DMA_CTRL_DMAR_DLY_CNT_SHIFT;
610	dma_ctrl_data \|= (DMAW_DLY_CNT & DMA_CTRL_DMAW_DLY_CNT_MASK)
611	<< DMA_CTRL_DMAW_DLY_CNT_SHIFT;
612
613	AT_WRITE_REG(hw, REG_DMA_CTRL, dma_ctrl_data);
614	return;
615	}
616
617	static void atl1e_setup_mac_ctrl(struct atl1e_adapter *adapter)
618	{
619	u32 value;
620	struct atl1e_hw *hw = &adapter->hw;
621
622	/* Config MAC CTRL Register */
623	value = MAC_CTRL_TX_EN \|
624	MAC_CTRL_RX_EN ;
625
626	if (FULL_DUPLEX == adapter->link_duplex)
627	value \|= MAC_CTRL_DUPLX;
628
629	value \|= ((u32)((SPEED_1000 == adapter->link_speed) ?
630	MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100) <<
631	MAC_CTRL_SPEED_SHIFT);
632	value \|= (MAC_CTRL_TX_FLOW \| MAC_CTRL_RX_FLOW);
633
634	value \|= (MAC_CTRL_ADD_CRC \| MAC_CTRL_PAD);
635	value \|= ((PREAMBLE_LEN & MAC_CTRL_PRMLEN_MASK) << MAC_CTRL_PRMLEN_SHIFT);
636
637	value \|= MAC_CTRL_BC_EN;
638	value \|= MAC_CTRL_MC_ALL_EN;
639
640	AT_WRITE_REG(hw, REG_MAC_CTRL, value);
641	}
642
643	/*
644	* atl1e_configure - Configure Transmit&Receive Unit after Reset
645	* @adapter: board private structure
646	*
647	* Configure the Tx /Rx unit of the MAC after a reset.
648	*/
649	static int atl1e_configure(struct atl1e_adapter *adapter)
650	{
651	struct atl1e_hw *hw = &adapter->hw;
652	u32 intr_status_data = 0;
653
654	/* clear interrupt status */
655	AT_WRITE_REG(hw, REG_ISR, ~0);
656
657	/* 1. set MAC Address */
658	atl1e_hw_set_mac_addr(hw);
659
660	/* 2. Init the Multicast HASH table (clear) */
661	AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
662	AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
663
664	/* 3. Clear any WOL status */
665	AT_WRITE_REG(hw, REG_WOL_CTRL, 0);
666
667	/* 4. Descripter Ring BaseMem/Length/Read ptr/Write ptr
668	* TPD Ring/SMB/RXF0 Page CMBs, they use the same
669	* High 32bits memory */
670	atl1e_configure_des_ring(adapter);
671
672	/* 5. set Interrupt Moderator Timer */
673	AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER_INIT, IMT_VAL);
674	AT_WRITE_REGW(hw, REG_IRQ_MODU_TIMER2_INIT, IMT_VAL);
675	AT_WRITE_REG(hw, REG_MASTER_CTRL, MASTER_CTRL_LED_MODE \|
676	MASTER_CTRL_ITIMER_EN \| MASTER_CTRL_ITIMER2_EN);
677
678	/* 6. rx/tx threshold to trig interrupt */
679	AT_WRITE_REGW(hw, REG_TRIG_RRD_THRESH, RRD_THRESH);
680	AT_WRITE_REGW(hw, REG_TRIG_TPD_THRESH, TPD_THRESH);
681	AT_WRITE_REGW(hw, REG_TRIG_RXTIMER, RX_COUNT_DOWN);
682	AT_WRITE_REGW(hw, REG_TRIG_TXTIMER, TX_COUNT_DOWN);
683
684	/* 7. set Interrupt Clear Timer */
685	AT_WRITE_REGW(hw, REG_CMBDISDMA_TIMER, ICT_VAL);
686
687	/* 8. set MTU */
688	AT_WRITE_REG(hw, REG_MTU, MAX_FRAME_SIZE + ETH_HLEN +
689	VLAN_HLEN + ETH_FCS_LEN);
690
691	/* 9. config TXQ early tx threshold */
692	atl1e_configure_tx(adapter);
693
694	/* 10. config RXQ */
695	atl1e_configure_rx(adapter);
696
697	/* 11. config DMA Engine */
698	atl1e_configure_dma(adapter);
699
700	/* 12. smb timer to trig interrupt */
701	AT_WRITE_REG(hw, REG_SMB_STAT_TIMER, SMB_TIMER);
702
703	intr_status_data = AT_READ_REG(hw, REG_ISR);
704	if ((intr_status_data & ISR_PHY_LINKDOWN) != 0) {
705	DBG("atl1e: configure failed, PCIE phy link down\n");
706	return -1;
707	}
708
709	AT_WRITE_REG(hw, REG_ISR, 0x7fffffff);
710	return 0;
711	}
712
713	static inline void atl1e_clear_phy_int(struct atl1e_adapter *adapter)
714	{
715	u16 phy_data;
716
717	atl1e_read_phy_reg(&adapter->hw, MII_INT_STATUS, &phy_data);
718	}
719
720	static int atl1e_clean_tx_irq(struct atl1e_adapter *adapter)
721	{
722	struct atl1e_tx_ring tx_ring = (struct atl1e_tx_ring )
723	&adapter->tx_ring;
724	struct atl1e_tx_buffer *tx_buffer = NULL;
725	u16 hw_next_to_clean = AT_READ_REGW(&adapter->hw, REG_TPD_CONS_IDX);
726	u16 next_to_clean = tx_ring->next_to_clean;
727
728	while (next_to_clean != hw_next_to_clean) {
729	tx_buffer = &tx_ring->tx_buffer[next_to_clean];
730
731	tx_buffer->dma = 0;
732	if (tx_buffer->iob) {
733	netdev_tx_complete(adapter->netdev, tx_buffer->iob);
734	tx_buffer->iob = NULL;
735	}
736
737	if (++next_to_clean == tx_ring->count)
738	next_to_clean = 0;
739	}
740
741	tx_ring->next_to_clean = next_to_clean;
742
743	return 1;
744	}
745
746	static struct atl1e_rx_page atl1e_get_rx_page(struct atl1e_adapter adapter)
747	{
748	struct atl1e_rx_page_desc *rx_page_desc =
749	(struct atl1e_rx_page_desc *) &adapter->rx_ring.rx_page_desc;
750	u8 rx_using = rx_page_desc->rx_using;
751
752	return (struct atl1e_rx_page *)&(rx_page_desc->rx_page[rx_using]);
753	}
754
755	static void atl1e_clean_rx_irq(struct atl1e_adapter *adapter)
756	{
757	struct net_device *netdev = adapter->netdev;
758	struct atl1e_rx_ring rx_ring = (struct atl1e_rx_ring )
759	&adapter->rx_ring;
760	struct atl1e_rx_page_desc *rx_page_desc =
761	(struct atl1e_rx_page_desc *) &rx_ring->rx_page_desc;
762	struct io_buffer *iob = NULL;
763	struct atl1e_rx_page *rx_page = atl1e_get_rx_page(adapter);
764	u32 packet_size, write_offset;
765	struct atl1e_recv_ret_status *prrs;
766
767	write_offset = *(rx_page->write_offset_addr);
768	if (rx_page->read_offset >= write_offset)
769	return;
770
771	do {
772	/* get new packet's rrs */
773	prrs = (struct atl1e_recv_ret_status *) (rx_page->addr +
774	rx_page->read_offset);
775	/* check sequence number */
776	if (prrs->seq_num != rx_page_desc->rx_nxseq) {
777	DBG("atl1e %s: RX sequence number error (%d != %d)\n",
778	netdev->name, prrs->seq_num,
779	rx_page_desc->rx_nxseq);
780	rx_page_desc->rx_nxseq++;
781	goto fatal_err;
782	}
783
784	rx_page_desc->rx_nxseq++;
785
786	/* error packet */
787	if (prrs->pkt_flag & RRS_IS_ERR_FRAME) {
788	if (prrs->err_flag & (RRS_ERR_BAD_CRC \|
789	RRS_ERR_DRIBBLE \| RRS_ERR_CODE \|
790	RRS_ERR_TRUNC)) {
791	/* hardware error, discard this
792	packet */
793	netdev_rx_err(netdev, NULL, EIO);
794	goto skip_pkt;
795	}
796	}
797
798	packet_size = ((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
799	RRS_PKT_SIZE_MASK) - ETH_FCS_LEN;
800	iob = alloc_iob(packet_size + NET_IP_ALIGN);
801	if (iob == NULL) {
802	DBG("atl1e %s: dropping packet under memory pressure\n",
803	netdev->name);
804	goto skip_pkt;
805	}
806	iob_reserve(iob, NET_IP_ALIGN);
807	memcpy(iob->data, (u8 *)(prrs + 1), packet_size);
808	iob_put(iob, packet_size);
809
810	netdev_rx(netdev, iob);
811
812	skip_pkt:
813	/* skip current packet whether it's ok or not. */
814	rx_page->read_offset +=
815	(((u32)((prrs->word1 >> RRS_PKT_SIZE_SHIFT) &
816	RRS_PKT_SIZE_MASK) +
817	sizeof(struct atl1e_recv_ret_status) + 31) &
818	0xFFFFFFE0);
819
820	if (rx_page->read_offset >= rx_ring->page_size) {
821	/* mark this page clean */
822	u16 reg_addr;
823	u8 rx_using;
824
825	rx_page->read_offset =
826	*(rx_page->write_offset_addr) = 0;
827	rx_using = rx_page_desc->rx_using;
828	reg_addr =
829	atl1e_rx_page_vld_regs[rx_using];
830	AT_WRITE_REGB(&adapter->hw, reg_addr, 1);
831	rx_page_desc->rx_using ^= 1;
832	rx_page = atl1e_get_rx_page(adapter);
833	}
834	write_offset = *(rx_page->write_offset_addr);
835	} while (rx_page->read_offset < write_offset);
836
837	return;
838
839	fatal_err:
840	if (!netdev_link_ok(adapter->netdev))
841	atl1e_reset(adapter);
842	}
843
844	/*
845	* atl1e_poll - poll for completed transmissions and received packets
846	* @netdev: network device
847	*/
848	static void atl1e_poll(struct net_device *netdev)
849	{
850	struct atl1e_adapter *adapter = netdev_priv(netdev);
851	struct atl1e_hw *hw = &adapter->hw;
852	int max_ints = 64;
853	u32 status;
854
855	do {
856	status = AT_READ_REG(hw, REG_ISR);
857	if ((status & IMR_NORMAL_MASK) == 0)
858	break;
859
860	/* link event */
861	if (status & ISR_GPHY)
862	atl1e_clear_phy_int(adapter);
863	/* Ack ISR */
864	AT_WRITE_REG(hw, REG_ISR, status \| ISR_DIS_INT);
865
866	/* check if PCIE PHY Link down */
867	if (status & ISR_PHY_LINKDOWN) {
868	DBG("atl1e: PCI-E PHY link down: %x\n", status);
869	if (netdev_link_ok(adapter->netdev)) {
870	/* reset MAC */
871	atl1e_irq_reset(adapter);
872	atl1e_reset(adapter);
873	break;
874	}
875	}
876
877	/* check if DMA read/write error */
878	if (status & (ISR_DMAR_TO_RST \| ISR_DMAW_TO_RST)) {
879	DBG("atl1e: PCI-E DMA RW error: %x\n", status);
880	atl1e_irq_reset(adapter);
881	atl1e_reset(adapter);
882	break;
883	}
884
885	/* link event */
886	if (status & (ISR_GPHY \| ISR_MANUAL)) {
887	atl1e_check_link(adapter);
888	break;
889	}
890
891	/* transmit event */
892	if (status & ISR_TX_EVENT)
893	atl1e_clean_tx_irq(adapter);
894
895	if (status & ISR_RX_EVENT)
896	atl1e_clean_rx_irq(adapter);
897	} while (--max_ints > 0);
898
899	/* re-enable Interrupt*/
900	AT_WRITE_REG(&adapter->hw, REG_ISR, 0);
901
902	return;
903	}
904
905	static inline u16 atl1e_tpd_avail(struct atl1e_adapter *adapter)
906	{
907	struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
908	u16 next_to_use = 0;
909	u16 next_to_clean = 0;
910
911	next_to_clean = tx_ring->next_to_clean;
912	next_to_use = tx_ring->next_to_use;
913
914	return (u16)(next_to_clean > next_to_use) ?
915	(next_to_clean - next_to_use - 1) :
916	(tx_ring->count + next_to_clean - next_to_use - 1);
917	}
918
919	/*
920	* get next usable tpd
921	* Note: should call atl1e_tdp_avail to make sure
922	* there is enough tpd to use
923	*/
924	static struct atl1e_tpd_desc atl1e_get_tpd(struct atl1e_adapter adapter)
925	{
926	struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
927	u16 next_to_use = 0;
928
929	next_to_use = tx_ring->next_to_use;
930	if (++tx_ring->next_to_use == tx_ring->count)
931	tx_ring->next_to_use = 0;
932
933	memset(&tx_ring->desc[next_to_use], 0, sizeof(struct atl1e_tpd_desc));
934	return (struct atl1e_tpd_desc *)&tx_ring->desc[next_to_use];
935	}
936
937	static struct atl1e_tx_buffer *
938	atl1e_get_tx_buffer(struct atl1e_adapter adapter, struct atl1e_tpd_desc tpd)
939	{
940	struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
941
942	return &tx_ring->tx_buffer[tpd - tx_ring->desc];
943	}
944
945	static void atl1e_tx_map(struct atl1e_adapter *adapter,
946	struct io_buffer iob, struct atl1e_tpd_desc tpd)
947	{
948	struct atl1e_tx_buffer *tx_buffer = NULL;
949	u16 buf_len = iob_len(iob);
950
951	tx_buffer = atl1e_get_tx_buffer(adapter, tpd);
952	tx_buffer->iob = iob;
953	tx_buffer->length = buf_len;
954	tx_buffer->dma = virt_to_bus(iob->data);
955	tpd->buffer_addr = cpu_to_le64(tx_buffer->dma);
956	tpd->word2 = ((tpd->word2 & ~TPD_BUFLEN_MASK) \|
957	((cpu_to_le32(buf_len) & TPD_BUFLEN_MASK) <<
958	TPD_BUFLEN_SHIFT));
959	tpd->word3 \|= 1 << TPD_EOP_SHIFT;
960	}
961
962	static void atl1e_tx_queue(struct atl1e_adapter *adapter, u16 count __unused,
963	struct atl1e_tpd_desc *tpd __unused)
964	{
965	struct atl1e_tx_ring *tx_ring = &adapter->tx_ring;
966	wmb();
967	AT_WRITE_REG(&adapter->hw, REG_MB_TPD_PROD_IDX, tx_ring->next_to_use);
968	}
969
970	static int atl1e_xmit_frame(struct net_device netdev, struct io_buffer iob)
971	{
972	struct atl1e_adapter *adapter = netdev_priv(netdev);
973	u16 tpd_req = 1;
974	struct atl1e_tpd_desc *tpd;
975
976	if (!netdev_link_ok(netdev)) {
977	return -EINVAL;
978	}
979
980	if (atl1e_tpd_avail(adapter) < tpd_req) {
981	return -EBUSY;
982	}
983
984	tpd = atl1e_get_tpd(adapter);
985
986	atl1e_tx_map(adapter, iob, tpd);
987	atl1e_tx_queue(adapter, tpd_req, tpd);
988
989	return 0;
990	}
991
992	int atl1e_up(struct atl1e_adapter *adapter)
993	{
994	struct net_device *netdev = adapter->netdev;
995	int err = 0;
996	u32 val;
997
998	/* hardware has been reset, we need to reload some things */
999	err = atl1e_init_hw(&adapter->hw);
1000	if (err) {
1001	return -EIO;
1002	}
1003	atl1e_init_ring_ptrs(adapter);
1004
1005	memcpy(adapter->hw.mac_addr, netdev->ll_addr, ETH_ALEN);
1006
1007	if (atl1e_configure(adapter) != 0) {
1008	return -EIO;
1009	}
1010
1011	atl1e_irq_disable(adapter);
1012
1013	val = AT_READ_REG(&adapter->hw, REG_MASTER_CTRL);
1014	AT_WRITE_REG(&adapter->hw, REG_MASTER_CTRL,
1015	val \| MASTER_CTRL_MANUAL_INT);
1016
1017	return err;
1018	}
1019
1020	void atl1e_irq(struct net_device *netdev, int enable)
1021	{
1022	struct atl1e_adapter *adapter = netdev_priv(netdev);
1023
1024	if (enable)
1025	atl1e_irq_enable(adapter);
1026	else
1027	atl1e_irq_disable(adapter);
1028	}
1029
1030	void atl1e_down(struct atl1e_adapter *adapter)
1031	{
1032	struct net_device *netdev = adapter->netdev;
1033
1034	/* reset MAC to disable all RX/TX */
1035	atl1e_reset_hw(&adapter->hw);
1036	mdelay(1);
1037
1038	netdev_link_down(netdev);
1039	adapter->link_speed = SPEED_0;
1040	adapter->link_duplex = -1;
1041
1042	atl1e_clean_tx_ring(adapter);
1043	atl1e_clean_rx_ring(adapter);
1044	}
1045
1046	/*
1047	* atl1e_open - Called when a network interface is made active
1048	* @netdev: network interface device structure
1049	*
1050	* Returns 0 on success, negative value on failure
1051	*
1052	* The open entry point is called when a network interface is made
1053	* active by the system (IFF_UP). At this point all resources needed
1054	* for transmit and receive operations are allocated, the interrupt
1055	* handler is registered with the OS, the watchdog timer is started,
1056	* and the stack is notified that the interface is ready.
1057	*/
1058	static int atl1e_open(struct net_device *netdev)
1059	{
1060	struct atl1e_adapter *adapter = netdev_priv(netdev);
1061	int err;
1062
1063	/* allocate rx/tx dma buffer & descriptors */
1064	atl1e_init_ring_resources(adapter);
1065	err = atl1e_setup_ring_resources(adapter);
1066	if (err)
1067	return err;
1068
1069	err = atl1e_up(adapter);
1070	if (err)
1071	goto err_up;
1072
1073	return 0;
1074
1075	err_up:
1076	atl1e_free_ring_resources(adapter);
1077	atl1e_reset_hw(&adapter->hw);
1078
1079	return err;
1080	}
1081
1082	/*
1083	* atl1e_close - Disables a network interface
1084	* @netdev: network interface device structure
1085	*
1086	* Returns 0, this is not allowed to fail
1087	*
1088	* The close entry point is called when an interface is de-activated
1089	* by the OS. The hardware is still under the drivers control, but
1090	* needs to be disabled. A global MAC reset is issued to stop the
1091	* hardware, and all transmit and receive resources are freed.
1092	*/
1093	static void atl1e_close(struct net_device *netdev)
1094	{
1095	struct atl1e_adapter *adapter = netdev_priv(netdev);
1096
1097	atl1e_down(adapter);
1098	atl1e_free_ring_resources(adapter);
1099	}
1100
1101	static struct net_device_operations atl1e_netdev_ops = {
1102	.open = atl1e_open,
1103	.close = atl1e_close,
1104	.transmit = atl1e_xmit_frame,
1105	.poll = atl1e_poll,
1106	.irq = atl1e_irq,
1107	};
1108
1109	static void atl1e_init_netdev(struct net_device netdev, struct pci_device pdev)
1110	{
1111	netdev_init(netdev, &atl1e_netdev_ops);
1112
1113	netdev->dev = &pdev->dev;
1114	pci_set_drvdata(pdev, netdev);
1115	}
1116
1117	/*
1118	* atl1e_probe - Device Initialization Routine
1119	* @pdev: PCI device information struct
1120	* @ent: entry in atl1e_pci_tbl
1121	*
1122	* Returns 0 on success, negative on failure
1123	*
1124	* atl1e_probe initializes an adapter identified by a pci_device structure.
1125	* The OS initialization, configuring of the adapter private structure,
1126	* and a hardware reset occur.
1127	*/
1128	static int atl1e_probe(struct pci_device *pdev,
1129	const struct pci_device_id *ent __unused)
1130	{
1131	struct net_device *netdev;
1132	struct atl1e_adapter *adapter = NULL;
1133	static int cards_found;
1134
1135	int err = 0;
1136
1137	adjust_pci_device(pdev);
1138
1139	netdev = alloc_etherdev(sizeof(struct atl1e_adapter));
1140	if (netdev == NULL) {
1141	err = -ENOMEM;
1142	DBG("atl1e: out of memory allocating net_device\n");
1143	goto err;
1144	}
1145
1146	atl1e_init_netdev(netdev, pdev);
1147
1148	adapter = netdev_priv(netdev);
1149	adapter->bd_number = cards_found;
1150	adapter->netdev = netdev;
1151	adapter->pdev = pdev;
1152	adapter->hw.adapter = adapter;
1153	if (!pdev->membase) {
1154	err = -EIO;
1155	DBG("atl1e: cannot map device registers\n");
1156	goto err_free_netdev;
1157	}
1158	adapter->hw.hw_addr = bus_to_virt(pdev->membase);
1159
1160	/* init mii data */
1161	adapter->mii.dev = netdev;
1162	adapter->mii.mdio_read = atl1e_mdio_read;
1163	adapter->mii.mdio_write = atl1e_mdio_write;
1164	adapter->mii.phy_id_mask = 0x1f;
1165	adapter->mii.reg_num_mask = MDIO_REG_ADDR_MASK;
1166
1167	/* get user settings */
1168	adapter->tx_ring.count = TX_DESC_COUNT;
1169	adapter->rx_ring.page_size = RX_MEM_SIZE;
1170
1171	atl1e_setup_pcicmd(pdev);
1172
1173	/* setup the private structure */
1174	err = atl1e_sw_init(adapter);
1175	if (err) {
1176	DBG("atl1e: private data init failed\n");
1177	goto err_free_netdev;
1178	}
1179
1180	/* Init GPHY as early as possible due to power saving issue */
1181	atl1e_phy_init(&adapter->hw);
1182
1183	/* reset the controller to
1184	* put the device in a known good starting state */
1185	err = atl1e_reset_hw(&adapter->hw);
1186	if (err) {
1187	err = -EIO;
1188	goto err_free_netdev;
1189	}
1190
1191	/* This may have been run by a zero-wait timer around
1192	now... unclear. */
1193	atl1e_restart_autoneg(&adapter->hw);
1194
1195	if (atl1e_read_mac_addr(&adapter->hw) != 0) {
1196	DBG("atl1e: cannot read MAC address from EEPROM\n");
1197	err = -EIO;
1198	goto err_free_netdev;
1199	}
1200
1201	memcpy(netdev->hw_addr, adapter->hw.perm_mac_addr, ETH_ALEN);
1202	memcpy(netdev->ll_addr, adapter->hw.mac_addr, ETH_ALEN);
1203	DBG("atl1e: Attansic L1E Ethernet controller on %s, "
1204	"%02x:%02x:%02x:%02x:%02x:%02x\n", adapter->netdev->name,
1205	adapter->hw.mac_addr[0], adapter->hw.mac_addr[1],
1206	adapter->hw.mac_addr[2], adapter->hw.mac_addr[3],
1207	adapter->hw.mac_addr[4], adapter->hw.mac_addr[5]);
1208
1209	err = register_netdev(netdev);
1210	if (err) {
1211	DBG("atl1e: cannot register network device\n");
1212	goto err_free_netdev;
1213	}
1214
1215	netdev_link_down(netdev);
1216
1217	cards_found++;
1218	return 0;
1219
1220	err_free_netdev:
1221	netdev_nullify(netdev);
1222	netdev_put(netdev);
1223	err:
1224	return err;
1225	}
1226
1227	/*
1228	* atl1e_remove - Device Removal Routine
1229	* @pdev: PCI device information struct
1230	*
1231	* atl1e_remove is called by the PCI subsystem to alert the driver
1232	* that it should release a PCI device. The could be caused by a
1233	* Hot-Plug event, or because the driver is going to be removed from
1234	* memory.
1235	*/
1236	static void atl1e_remove(struct pci_device *pdev)
1237	{
1238	struct net_device *netdev = pci_get_drvdata(pdev);
1239	struct atl1e_adapter *adapter = netdev_priv(netdev);
1240
1241	unregister_netdev(netdev);
1242	atl1e_free_ring_resources(adapter);
1243	atl1e_force_ps(&adapter->hw);
1244	netdev_nullify(netdev);
1245	netdev_put(netdev);
1246	}
1247
1248	struct pci_driver atl1e_driver __pci_driver = {
1249	.ids = atl1e_pci_tbl,
1250	.id_count = (sizeof(atl1e_pci_tbl) / sizeof(atl1e_pci_tbl[0])),
1251	.probe = atl1e_probe,
1252	.remove = atl1e_remove,
1253	};
1254
1255	/******** Hardware-level functions: ********/
1256
1257	/*
1258	* check_eeprom_exist
1259	* return 0 if eeprom exist
1260	*/
1261	int atl1e_check_eeprom_exist(struct atl1e_hw *hw)
1262	{
1263	u32 value;
1264
1265	value = AT_READ_REG(hw, REG_SPI_FLASH_CTRL);
1266	if (value & SPI_FLASH_CTRL_EN_VPD) {
1267	value &= ~SPI_FLASH_CTRL_EN_VPD;
1268	AT_WRITE_REG(hw, REG_SPI_FLASH_CTRL, value);
1269	}
1270	value = AT_READ_REGW(hw, REG_PCIE_CAP_LIST);
1271	return ((value & 0xFF00) == 0x6C00) ? 0 : 1;
1272	}
1273
1274	void atl1e_hw_set_mac_addr(struct atl1e_hw *hw)
1275	{
1276	u32 value;
1277	/*
1278	* 00-0B-6A-F6-00-DC
1279	* 0: 6AF600DC 1: 000B
1280	* low dword
1281	*/
1282	value = (((u32)hw->mac_addr[2]) << 24) \|
1283	(((u32)hw->mac_addr[3]) << 16) \|
1284	(((u32)hw->mac_addr[4]) << 8) \|
1285	(((u32)hw->mac_addr[5])) ;
1286	AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value);
1287	/* hight dword */
1288	value = (((u32)hw->mac_addr[0]) << 8) \|
1289	(((u32)hw->mac_addr[1])) ;
1290	AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value);
1291	}
1292
1293	/*
1294	* atl1e_get_permanent_address
1295	* return 0 if get valid mac address,
1296	*/
1297	static int atl1e_get_permanent_address(struct atl1e_hw *hw)
1298	{
1299	union {
1300	u32 dword[2];
1301	u8 byte[8];
1302	} hw_addr;
1303	u32 i;
1304	u32 twsi_ctrl_data;
1305	u8 eth_addr[ETH_ALEN];
1306
1307	if (!atl1e_check_eeprom_exist(hw)) {
1308	/* eeprom exist */
1309	twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
1310	twsi_ctrl_data \|= TWSI_CTRL_SW_LDSTART;
1311	AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data);
1312	for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) {
1313	mdelay(10);
1314	twsi_ctrl_data = AT_READ_REG(hw, REG_TWSI_CTRL);
1315	if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0)
1316	break;
1317	}
1318	if (i >= AT_TWSI_EEPROM_TIMEOUT)
1319	return AT_ERR_TIMEOUT;
1320	}
1321
1322	/* maybe MAC-address is from BIOS */
1323	hw_addr.dword[0] = AT_READ_REG(hw, REG_MAC_STA_ADDR);
1324	hw_addr.dword[1] = AT_READ_REG(hw, REG_MAC_STA_ADDR + 4);
1325	for (i = 0; i < ETH_ALEN; i++) {
1326	eth_addr[ETH_ALEN - i - 1] = hw_addr.byte[i];
1327	}
1328
1329	memcpy(hw->perm_mac_addr, eth_addr, ETH_ALEN);
1330	return 0;
1331	}
1332
1333	void atl1e_force_ps(struct atl1e_hw *hw)
1334	{
1335	AT_WRITE_REGW(hw, REG_GPHY_CTRL,
1336	GPHY_CTRL_PW_WOL_DIS \| GPHY_CTRL_EXT_RESET);
1337	}
1338
1339	/*
1340	* Reads the adapter's MAC address from the EEPROM
1341	*
1342	* hw - Struct containing variables accessed by shared code
1343	*/
1344	int atl1e_read_mac_addr(struct atl1e_hw *hw)
1345	{
1346	int err = 0;
1347
1348	err = atl1e_get_permanent_address(hw);
1349	if (err)
1350	return AT_ERR_EEPROM;
1351	memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr));
1352	return 0;
1353	}
1354
1355	/*
1356	* Reads the value from a PHY register
1357	* hw - Struct containing variables accessed by shared code
1358	* reg_addr - address of the PHY register to read
1359	*/
1360	int atl1e_read_phy_reg(struct atl1e_hw hw, u16 reg_addr, u16 phy_data)
1361	{
1362	u32 val;
1363	int i;
1364
1365	val = ((u32)(reg_addr & MDIO_REG_ADDR_MASK)) << MDIO_REG_ADDR_SHIFT \|
1366	MDIO_START \| MDIO_SUP_PREAMBLE \| MDIO_RW \|
1367	MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
1368
1369	AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
1370
1371	wmb();
1372
1373	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1374	udelay(2);
1375	val = AT_READ_REG(hw, REG_MDIO_CTRL);
1376	if (!(val & (MDIO_START \| MDIO_BUSY)))
1377	break;
1378	wmb();
1379	}
1380	if (!(val & (MDIO_START \| MDIO_BUSY))) {
1381	*phy_data = (u16)val;
1382	return 0;
1383	}
1384
1385	return AT_ERR_PHY;
1386	}
1387
1388	/*
1389	* Writes a value to a PHY register
1390	* hw - Struct containing variables accessed by shared code
1391	* reg_addr - address of the PHY register to write
1392	* data - data to write to the PHY
1393	*/
1394	int atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data)
1395	{
1396	int i;
1397	u32 val;
1398
1399	val = ((u32)(phy_data & MDIO_DATA_MASK)) << MDIO_DATA_SHIFT \|
1400	(reg_addr&MDIO_REG_ADDR_MASK) << MDIO_REG_ADDR_SHIFT \|
1401	MDIO_SUP_PREAMBLE \|
1402	MDIO_START \|
1403	MDIO_CLK_25_4 << MDIO_CLK_SEL_SHIFT;
1404
1405	AT_WRITE_REG(hw, REG_MDIO_CTRL, val);
1406	wmb();
1407
1408	for (i = 0; i < MDIO_WAIT_TIMES; i++) {
1409	udelay(2);
1410	val = AT_READ_REG(hw, REG_MDIO_CTRL);
1411	if (!(val & (MDIO_START \| MDIO_BUSY)))
1412	break;
1413	wmb();
1414	}
1415
1416	if (!(val & (MDIO_START \| MDIO_BUSY)))
1417	return 0;
1418
1419	return AT_ERR_PHY;
1420	}
1421
1422	/*
1423	* atl1e_init_pcie - init PCIE module
1424	*/
1425	static void atl1e_init_pcie(struct atl1e_hw *hw)
1426	{
1427	u32 value;
1428	/* comment 2lines below to save more power when sususpend
1429	value = LTSSM_TEST_MODE_DEF;
1430	AT_WRITE_REG(hw, REG_LTSSM_TEST_MODE, value);
1431	*/
1432
1433	/* pcie flow control mode change */
1434	value = AT_READ_REG(hw, 0x1008);
1435	value \|= 0x8000;
1436	AT_WRITE_REG(hw, 0x1008, value);
1437	}
1438	/*
1439	* Configures PHY autoneg and flow control advertisement settings
1440	*
1441	* hw - Struct containing variables accessed by shared code
1442	*/
1443	static int atl1e_phy_setup_autoneg_adv(struct atl1e_hw *hw)
1444	{
1445	s32 ret_val;
1446	u16 mii_autoneg_adv_reg;
1447	u16 mii_1000t_ctrl_reg;
1448
1449	if (0 != hw->mii_autoneg_adv_reg)
1450	return 0;
1451	/* Read the MII Auto-Neg Advertisement Register (Address 4/9). */
1452	mii_autoneg_adv_reg = MII_AR_DEFAULT_CAP_MASK;
1453	mii_1000t_ctrl_reg = MII_AT001_CR_1000T_DEFAULT_CAP_MASK;
1454
1455	/*
1456	* First we clear all the 10/100 mb speed bits in the Auto-Neg
1457	* Advertisement Register (Address 4) and the 1000 mb speed bits in
1458	* the 1000Base-T control Register (Address 9).
1459	*/
1460	mii_autoneg_adv_reg &= ~MII_AR_SPEED_MASK;
1461	mii_1000t_ctrl_reg &= ~MII_AT001_CR_1000T_SPEED_MASK;
1462
1463	/* Assume auto-detect media type */
1464	mii_autoneg_adv_reg \|= (MII_AR_10T_HD_CAPS \|
1465	MII_AR_10T_FD_CAPS \|
1466	MII_AR_100TX_HD_CAPS \|
1467	MII_AR_100TX_FD_CAPS);
1468	if (hw->nic_type == athr_l1e) {
1469	mii_1000t_ctrl_reg \|= MII_AT001_CR_1000T_FD_CAPS;
1470	}
1471
1472	/* flow control fixed to enable all */
1473	mii_autoneg_adv_reg \|= (MII_AR_ASM_DIR \| MII_AR_PAUSE);
1474
1475	hw->mii_autoneg_adv_reg = mii_autoneg_adv_reg;
1476	hw->mii_1000t_ctrl_reg = mii_1000t_ctrl_reg;
1477
1478	ret_val = atl1e_write_phy_reg(hw, MII_ADVERTISE, mii_autoneg_adv_reg);
1479	if (ret_val)
1480	return ret_val;
1481
1482	if (hw->nic_type == athr_l1e \|\| hw->nic_type == athr_l2e_revA) {
1483	ret_val = atl1e_write_phy_reg(hw, MII_AT001_CR,
1484	mii_1000t_ctrl_reg);
1485	if (ret_val)
1486	return ret_val;
1487	}
1488
1489	return 0;
1490	}
1491
1492
1493	/*
1494	* Resets the PHY and make all config validate
1495	*
1496	* hw - Struct containing variables accessed by shared code
1497	*
1498	* Sets bit 15 and 12 of the MII control regiser (for F001 bug)
1499	*/
1500	int atl1e_phy_commit(struct atl1e_hw *hw)
1501	{
1502	int ret_val;
1503	u16 phy_data;
1504
1505	phy_data = MII_CR_RESET \| MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG;
1506
1507	ret_val = atl1e_write_phy_reg(hw, MII_BMCR, phy_data);
1508	if (ret_val) {
1509	u32 val;
1510	int i;
1511	/**************************************
1512	* pcie serdes link may be down !
1513	**************************************/
1514	for (i = 0; i < 25; i++) {
1515	mdelay(1);
1516	val = AT_READ_REG(hw, REG_MDIO_CTRL);
1517	if (!(val & (MDIO_START \| MDIO_BUSY)))
1518	break;
1519	}
1520
1521	if (0 != (val & (MDIO_START \| MDIO_BUSY))) {
1522	DBG("atl1e: PCI-E link down for at least 25ms\n");
1523	return ret_val;
1524	}
1525
1526	DBG("atl1e: PCI-E link up after %d ms\n", i);
1527	}
1528	return 0;
1529	}
1530
1531	int atl1e_phy_init(struct atl1e_hw *hw)
1532	{
1533	s32 ret_val;
1534	u16 phy_val;
1535
1536	if (hw->phy_configured) {
1537	if (hw->re_autoneg) {
1538	hw->re_autoneg = 0;
1539	return atl1e_restart_autoneg(hw);
1540	}
1541	return 0;
1542	}
1543
1544	/* RESET GPHY Core */
1545	AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT);
1546	mdelay(2);
1547	AT_WRITE_REGW(hw, REG_GPHY_CTRL, GPHY_CTRL_DEFAULT \|
1548	GPHY_CTRL_EXT_RESET);
1549	mdelay(2);
1550
1551	/* patches */
1552	/* p1. eable hibernation mode */
1553	ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0xB);
1554	if (ret_val)
1555	return ret_val;
1556	ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0xBC00);
1557	if (ret_val)
1558	return ret_val;
1559	/* p2. set Class A/B for all modes */
1560	ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0);
1561	if (ret_val)
1562	return ret_val;
1563	phy_val = 0x02ef;
1564	/* remove Class AB */
1565	/* phy_val = hw->emi_ca ? 0x02ef : 0x02df; */
1566	ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, phy_val);
1567	if (ret_val)
1568	return ret_val;
1569	/* p3. 10B ??? */
1570	ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x12);
1571	if (ret_val)
1572	return ret_val;
1573	ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x4C04);
1574	if (ret_val)
1575	return ret_val;
1576	/* p4. 1000T power */
1577	ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x4);
1578	if (ret_val)
1579	return ret_val;
1580	ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x8BBB);
1581	if (ret_val)
1582	return ret_val;
1583
1584	ret_val = atl1e_write_phy_reg(hw, MII_DBG_ADDR, 0x5);
1585	if (ret_val)
1586	return ret_val;
1587	ret_val = atl1e_write_phy_reg(hw, MII_DBG_DATA, 0x2C46);
1588	if (ret_val)
1589	return ret_val;
1590
1591	mdelay(1);
1592
1593	/Enable PHY LinkChange Interrupt /
1594	ret_val = atl1e_write_phy_reg(hw, MII_INT_CTRL, 0xC00);
1595	if (ret_val) {
1596	DBG("atl1e: Error enable PHY linkChange Interrupt\n");
1597	return ret_val;
1598	}
1599	/* setup AutoNeg parameters */
1600	ret_val = atl1e_phy_setup_autoneg_adv(hw);
1601	if (ret_val) {
1602	DBG("atl1e: Error Setting up Auto-Negotiation\n");
1603	return ret_val;
1604	}
1605	/* SW.Reset & En-Auto-Neg to restart Auto-Neg*/
1606	DBG("atl1e: Restarting Auto-Neg");
1607	ret_val = atl1e_phy_commit(hw);
1608	if (ret_val) {
1609	DBG("atl1e: Error Resetting the phy");
1610	return ret_val;
1611	}
1612
1613	hw->phy_configured = 1;
1614
1615	return 0;
1616	}
1617
1618	/*
1619	* Reset the transmit and receive units; mask and clear all interrupts.
1620	* hw - Struct containing variables accessed by shared code
1621	* return : 0 or idle status (if error)
1622	*/
1623	int atl1e_reset_hw(struct atl1e_hw *hw)
1624	{
1625	struct atl1e_adapter *adapter = hw->adapter;
1626	struct pci_device *pdev = adapter->pdev;
1627	int timeout = 0;
1628	u32 idle_status_data = 0;
1629	u16 pci_cfg_cmd_word = 0;
1630
1631	/* Workaround for PCI problem when BIOS sets MMRBC incorrectly. */
1632	pci_read_config_word(pdev, PCI_COMMAND, &pci_cfg_cmd_word);
1633	if ((pci_cfg_cmd_word & (PCI_COMMAND_IO \| PCI_COMMAND_MEM \|
1634	PCI_COMMAND_MASTER))
1635	!= (PCI_COMMAND_IO \| PCI_COMMAND_MEM \|
1636	PCI_COMMAND_MASTER)) {
1637	pci_cfg_cmd_word \|= (PCI_COMMAND_IO \| PCI_COMMAND_MEM \|
1638	PCI_COMMAND_MASTER);
1639	pci_write_config_word(pdev, PCI_COMMAND, pci_cfg_cmd_word);
1640	}
1641
1642	/*
1643	* Issue Soft Reset to the MAC. This will reset the chip's
1644	* transmit, receive, DMA. It will not effect
1645	* the current PCI configuration. The global reset bit is self-
1646	* clearing, and should clear within a microsecond.
1647	*/
1648	AT_WRITE_REG(hw, REG_MASTER_CTRL,
1649	MASTER_CTRL_LED_MODE \| MASTER_CTRL_SOFT_RST);
1650	wmb();
1651	mdelay(1);
1652
1653	/* Wait at least 10ms for All module to be Idle */
1654	for (timeout = 0; timeout < AT_HW_MAX_IDLE_DELAY; timeout++) {
1655	idle_status_data = AT_READ_REG(hw, REG_IDLE_STATUS);
1656	if (idle_status_data == 0)
1657	break;
1658	mdelay(1);
1659	}
1660
1661	if (timeout >= AT_HW_MAX_IDLE_DELAY) {
1662	DBG("atl1e: MAC reset timeout\n");
1663	return AT_ERR_TIMEOUT;
1664	}
1665
1666	return 0;
1667	}
1668
1669
1670	/*
1671	* Performs basic configuration of the adapter.
1672	*
1673	* hw - Struct containing variables accessed by shared code
1674	* Assumes that the controller has previously been reset and is in a
1675	* post-reset uninitialized state. Initializes multicast table,
1676	* and Calls routines to setup link
1677	* Leaves the transmit and receive units disabled and uninitialized.
1678	*/
1679	int atl1e_init_hw(struct atl1e_hw *hw)
1680	{
1681	s32 ret_val = 0;
1682
1683	atl1e_init_pcie(hw);
1684
1685	/* Zero out the Multicast HASH table */
1686	/* clear the old settings from the multicast hash table */
1687	AT_WRITE_REG(hw, REG_RX_HASH_TABLE, 0);
1688	AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, 1, 0);
1689
1690	ret_val = atl1e_phy_init(hw);
1691
1692	return ret_val;
1693	}
1694
1695	/*
1696	* Detects the current speed and duplex settings of the hardware.
1697	*
1698	* hw - Struct containing variables accessed by shared code
1699	* speed - Speed of the connection
1700	* duplex - Duplex setting of the connection
1701	*/
1702	int atl1e_get_speed_and_duplex(struct atl1e_hw hw, u16 speed, u16 *duplex)
1703	{
1704	int err;
1705	u16 phy_data;
1706
1707	/* Read PHY Specific Status Register (17) */
1708	err = atl1e_read_phy_reg(hw, MII_AT001_PSSR, &phy_data);
1709	if (err)
1710	return err;
1711
1712	if (!(phy_data & MII_AT001_PSSR_SPD_DPLX_RESOLVED))
1713	return AT_ERR_PHY_RES;
1714
1715	switch (phy_data & MII_AT001_PSSR_SPEED) {
1716	case MII_AT001_PSSR_1000MBS:
1717	*speed = SPEED_1000;
1718	break;
1719	case MII_AT001_PSSR_100MBS:
1720	*speed = SPEED_100;
1721	break;
1722	case MII_AT001_PSSR_10MBS:
1723	*speed = SPEED_10;
1724	break;
1725	default:
1726	return AT_ERR_PHY_SPEED;
1727	break;
1728	}
1729
1730	if (phy_data & MII_AT001_PSSR_DPLX)
1731	*duplex = FULL_DUPLEX;
1732	else
1733	*duplex = HALF_DUPLEX;
1734
1735	return 0;
1736	}
1737
1738	int atl1e_restart_autoneg(struct atl1e_hw *hw)
1739	{
1740	int err = 0;
1741
1742	err = atl1e_write_phy_reg(hw, MII_ADVERTISE, hw->mii_autoneg_adv_reg);
1743	if (err)
1744	return err;
1745
1746	if (hw->nic_type == athr_l1e \|\| hw->nic_type == athr_l2e_revA) {
1747	err = atl1e_write_phy_reg(hw, MII_AT001_CR,
1748	hw->mii_1000t_ctrl_reg);
1749	if (err)
1750	return err;
1751	}
1752
1753	err = atl1e_write_phy_reg(hw, MII_BMCR,
1754	MII_CR_RESET \| MII_CR_AUTO_NEG_EN \|
1755	MII_CR_RESTART_AUTO_NEG);
1756	return err;
1757	}
1758

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