Context Navigation

source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/atl1e.h

Last change on this file was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago
bootstuff
Property mode set to `100644`
File size: 43.1 KB

Line
1	/*
2	* Copyright(c) 2007 Atheros Corporation. All rights reserved.
3	* Copyright(c) 2007 xiong huang <xiong.huang@atheros.com>
4	*
5	* Derived from Intel e1000 driver
6	* Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved.
7	*
8	* Modified for gPXE, October 2009 by Joshua Oreman <oremanj@rwcr.net>
9	*
10	* This program is free software; you can redistribute it and/or modify it
11	* under the terms of the GNU General Public License as published by the Free
12	* Software Foundation; either version 2 of the License, or (at your option)
13	* any later version.
14	*
15	* This program is distributed in the hope that it will be useful, but WITHOUT
16	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
17	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
18	* more details.
19	*
20	* You should have received a copy of the GNU General Public License along with
21	* this program; if not, write to the Free Software Foundation, Inc., 59
22	* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23	*/
24
25	#ifndef _ATL1E_H_
26	#define _ATL1E_H_
27
28	#include <mii.h>
29	#include <stdlib.h>
30	#include <string.h>
31	#include <unistd.h>
32	#include <byteswap.h>
33	#include <errno.h>
34	#include <gpxe/malloc.h>
35	#include <gpxe/pci.h>
36	#include <gpxe/pci_io.h>
37	#include <gpxe/iobuf.h>
38	#include <gpxe/netdevice.h>
39	#include <gpxe/ethernet.h>
40	#include <gpxe/if_ether.h>
41	#include <gpxe/io.h>
42
43	#define ETH_FCS_LEN 4
44	#define VLAN_HLEN 4
45	#define NET_IP_ALIGN 2
46
47	#define SPEED_0 0xffff
48	#define SPEED_10 10
49	#define SPEED_100 100
50	#define SPEED_1000 1000
51	#define HALF_DUPLEX 1
52	#define FULL_DUPLEX 2
53
54	/* Error Codes */
55	#define AT_ERR_EEPROM 1
56	#define AT_ERR_PHY 2
57	#define AT_ERR_CONFIG 3
58	#define AT_ERR_PARAM 4
59	#define AT_ERR_MAC_TYPE 5
60	#define AT_ERR_PHY_TYPE 6
61	#define AT_ERR_PHY_SPEED 7
62	#define AT_ERR_PHY_RES 8
63	#define AT_ERR_TIMEOUT 9
64
65	#define AT_MAX_RECEIVE_QUEUE 4
66	#define AT_PAGE_NUM_PER_QUEUE 2
67
68	#define AT_TWSI_EEPROM_TIMEOUT 100
69	#define AT_HW_MAX_IDLE_DELAY 10
70
71	#define AT_REGS_LEN 75
72	#define AT_EEPROM_LEN 512
73
74	/* tpd word 2 */
75	#define TPD_BUFLEN_MASK 0x3FFF
76	#define TPD_BUFLEN_SHIFT 0
77
78	/* tpd word 3 bits 0:4 */
79	#define TPD_EOP_MASK 0x0001
80	#define TPD_EOP_SHIFT 0
81
82	struct atl1e_tpd_desc {
83	u64 buffer_addr;
84	u32 word2;
85	u32 word3;
86	};
87
88	#define MAX_TX_BUF_LEN 0x2000
89	#define MAX_TX_BUF_SHIFT 13
90
91	/* rrs word 1 bit 0:31 */
92	#define RRS_RX_CSUM_MASK 0xFFFF
93	#define RRS_RX_CSUM_SHIFT 0
94	#define RRS_PKT_SIZE_MASK 0x3FFF
95	#define RRS_PKT_SIZE_SHIFT 16
96	#define RRS_CPU_NUM_MASK 0x0003
97	#define RRS_CPU_NUM_SHIFT 30
98
99	#define RRS_IS_RSS_IPV4 0x0001
100	#define RRS_IS_RSS_IPV4_TCP 0x0002
101	#define RRS_IS_RSS_IPV6 0x0004
102	#define RRS_IS_RSS_IPV6_TCP 0x0008
103	#define RRS_IS_IPV6 0x0010
104	#define RRS_IS_IP_FRAG 0x0020
105	#define RRS_IS_IP_DF 0x0040
106	#define RRS_IS_802_3 0x0080
107	#define RRS_IS_VLAN_TAG 0x0100
108	#define RRS_IS_ERR_FRAME 0x0200
109	#define RRS_IS_IPV4 0x0400
110	#define RRS_IS_UDP 0x0800
111	#define RRS_IS_TCP 0x1000
112	#define RRS_IS_BCAST 0x2000
113	#define RRS_IS_MCAST 0x4000
114	#define RRS_IS_PAUSE 0x8000
115
116	#define RRS_ERR_BAD_CRC 0x0001
117	#define RRS_ERR_CODE 0x0002
118	#define RRS_ERR_DRIBBLE 0x0004
119	#define RRS_ERR_RUNT 0x0008
120	#define RRS_ERR_RX_OVERFLOW 0x0010
121	#define RRS_ERR_TRUNC 0x0020
122	#define RRS_ERR_IP_CSUM 0x0040
123	#define RRS_ERR_L4_CSUM 0x0080
124	#define RRS_ERR_LENGTH 0x0100
125	#define RRS_ERR_DES_ADDR 0x0200
126
127	struct atl1e_recv_ret_status {
128	u16 seq_num;
129	u16 hash_lo;
130	u32 word1;
131	u16 pkt_flag;
132	u16 err_flag;
133	u16 hash_hi;
134	u16 vtag;
135	};
136
137	enum atl1e_dma_req_block {
138	atl1e_dma_req_128 = 0,
139	atl1e_dma_req_256 = 1,
140	atl1e_dma_req_512 = 2,
141	atl1e_dma_req_1024 = 3,
142	atl1e_dma_req_2048 = 4,
143	atl1e_dma_req_4096 = 5
144	};
145
146	enum atl1e_nic_type {
147	athr_l1e = 0,
148	athr_l2e_revA = 1,
149	athr_l2e_revB = 2
150	};
151
152	struct atl1e_hw {
153	u8 hw_addr; / inner register address */
154	struct atl1e_adapter *adapter;
155	enum atl1e_nic_type nic_type;
156	u8 mac_addr[ETH_ALEN];
157	u8 perm_mac_addr[ETH_ALEN];
158
159	u16 mii_autoneg_adv_reg;
160	u16 mii_1000t_ctrl_reg;
161
162	enum atl1e_dma_req_block dmar_block;
163	enum atl1e_dma_req_block dmaw_block;
164
165	int phy_configured;
166	int re_autoneg;
167	int emi_ca;
168	};
169
170	/*
171	* wrapper around a pointer to a socket buffer,
172	* so a DMA handle can be stored along with the buffer
173	*/
174	struct atl1e_tx_buffer {
175	struct io_buffer *iob;
176	u16 length;
177	u32 dma;
178	};
179
180	struct atl1e_rx_page {
181	u32 dma; /* receive rage DMA address */
182	u8 addr; / receive rage virtual address */
183	u32 write_offset_dma; /* the DMA address which contain the
184	receive data offset in the page */
185	u32 write_offset_addr; / the virtaul address which contain
186	the receive data offset in the page */
187	u32 read_offset; /* the offset where we have read */
188	};
189
190	struct atl1e_rx_page_desc {
191	struct atl1e_rx_page rx_page[AT_PAGE_NUM_PER_QUEUE];
192	u8 rx_using;
193	u16 rx_nxseq;
194	};
195
196	/* transmit packet descriptor (tpd) ring */
197	struct atl1e_tx_ring {
198	struct atl1e_tpd_desc desc; / descriptor ring virtual address */
199	u32 dma; /* descriptor ring physical address */
200	u16 count; /* the count of transmit rings */
201	u16 next_to_use;
202	u16 next_to_clean;
203	struct atl1e_tx_buffer *tx_buffer;
204	u32 cmb_dma;
205	u32 *cmb;
206	};
207
208	/* receive packet descriptor ring */
209	struct atl1e_rx_ring {
210	void *desc;
211	u32 dma;
212	int size;
213	u32 page_size; /* bytes length of rxf page */
214	u32 real_page_size; /* real_page_size = page_size + jumbo + aliagn */
215	struct atl1e_rx_page_desc rx_page_desc;
216	};
217
218	/* board specific private data structure */
219	struct atl1e_adapter {
220	struct net_device *netdev;
221	struct pci_device *pdev;
222	struct mii_if_info mii; /* MII interface info */
223	struct atl1e_hw hw;
224
225	u16 link_speed;
226	u16 link_duplex;
227
228	/* All Descriptor memory */
229	u32 ring_dma;
230	void *ring_vir_addr;
231	u32 ring_size;
232
233	struct atl1e_tx_ring tx_ring;
234	struct atl1e_rx_ring rx_ring;
235
236	int bd_number; /* board number;*/
237	};
238
239	#define AT_WRITE_REG(a, reg, value) \
240	writel((value), ((a)->hw_addr + reg))
241
242	#define AT_WRITE_FLUSH(a) \
243	readl((a)->hw_addr)
244
245	#define AT_READ_REG(a, reg) \
246	readl((a)->hw_addr + reg)
247
248	#define AT_WRITE_REGB(a, reg, value) \
249	writeb((value), ((a)->hw_addr + reg))
250
251	#define AT_READ_REGB(a, reg) \
252	readb((a)->hw_addr + reg)
253
254	#define AT_WRITE_REGW(a, reg, value) \
255	writew((value), ((a)->hw_addr + reg))
256
257	#define AT_READ_REGW(a, reg) \
258	readw((a)->hw_addr + reg)
259
260	#define AT_WRITE_REG_ARRAY(a, reg, offset, value) \
261	writel((value), (((a)->hw_addr + reg) + ((offset) << 2)))
262
263	#define AT_READ_REG_ARRAY(a, reg, offset) \
264	readl(((a)->hw_addr + reg) + ((offset) << 2))
265
266	extern int atl1e_up(struct atl1e_adapter *adapter);
267	extern void atl1e_down(struct atl1e_adapter *adapter);
268	extern s32 atl1e_reset_hw(struct atl1e_hw *hw);
269
270	/******** Hardware-level functionality: ********/
271
272	/* function prototype */
273	s32 atl1e_reset_hw(struct atl1e_hw *hw);
274	s32 atl1e_read_mac_addr(struct atl1e_hw *hw);
275	s32 atl1e_init_hw(struct atl1e_hw *hw);
276	s32 atl1e_phy_commit(struct atl1e_hw *hw);
277	s32 atl1e_get_speed_and_duplex(struct atl1e_hw hw, u16 speed, u16 *duplex);
278	u32 atl1e_auto_get_fc(struct atl1e_adapter *adapter, u16 duplex);
279	s32 atl1e_read_phy_reg(struct atl1e_hw hw, u16 reg_addr, u16 phy_data);
280	s32 atl1e_write_phy_reg(struct atl1e_hw *hw, u32 reg_addr, u16 phy_data);
281	s32 atl1e_validate_mdi_setting(struct atl1e_hw *hw);
282	void atl1e_hw_set_mac_addr(struct atl1e_hw *hw);
283	s32 atl1e_phy_enter_power_saving(struct atl1e_hw *hw);
284	s32 atl1e_phy_leave_power_saving(struct atl1e_hw *hw);
285	s32 atl1e_phy_init(struct atl1e_hw *hw);
286	int atl1e_check_eeprom_exist(struct atl1e_hw *hw);
287	void atl1e_force_ps(struct atl1e_hw *hw);
288	s32 atl1e_restart_autoneg(struct atl1e_hw *hw);
289
290	/* register definition */
291	#define REG_PM_CTRLSTAT 0x44
292
293	#define REG_PCIE_CAP_LIST 0x58
294
295	#define REG_DEVICE_CAP 0x5C
296	#define DEVICE_CAP_MAX_PAYLOAD_MASK 0x7
297	#define DEVICE_CAP_MAX_PAYLOAD_SHIFT 0
298
299	#define REG_DEVICE_CTRL 0x60
300	#define DEVICE_CTRL_MAX_PAYLOAD_MASK 0x7
301	#define DEVICE_CTRL_MAX_PAYLOAD_SHIFT 5
302	#define DEVICE_CTRL_MAX_RREQ_SZ_MASK 0x7
303	#define DEVICE_CTRL_MAX_RREQ_SZ_SHIFT 12
304
305	#define REG_VPD_CAP 0x6C
306	#define VPD_CAP_ID_MASK 0xff
307	#define VPD_CAP_ID_SHIFT 0
308	#define VPD_CAP_NEXT_PTR_MASK 0xFF
309	#define VPD_CAP_NEXT_PTR_SHIFT 8
310	#define VPD_CAP_VPD_ADDR_MASK 0x7FFF
311	#define VPD_CAP_VPD_ADDR_SHIFT 16
312	#define VPD_CAP_VPD_FLAG 0x80000000
313
314	#define REG_VPD_DATA 0x70
315
316	#define REG_SPI_FLASH_CTRL 0x200
317	#define SPI_FLASH_CTRL_STS_NON_RDY 0x1
318	#define SPI_FLASH_CTRL_STS_WEN 0x2
319	#define SPI_FLASH_CTRL_STS_WPEN 0x80
320	#define SPI_FLASH_CTRL_DEV_STS_MASK 0xFF
321	#define SPI_FLASH_CTRL_DEV_STS_SHIFT 0
322	#define SPI_FLASH_CTRL_INS_MASK 0x7
323	#define SPI_FLASH_CTRL_INS_SHIFT 8
324	#define SPI_FLASH_CTRL_START 0x800
325	#define SPI_FLASH_CTRL_EN_VPD 0x2000
326	#define SPI_FLASH_CTRL_LDSTART 0x8000
327	#define SPI_FLASH_CTRL_CS_HI_MASK 0x3
328	#define SPI_FLASH_CTRL_CS_HI_SHIFT 16
329	#define SPI_FLASH_CTRL_CS_HOLD_MASK 0x3
330	#define SPI_FLASH_CTRL_CS_HOLD_SHIFT 18
331	#define SPI_FLASH_CTRL_CLK_LO_MASK 0x3
332	#define SPI_FLASH_CTRL_CLK_LO_SHIFT 20
333	#define SPI_FLASH_CTRL_CLK_HI_MASK 0x3
334	#define SPI_FLASH_CTRL_CLK_HI_SHIFT 22
335	#define SPI_FLASH_CTRL_CS_SETUP_MASK 0x3
336	#define SPI_FLASH_CTRL_CS_SETUP_SHIFT 24
337	#define SPI_FLASH_CTRL_EROM_PGSZ_MASK 0x3
338	#define SPI_FLASH_CTRL_EROM_PGSZ_SHIFT 26
339	#define SPI_FLASH_CTRL_WAIT_READY 0x10000000
340
341	#define REG_SPI_ADDR 0x204
342
343	#define REG_SPI_DATA 0x208
344
345	#define REG_SPI_FLASH_CONFIG 0x20C
346	#define SPI_FLASH_CONFIG_LD_ADDR_MASK 0xFFFFFF
347	#define SPI_FLASH_CONFIG_LD_ADDR_SHIFT 0
348	#define SPI_FLASH_CONFIG_VPD_ADDR_MASK 0x3
349	#define SPI_FLASH_CONFIG_VPD_ADDR_SHIFT 24
350	#define SPI_FLASH_CONFIG_LD_EXIST 0x4000000
351
352
353	#define REG_SPI_FLASH_OP_PROGRAM 0x210
354	#define REG_SPI_FLASH_OP_SC_ERASE 0x211
355	#define REG_SPI_FLASH_OP_CHIP_ERASE 0x212
356	#define REG_SPI_FLASH_OP_RDID 0x213
357	#define REG_SPI_FLASH_OP_WREN 0x214
358	#define REG_SPI_FLASH_OP_RDSR 0x215
359	#define REG_SPI_FLASH_OP_WRSR 0x216
360	#define REG_SPI_FLASH_OP_READ 0x217
361
362	#define REG_TWSI_CTRL 0x218
363	#define TWSI_CTRL_LD_OFFSET_MASK 0xFF
364	#define TWSI_CTRL_LD_OFFSET_SHIFT 0
365	#define TWSI_CTRL_LD_SLV_ADDR_MASK 0x7
366	#define TWSI_CTRL_LD_SLV_ADDR_SHIFT 8
367	#define TWSI_CTRL_SW_LDSTART 0x800
368	#define TWSI_CTRL_HW_LDSTART 0x1000
369	#define TWSI_CTRL_SMB_SLV_ADDR_MASK 0x0x7F
370	#define TWSI_CTRL_SMB_SLV_ADDR_SHIFT 15
371	#define TWSI_CTRL_LD_EXIST 0x400000
372	#define TWSI_CTRL_READ_FREQ_SEL_MASK 0x3
373	#define TWSI_CTRL_READ_FREQ_SEL_SHIFT 23
374	#define TWSI_CTRL_FREQ_SEL_100K 0
375	#define TWSI_CTRL_FREQ_SEL_200K 1
376	#define TWSI_CTRL_FREQ_SEL_300K 2
377	#define TWSI_CTRL_FREQ_SEL_400K 3
378	#define TWSI_CTRL_SMB_SLV_ADDR
379	#define TWSI_CTRL_WRITE_FREQ_SEL_MASK 0x3
380	#define TWSI_CTRL_WRITE_FREQ_SEL_SHIFT 24
381
382
383	#define REG_PCIE_DEV_MISC_CTRL 0x21C
384	#define PCIE_DEV_MISC_CTRL_EXT_PIPE 0x2
385	#define PCIE_DEV_MISC_CTRL_RETRY_BUFDIS 0x1
386	#define PCIE_DEV_MISC_CTRL_SPIROM_EXIST 0x4
387	#define PCIE_DEV_MISC_CTRL_SERDES_ENDIAN 0x8
388	#define PCIE_DEV_MISC_CTRL_SERDES_SEL_DIN 0x10
389
390	#define REG_PCIE_PHYMISC 0x1000
391	#define PCIE_PHYMISC_FORCE_RCV_DET 0x4
392
393	#define REG_LTSSM_TEST_MODE 0x12FC
394	#define LTSSM_TEST_MODE_DEF 0xE000
395
396	/* Selene Master Control Register */
397	#define REG_MASTER_CTRL 0x1400
398	#define MASTER_CTRL_SOFT_RST 0x1
399	#define MASTER_CTRL_MTIMER_EN 0x2
400	#define MASTER_CTRL_ITIMER_EN 0x4
401	#define MASTER_CTRL_MANUAL_INT 0x8
402	#define MASTER_CTRL_ITIMER2_EN 0x20
403	#define MASTER_CTRL_INT_RDCLR 0x40
404	#define MASTER_CTRL_LED_MODE 0x200
405	#define MASTER_CTRL_REV_NUM_SHIFT 16
406	#define MASTER_CTRL_REV_NUM_MASK 0xff
407	#define MASTER_CTRL_DEV_ID_SHIFT 24
408	#define MASTER_CTRL_DEV_ID_MASK 0xff
409
410	/* Timer Initial Value Register */
411	#define REG_MANUAL_TIMER_INIT 0x1404
412
413
414	/* IRQ ModeratorTimer Initial Value Register */
415	#define REG_IRQ_MODU_TIMER_INIT 0x1408 /* w */
416	#define REG_IRQ_MODU_TIMER2_INIT 0x140A /* w */
417
418
419	#define REG_GPHY_CTRL 0x140C
420	#define GPHY_CTRL_EXT_RESET 1
421	#define GPHY_CTRL_PIPE_MOD 2
422	#define GPHY_CTRL_TEST_MODE_MASK 3
423	#define GPHY_CTRL_TEST_MODE_SHIFT 2
424	#define GPHY_CTRL_BERT_START 0x10
425	#define GPHY_CTRL_GATE_25M_EN 0x20
426	#define GPHY_CTRL_LPW_EXIT 0x40
427	#define GPHY_CTRL_PHY_IDDQ 0x80
428	#define GPHY_CTRL_PHY_IDDQ_DIS 0x100
429	#define GPHY_CTRL_PCLK_SEL_DIS 0x200
430	#define GPHY_CTRL_HIB_EN 0x400
431	#define GPHY_CTRL_HIB_PULSE 0x800
432	#define GPHY_CTRL_SEL_ANA_RST 0x1000
433	#define GPHY_CTRL_PHY_PLL_ON 0x2000
434	#define GPHY_CTRL_PWDOWN_HW 0x4000
435	#define GPHY_CTRL_DEFAULT (\
436	GPHY_CTRL_PHY_PLL_ON \|\
437	GPHY_CTRL_SEL_ANA_RST \|\
438	GPHY_CTRL_HIB_PULSE \|\
439	GPHY_CTRL_HIB_EN)
440
441	#define GPHY_CTRL_PW_WOL_DIS (\
442	GPHY_CTRL_PHY_PLL_ON \|\
443	GPHY_CTRL_SEL_ANA_RST \|\
444	GPHY_CTRL_HIB_PULSE \|\
445	GPHY_CTRL_HIB_EN \|\
446	GPHY_CTRL_PWDOWN_HW \|\
447	GPHY_CTRL_PCLK_SEL_DIS \|\
448	GPHY_CTRL_PHY_IDDQ)
449
450	/* IRQ Anti-Lost Timer Initial Value Register */
451	#define REG_CMBDISDMA_TIMER 0x140E
452
453
454	/* Block IDLE Status Register */
455	#define REG_IDLE_STATUS 0x1410
456	#define IDLE_STATUS_RXMAC 1 /* 1: RXMAC state machine is in non-IDLE state. 0: RXMAC is idling */
457	#define IDLE_STATUS_TXMAC 2 /* 1: TXMAC state machine is in non-IDLE state. 0: TXMAC is idling */
458	#define IDLE_STATUS_RXQ 4 /* 1: RXQ state machine is in non-IDLE state. 0: RXQ is idling */
459	#define IDLE_STATUS_TXQ 8 /* 1: TXQ state machine is in non-IDLE state. 0: TXQ is idling */
460	#define IDLE_STATUS_DMAR 0x10 /* 1: DMAR state machine is in non-IDLE state. 0: DMAR is idling */
461	#define IDLE_STATUS_DMAW 0x20 /* 1: DMAW state machine is in non-IDLE state. 0: DMAW is idling */
462	#define IDLE_STATUS_SMB 0x40 /* 1: SMB state machine is in non-IDLE state. 0: SMB is idling */
463	#define IDLE_STATUS_CMB 0x80 /* 1: CMB state machine is in non-IDLE state. 0: CMB is idling */
464
465	/* MDIO Control Register */
466	#define REG_MDIO_CTRL 0x1414
467	#define MDIO_DATA_MASK 0xffff /* On MDIO write, the 16-bit control data to write to PHY MII management register */
468	#define MDIO_DATA_SHIFT 0 /* On MDIO read, the 16-bit status data that was read from the PHY MII management register*/
469	#define MDIO_REG_ADDR_MASK 0x1f /* MDIO register address */
470	#define MDIO_REG_ADDR_SHIFT 16
471	#define MDIO_RW 0x200000 /* 1: read, 0: write */
472	#define MDIO_SUP_PREAMBLE 0x400000 /* Suppress preamble */
473	#define MDIO_START 0x800000 /* Write 1 to initiate the MDIO master. And this bit is self cleared after one cycle*/
474	#define MDIO_CLK_SEL_SHIFT 24
475	#define MDIO_CLK_25_4 0
476	#define MDIO_CLK_25_6 2
477	#define MDIO_CLK_25_8 3
478	#define MDIO_CLK_25_10 4
479	#define MDIO_CLK_25_14 5
480	#define MDIO_CLK_25_20 6
481	#define MDIO_CLK_25_28 7
482	#define MDIO_BUSY 0x8000000
483	#define MDIO_AP_EN 0x10000000
484	#define MDIO_WAIT_TIMES 10
485
486	/* MII PHY Status Register */
487	#define REG_PHY_STATUS 0x1418
488	#define PHY_STATUS_100M 0x20000
489	#define PHY_STATUS_EMI_CA 0x40000
490
491	/* BIST Control and Status Register0 (for the Packet Memory) */
492	#define REG_BIST0_CTRL 0x141c
493	#define BIST0_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
494	/* BIST process and reset to zero when BIST is done */
495	#define BIST0_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
496	/* decoder failure or more than 1 cell stuck-to-x failure */
497	#define BIST0_FUSE_FLAG 0x4 /* 1: Indicating one cell has been fixed */
498
499	/* BIST Control and Status Register1(for the retry buffer of PCI Express) */
500	#define REG_BIST1_CTRL 0x1420
501	#define BIST1_NOW 0x1 /* 1: To trigger BIST0 logic. This bit stays high during the */
502	/* BIST process and reset to zero when BIST is done */
503	#define BIST1_SRAM_FAIL 0x2 /* 1: The SRAM failure is un-repairable because it has address */
504	/* decoder failure or more than 1 cell stuck-to-x failure.*/
505	#define BIST1_FUSE_FLAG 0x4
506
507	/* SerDes Lock Detect Control and Status Register */
508	#define REG_SERDES_LOCK 0x1424
509	#define SERDES_LOCK_DETECT 1 /* 1: SerDes lock detected . This signal comes from Analog SerDes */
510	#define SERDES_LOCK_DETECT_EN 2 /* 1: Enable SerDes Lock detect function */
511
512	/* MAC Control Register */
513	#define REG_MAC_CTRL 0x1480
514	#define MAC_CTRL_TX_EN 1 /* 1: Transmit Enable */
515	#define MAC_CTRL_RX_EN 2 /* 1: Receive Enable */
516	#define MAC_CTRL_TX_FLOW 4 /* 1: Transmit Flow Control Enable */
517	#define MAC_CTRL_RX_FLOW 8 /* 1: Receive Flow Control Enable */
518	#define MAC_CTRL_LOOPBACK 0x10 /* 1: Loop back at G/MII Interface */
519	#define MAC_CTRL_DUPLX 0x20 /* 1: Full-duplex mode 0: Half-duplex mode */
520	#define MAC_CTRL_ADD_CRC 0x40 /* 1: Instruct MAC to attach CRC on all egress Ethernet frames */
521	#define MAC_CTRL_PAD 0x80 /* 1: Instruct MAC to pad short frames to 60-bytes, and then attach CRC. This bit has higher priority over CRC_EN */
522	#define MAC_CTRL_LENCHK 0x100 /* 1: Instruct MAC to check if length field matches the real packet length */
523	#define MAC_CTRL_HUGE_EN 0x200 /* 1: receive Jumbo frame enable */
524	#define MAC_CTRL_PRMLEN_SHIFT 10 /* Preamble length */
525	#define MAC_CTRL_PRMLEN_MASK 0xf
526	#define MAC_CTRL_RMV_VLAN 0x4000 /* 1: to remove VLAN Tag automatically from all receive packets */
527	#define MAC_CTRL_PROMIS_EN 0x8000 /* 1: Promiscuous Mode Enable */
528	#define MAC_CTRL_TX_PAUSE 0x10000 /* 1: transmit test pause */
529	#define MAC_CTRL_SCNT 0x20000 /* 1: shortcut slot time counter */
530	#define MAC_CTRL_SRST_TX 0x40000 /* 1: synchronized reset Transmit MAC module */
531	#define MAC_CTRL_TX_SIMURST 0x80000 /* 1: transmit simulation reset */
532	#define MAC_CTRL_SPEED_SHIFT 20 /* 10: gigabit 01:10M/100M */
533	#define MAC_CTRL_SPEED_MASK 0x300000
534	#define MAC_CTRL_SPEED_1000 2
535	#define MAC_CTRL_SPEED_10_100 1
536	#define MAC_CTRL_DBG_TX_BKPRESURE 0x400000 /* 1: transmit maximum backoff (half-duplex test bit) */
537	#define MAC_CTRL_TX_HUGE 0x800000 /* 1: transmit huge enable */
538	#define MAC_CTRL_RX_CHKSUM_EN 0x1000000 /* 1: RX checksum enable */
539	#define MAC_CTRL_MC_ALL_EN 0x2000000 /* 1: upload all multicast frame without error to system */
540	#define MAC_CTRL_BC_EN 0x4000000 /* 1: upload all broadcast frame without error to system */
541	#define MAC_CTRL_DBG 0x8000000 /* 1: upload all received frame to system (Debug Mode) */
542
543	/* MAC IPG/IFG Control Register */
544	#define REG_MAC_IPG_IFG 0x1484
545	#define MAC_IPG_IFG_IPGT_SHIFT 0 /* Desired back to back inter-packet gap. The default is 96-bit time */
546	#define MAC_IPG_IFG_IPGT_MASK 0x7f
547	#define MAC_IPG_IFG_MIFG_SHIFT 8 /* Minimum number of IFG to enforce in between RX frames */
548	#define MAC_IPG_IFG_MIFG_MASK 0xff /* Frame gap below such IFP is dropped */
549	#define MAC_IPG_IFG_IPGR1_SHIFT 16 /* 64bit Carrier-Sense window */
550	#define MAC_IPG_IFG_IPGR1_MASK 0x7f
551	#define MAC_IPG_IFG_IPGR2_SHIFT 24 /* 96-bit IPG window */
552	#define MAC_IPG_IFG_IPGR2_MASK 0x7f
553
554	/* MAC STATION ADDRESS */
555	#define REG_MAC_STA_ADDR 0x1488
556
557	/* Hash table for multicast address */
558	#define REG_RX_HASH_TABLE 0x1490
559
560
561	/* MAC Half-Duplex Control Register */
562	#define REG_MAC_HALF_DUPLX_CTRL 0x1498
563	#define MAC_HALF_DUPLX_CTRL_LCOL_SHIFT 0 /* Collision Window */
564	#define MAC_HALF_DUPLX_CTRL_LCOL_MASK 0x3ff
565	#define MAC_HALF_DUPLX_CTRL_RETRY_SHIFT 12 /* Retransmission maximum, afterwards the packet will be discarded */
566	#define MAC_HALF_DUPLX_CTRL_RETRY_MASK 0xf
567	#define MAC_HALF_DUPLX_CTRL_EXC_DEF_EN 0x10000 /* 1: Allow the transmission of a packet which has been excessively deferred */
568	#define MAC_HALF_DUPLX_CTRL_NO_BACK_C 0x20000 /* 1: No back-off on collision, immediately start the retransmission */
569	#define MAC_HALF_DUPLX_CTRL_NO_BACK_P 0x40000 /* 1: No back-off on backpressure, immediately start the transmission after back pressure */
570	#define MAC_HALF_DUPLX_CTRL_ABEBE 0x80000 /* 1: Alternative Binary Exponential Back-off Enabled */
571	#define MAC_HALF_DUPLX_CTRL_ABEBT_SHIFT 20 /* Maximum binary exponential number */
572	#define MAC_HALF_DUPLX_CTRL_ABEBT_MASK 0xf
573	#define MAC_HALF_DUPLX_CTRL_JAMIPG_SHIFT 24 /* IPG to start JAM for collision based flow control in half-duplex */
574	#define MAC_HALF_DUPLX_CTRL_JAMIPG_MASK 0xf /* mode. In unit of 8-bit time */
575
576	/* Maximum Frame Length Control Register */
577	#define REG_MTU 0x149c
578
579	/* Wake-On-Lan control register */
580	#define REG_WOL_CTRL 0x14a0
581	#define WOL_PATTERN_EN 0x00000001
582	#define WOL_PATTERN_PME_EN 0x00000002
583	#define WOL_MAGIC_EN 0x00000004
584	#define WOL_MAGIC_PME_EN 0x00000008
585	#define WOL_LINK_CHG_EN 0x00000010
586	#define WOL_LINK_CHG_PME_EN 0x00000020
587	#define WOL_PATTERN_ST 0x00000100
588	#define WOL_MAGIC_ST 0x00000200
589	#define WOL_LINKCHG_ST 0x00000400
590	#define WOL_CLK_SWITCH_EN 0x00008000
591	#define WOL_PT0_EN 0x00010000
592	#define WOL_PT1_EN 0x00020000
593	#define WOL_PT2_EN 0x00040000
594	#define WOL_PT3_EN 0x00080000
595	#define WOL_PT4_EN 0x00100000
596	#define WOL_PT5_EN 0x00200000
597	#define WOL_PT6_EN 0x00400000
598	/* WOL Length ( 2 DWORD ) */
599	#define REG_WOL_PATTERN_LEN 0x14a4
600	#define WOL_PT_LEN_MASK 0x7f
601	#define WOL_PT0_LEN_SHIFT 0
602	#define WOL_PT1_LEN_SHIFT 8
603	#define WOL_PT2_LEN_SHIFT 16
604	#define WOL_PT3_LEN_SHIFT 24
605	#define WOL_PT4_LEN_SHIFT 0
606	#define WOL_PT5_LEN_SHIFT 8
607	#define WOL_PT6_LEN_SHIFT 16
608
609	/* Internal SRAM Partition Register */
610	#define REG_SRAM_TRD_ADDR 0x1518
611	#define REG_SRAM_TRD_LEN 0x151C
612	#define REG_SRAM_RXF_ADDR 0x1520
613	#define REG_SRAM_RXF_LEN 0x1524
614	#define REG_SRAM_TXF_ADDR 0x1528
615	#define REG_SRAM_TXF_LEN 0x152C
616	#define REG_SRAM_TCPH_ADDR 0x1530
617	#define REG_SRAM_PKTH_ADDR 0x1532
618
619	/* Load Ptr Register */
620	#define REG_LOAD_PTR 0x1534 /* Software sets this bit after the initialization of the head and tail */
621
622	/*
623	* addresses of all descriptors, as well as the following descriptor
624	* control register, which triggers each function block to load the head
625	* pointer to prepare for the operation. This bit is then self-cleared
626	* after one cycle.
627	*/
628
629	/* Descriptor Control register */
630	#define REG_RXF3_BASE_ADDR_HI 0x153C
631	#define REG_DESC_BASE_ADDR_HI 0x1540
632	#define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
633	#define REG_HOST_RXF0_PAGE0_LO 0x1544
634	#define REG_HOST_RXF0_PAGE1_LO 0x1548
635	#define REG_TPD_BASE_ADDR_LO 0x154C
636	#define REG_RXF1_BASE_ADDR_HI 0x1550
637	#define REG_RXF2_BASE_ADDR_HI 0x1554
638	#define REG_HOST_RXFPAGE_SIZE 0x1558
639	#define REG_TPD_RING_SIZE 0x155C
640	/* RSS about */
641	#define REG_RSS_KEY0 0x14B0
642	#define REG_RSS_KEY1 0x14B4
643	#define REG_RSS_KEY2 0x14B8
644	#define REG_RSS_KEY3 0x14BC
645	#define REG_RSS_KEY4 0x14C0
646	#define REG_RSS_KEY5 0x14C4
647	#define REG_RSS_KEY6 0x14C8
648	#define REG_RSS_KEY7 0x14CC
649	#define REG_RSS_KEY8 0x14D0
650	#define REG_RSS_KEY9 0x14D4
651	#define REG_IDT_TABLE4 0x14E0
652	#define REG_IDT_TABLE5 0x14E4
653	#define REG_IDT_TABLE6 0x14E8
654	#define REG_IDT_TABLE7 0x14EC
655	#define REG_IDT_TABLE0 0x1560
656	#define REG_IDT_TABLE1 0x1564
657	#define REG_IDT_TABLE2 0x1568
658	#define REG_IDT_TABLE3 0x156C
659	#define REG_IDT_TABLE REG_IDT_TABLE0
660	#define REG_RSS_HASH_VALUE 0x1570
661	#define REG_RSS_HASH_FLAG 0x1574
662	#define REG_BASE_CPU_NUMBER 0x157C
663
664
665	/* TXQ Control Register */
666	#define REG_TXQ_CTRL 0x1580
667	#define TXQ_CTRL_NUM_TPD_BURST_MASK 0xF
668	#define TXQ_CTRL_NUM_TPD_BURST_SHIFT 0
669	#define TXQ_CTRL_EN 0x20 /* 1: Enable TXQ */
670	#define TXQ_CTRL_ENH_MODE 0x40 /* Performance enhancement mode, in which up to two back-to-back DMA read commands might be dispatched. */
671	#define TXQ_CTRL_TXF_BURST_NUM_SHIFT 16 /* Number of data byte to read in a cache-aligned burst. Each SRAM entry is 8-byte in length. */
672	#define TXQ_CTRL_TXF_BURST_NUM_MASK 0xffff
673
674	/* Jumbo packet Threshold for task offload */
675	#define REG_TX_EARLY_TH 0x1584 /* Jumbo frame threshold in QWORD unit. Packet greater than */
676	/* JUMBO_TASK_OFFLOAD_THRESHOLD will not be task offloaded. */
677	#define TX_TX_EARLY_TH_MASK 0x7ff
678	#define TX_TX_EARLY_TH_SHIFT 0
679
680
681	/* RXQ Control Register */
682	#define REG_RXQ_CTRL 0x15A0
683	#define RXQ_CTRL_PBA_ALIGN_32 0 /* rx-packet alignment */
684	#define RXQ_CTRL_PBA_ALIGN_64 1
685	#define RXQ_CTRL_PBA_ALIGN_128 2
686	#define RXQ_CTRL_PBA_ALIGN_256 3
687	#define RXQ_CTRL_Q1_EN 0x10
688	#define RXQ_CTRL_Q2_EN 0x20
689	#define RXQ_CTRL_Q3_EN 0x40
690	#define RXQ_CTRL_IPV6_XSUM_VERIFY_EN 0x80
691	#define RXQ_CTRL_HASH_TLEN_SHIFT 8
692	#define RXQ_CTRL_HASH_TLEN_MASK 0xFF
693	#define RXQ_CTRL_HASH_TYPE_IPV4 0x10000
694	#define RXQ_CTRL_HASH_TYPE_IPV4_TCP 0x20000
695	#define RXQ_CTRL_HASH_TYPE_IPV6 0x40000
696	#define RXQ_CTRL_HASH_TYPE_IPV6_TCP 0x80000
697	#define RXQ_CTRL_RSS_MODE_DISABLE 0
698	#define RXQ_CTRL_RSS_MODE_SQSINT 0x4000000
699	#define RXQ_CTRL_RSS_MODE_MQUESINT 0x8000000
700	#define RXQ_CTRL_RSS_MODE_MQUEMINT 0xC000000
701	#define RXQ_CTRL_NIP_QUEUE_SEL_TBL 0x10000000
702	#define RXQ_CTRL_HASH_ENABLE 0x20000000
703	#define RXQ_CTRL_CUT_THRU_EN 0x40000000
704	#define RXQ_CTRL_EN 0x80000000
705
706	/* Rx jumbo packet threshold and rrd retirement timer */
707	#define REG_RXQ_JMBOSZ_RRDTIM 0x15A4
708	/*
709	* Jumbo packet threshold for non-VLAN packet, in QWORD (64-bit) unit.
710	* When the packet length greater than or equal to this value, RXQ
711	* shall start cut-through forwarding of the received packet.
712	*/
713	#define RXQ_JMBOSZ_TH_MASK 0x7ff
714	#define RXQ_JMBOSZ_TH_SHIFT 0 /* RRD retirement timer. Decrement by 1 after every 512ns passes*/
715	#define RXQ_JMBO_LKAH_MASK 0xf
716	#define RXQ_JMBO_LKAH_SHIFT 11
717
718	/* RXF flow control register */
719	#define REG_RXQ_RXF_PAUSE_THRESH 0x15A8
720	#define RXQ_RXF_PAUSE_TH_HI_SHIFT 0
721	#define RXQ_RXF_PAUSE_TH_HI_MASK 0xfff
722	#define RXQ_RXF_PAUSE_TH_LO_SHIFT 16
723	#define RXQ_RXF_PAUSE_TH_LO_MASK 0xfff
724
725
726	/* DMA Engine Control Register */
727	#define REG_DMA_CTRL 0x15C0
728	#define DMA_CTRL_DMAR_IN_ORDER 0x1
729	#define DMA_CTRL_DMAR_ENH_ORDER 0x2
730	#define DMA_CTRL_DMAR_OUT_ORDER 0x4
731	#define DMA_CTRL_RCB_VALUE 0x8
732	#define DMA_CTRL_DMAR_BURST_LEN_SHIFT 4
733	#define DMA_CTRL_DMAR_BURST_LEN_MASK 7
734	#define DMA_CTRL_DMAW_BURST_LEN_SHIFT 7
735	#define DMA_CTRL_DMAW_BURST_LEN_MASK 7
736	#define DMA_CTRL_DMAR_REQ_PRI 0x400
737	#define DMA_CTRL_DMAR_DLY_CNT_MASK 0x1F
738	#define DMA_CTRL_DMAR_DLY_CNT_SHIFT 11
739	#define DMA_CTRL_DMAW_DLY_CNT_MASK 0xF
740	#define DMA_CTRL_DMAW_DLY_CNT_SHIFT 16
741	#define DMA_CTRL_TXCMB_EN 0x100000
742	#define DMA_CTRL_RXCMB_EN 0x200000
743
744
745	/* CMB/SMB Control Register */
746	#define REG_SMB_STAT_TIMER 0x15C4
747	#define REG_TRIG_RRD_THRESH 0x15CA
748	#define REG_TRIG_TPD_THRESH 0x15C8
749	#define REG_TRIG_TXTIMER 0x15CC
750	#define REG_TRIG_RXTIMER 0x15CE
751
752	/* HOST RXF Page 1,2,3 address */
753	#define REG_HOST_RXF1_PAGE0_LO 0x15D0
754	#define REG_HOST_RXF1_PAGE1_LO 0x15D4
755	#define REG_HOST_RXF2_PAGE0_LO 0x15D8
756	#define REG_HOST_RXF2_PAGE1_LO 0x15DC
757	#define REG_HOST_RXF3_PAGE0_LO 0x15E0
758	#define REG_HOST_RXF3_PAGE1_LO 0x15E4
759
760	/* Mail box */
761	#define REG_MB_RXF1_RADDR 0x15B4
762	#define REG_MB_RXF2_RADDR 0x15B8
763	#define REG_MB_RXF3_RADDR 0x15BC
764	#define REG_MB_TPD_PROD_IDX 0x15F0
765
766	/* RXF-Page 0-3 PageNo & Valid bit */
767	#define REG_HOST_RXF0_PAGE0_VLD 0x15F4
768	#define HOST_RXF_VALID 1
769	#define HOST_RXF_PAGENO_SHIFT 1
770	#define HOST_RXF_PAGENO_MASK 0x7F
771	#define REG_HOST_RXF0_PAGE1_VLD 0x15F5
772	#define REG_HOST_RXF1_PAGE0_VLD 0x15F6
773	#define REG_HOST_RXF1_PAGE1_VLD 0x15F7
774	#define REG_HOST_RXF2_PAGE0_VLD 0x15F8
775	#define REG_HOST_RXF2_PAGE1_VLD 0x15F9
776	#define REG_HOST_RXF3_PAGE0_VLD 0x15FA
777	#define REG_HOST_RXF3_PAGE1_VLD 0x15FB
778
779	/* Interrupt Status Register */
780	#define REG_ISR 0x1600
781	#define ISR_SMB 1
782	#define ISR_TIMER 2 /* Interrupt when Timer is counted down to zero */
783	/*
784	* Software manual interrupt, for debug. Set when SW_MAN_INT_EN is set
785	* in Table 51 Selene Master Control Register (Offset 0x1400).
786	*/
787	#define ISR_MANUAL 4
788	#define ISR_HW_RXF_OV 8 /* RXF overflow interrupt */
789	#define ISR_HOST_RXF0_OV 0x10
790	#define ISR_HOST_RXF1_OV 0x20
791	#define ISR_HOST_RXF2_OV 0x40
792	#define ISR_HOST_RXF3_OV 0x80
793	#define ISR_TXF_UN 0x100
794	#define ISR_RX0_PAGE_FULL 0x200
795	#define ISR_DMAR_TO_RST 0x400
796	#define ISR_DMAW_TO_RST 0x800
797	#define ISR_GPHY 0x1000
798	#define ISR_TX_CREDIT 0x2000
799	#define ISR_GPHY_LPW 0x4000 /* GPHY low power state interrupt */
800	#define ISR_RX_PKT 0x10000 /* One packet received, triggered by RFD */
801	#define ISR_TX_PKT 0x20000 /* One packet transmitted, triggered by TPD */
802	#define ISR_TX_DMA 0x40000
803	#define ISR_RX_PKT_1 0x80000
804	#define ISR_RX_PKT_2 0x100000
805	#define ISR_RX_PKT_3 0x200000
806	#define ISR_MAC_RX 0x400000
807	#define ISR_MAC_TX 0x800000
808	#define ISR_UR_DETECTED 0x1000000
809	#define ISR_FERR_DETECTED 0x2000000
810	#define ISR_NFERR_DETECTED 0x4000000
811	#define ISR_CERR_DETECTED 0x8000000
812	#define ISR_PHY_LINKDOWN 0x10000000
813	#define ISR_DIS_INT 0x80000000
814
815
816	/* Interrupt Mask Register */
817	#define REG_IMR 0x1604
818
819
820	#define IMR_NORMAL_MASK (\
821	ISR_SMB \|\
822	ISR_TXF_UN \|\
823	ISR_HW_RXF_OV \|\
824	ISR_HOST_RXF0_OV\|\
825	ISR_MANUAL \|\
826	ISR_GPHY \|\
827	ISR_GPHY_LPW \|\
828	ISR_DMAR_TO_RST \|\
829	ISR_DMAW_TO_RST \|\
830	ISR_PHY_LINKDOWN\|\
831	ISR_RX_PKT \|\
832	ISR_TX_PKT)
833
834	#define ISR_TX_EVENT (ISR_TXF_UN \| ISR_TX_PKT)
835	#define ISR_RX_EVENT (ISR_HOST_RXF0_OV \| ISR_HW_RXF_OV \| ISR_RX_PKT)
836
837	#define REG_MAC_RX_STATUS_BIN 0x1700
838	#define REG_MAC_RX_STATUS_END 0x175c
839	#define REG_MAC_TX_STATUS_BIN 0x1760
840	#define REG_MAC_TX_STATUS_END 0x17c0
841
842	/* Hardware Offset Register */
843	#define REG_HOST_RXF0_PAGEOFF 0x1800
844	#define REG_TPD_CONS_IDX 0x1804
845	#define REG_HOST_RXF1_PAGEOFF 0x1808
846	#define REG_HOST_RXF2_PAGEOFF 0x180C
847	#define REG_HOST_RXF3_PAGEOFF 0x1810
848
849	/* RXF-Page 0-3 Offset DMA Address */
850	#define REG_HOST_RXF0_MB0_LO 0x1820
851	#define REG_HOST_RXF0_MB1_LO 0x1824
852	#define REG_HOST_RXF1_MB0_LO 0x1828
853	#define REG_HOST_RXF1_MB1_LO 0x182C
854	#define REG_HOST_RXF2_MB0_LO 0x1830
855	#define REG_HOST_RXF2_MB1_LO 0x1834
856	#define REG_HOST_RXF3_MB0_LO 0x1838
857	#define REG_HOST_RXF3_MB1_LO 0x183C
858
859	/* Tpd CMB DMA Address */
860	#define REG_HOST_TX_CMB_LO 0x1840
861	#define REG_HOST_SMB_ADDR_LO 0x1844
862
863	/* DEBUG ADDR */
864	#define REG_DEBUG_DATA0 0x1900
865	#define REG_DEBUG_DATA1 0x1904
866
867	/*************************** MII definition *************************************/
868	/* PHY Common Register */
869	#define MII_BMCR 0x00
870	#define MII_BMSR 0x01
871	#define MII_PHYSID1 0x02
872	#define MII_PHYSID2 0x03
873	#define MII_ADVERTISE 0x04
874	#define MII_LPA 0x05
875	#define MII_EXPANSION 0x06
876	#define MII_AT001_CR 0x09
877	#define MII_AT001_SR 0x0A
878	#define MII_AT001_ESR 0x0F
879	#define MII_AT001_PSCR 0x10
880	#define MII_AT001_PSSR 0x11
881	#define MII_INT_CTRL 0x12
882	#define MII_INT_STATUS 0x13
883	#define MII_SMARTSPEED 0x14
884	#define MII_RERRCOUNTER 0x15
885	#define MII_SREVISION 0x16
886	#define MII_RESV1 0x17
887	#define MII_LBRERROR 0x18
888	#define MII_PHYADDR 0x19
889	#define MII_RESV2 0x1a
890	#define MII_TPISTATUS 0x1b
891	#define MII_NCONFIG 0x1c
892
893	#define MII_DBG_ADDR 0x1D
894	#define MII_DBG_DATA 0x1E
895
896
897	/* PHY Control Register */
898	#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
899	#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
900	#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
901	#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
902	#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
903	#define MII_CR_POWER_DOWN 0x0800 /* Power down */
904	#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
905	#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
906	#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
907	#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
908	#define MII_CR_SPEED_MASK 0x2040
909	#define MII_CR_SPEED_1000 0x0040
910	#define MII_CR_SPEED_100 0x2000
911	#define MII_CR_SPEED_10 0x0000
912
913
914	/* PHY Status Register */
915	#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
916	#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
917	#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
918	#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
919	#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
920	#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
921	#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
922	#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
923	#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
924	#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
925	#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
926	#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
927	#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
928	#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
929	#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
930
931	/* Link partner ability register. */
932	#define MII_LPA_SLCT 0x001f /* Same as advertise selector */
933	#define MII_LPA_10HALF 0x0020 /* Can do 10mbps half-duplex */
934	#define MII_LPA_10FULL 0x0040 /* Can do 10mbps full-duplex */
935	#define MII_LPA_100HALF 0x0080 /* Can do 100mbps half-duplex */
936	#define MII_LPA_100FULL 0x0100 /* Can do 100mbps full-duplex */
937	#define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
938	#define MII_LPA_PAUSE 0x0400 /* PAUSE */
939	#define MII_LPA_ASYPAUSE 0x0800 /* Asymmetrical PAUSE */
940	#define MII_LPA_RFAULT 0x2000 /* Link partner faulted */
941	#define MII_LPA_LPACK 0x4000 /* Link partner acked us */
942	#define MII_LPA_NPAGE 0x8000 /* Next page bit */
943
944	/* Autoneg Advertisement Register */
945	#define MII_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
946	#define MII_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
947	#define MII_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
948	#define MII_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
949	#define MII_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
950	#define MII_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
951	#define MII_AR_PAUSE 0x0400 /* Pause operation desired */
952	#define MII_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
953	#define MII_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
954	#define MII_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
955	#define MII_AR_SPEED_MASK 0x01E0
956	#define MII_AR_DEFAULT_CAP_MASK 0x0DE0
957
958	/* 1000BASE-T Control Register */
959	#define MII_AT001_CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
960	#define MII_AT001_CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
961	#define MII_AT001_CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
962	/* 0=DTE device */
963	#define MII_AT001_CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
964	/* 0=Configure PHY as Slave */
965	#define MII_AT001_CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
966	/* 0=Automatic Master/Slave config */
967	#define MII_AT001_CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
968	#define MII_AT001_CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
969	#define MII_AT001_CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
970	#define MII_AT001_CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
971	#define MII_AT001_CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
972	#define MII_AT001_CR_1000T_SPEED_MASK 0x0300
973	#define MII_AT001_CR_1000T_DEFAULT_CAP_MASK 0x0300
974
975	/* 1000BASE-T Status Register */
976	#define MII_AT001_SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
977	#define MII_AT001_SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
978	#define MII_AT001_SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
979	#define MII_AT001_SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
980	#define MII_AT001_SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
981	#define MII_AT001_SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
982	#define MII_AT001_SR_1000T_REMOTE_RX_STATUS_SHIFT 12
983	#define MII_AT001_SR_1000T_LOCAL_RX_STATUS_SHIFT 13
984
985	/* Extended Status Register */
986	#define MII_AT001_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
987	#define MII_AT001_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
988	#define MII_AT001_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
989	#define MII_AT001_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
990
991	/* AT001 PHY Specific Control Register */
992	#define MII_AT001_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
993	#define MII_AT001_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
994	#define MII_AT001_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
995	#define MII_AT001_PSCR_MAC_POWERDOWN 0x0008
996	#define MII_AT001_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
997	* 0=CLK125 toggling
998	*/
999	#define MII_AT001_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
1000	/* Manual MDI configuration */
1001	#define MII_AT001_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
1002	#define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
1003	* 100BASE-TX/10BASE-T:
1004	* MDI Mode
1005	*/
1006	#define MII_AT001_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
1007	* all speeds.
1008	*/
1009	#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE 0x0080
1010	/* 1=Enable Extended 10BASE-T distance
1011	* (Lower 10BASE-T RX Threshold)
1012	* 0=Normal 10BASE-T RX Threshold */
1013	#define MII_AT001_PSCR_MII_5BIT_ENABLE 0x0100
1014	/* 1=5-Bit interface in 100BASE-TX
1015	* 0=MII interface in 100BASE-TX */
1016	#define MII_AT001_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
1017	#define MII_AT001_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
1018	#define MII_AT001_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
1019	#define MII_AT001_PSCR_POLARITY_REVERSAL_SHIFT 1
1020	#define MII_AT001_PSCR_AUTO_X_MODE_SHIFT 5
1021	#define MII_AT001_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
1022	/* AT001 PHY Specific Status Register */
1023	#define MII_AT001_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
1024	#define MII_AT001_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
1025	#define MII_AT001_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
1026	#define MII_AT001_PSSR_10MBS 0x0000 /* 00=10Mbs */
1027	#define MII_AT001_PSSR_100MBS 0x4000 /* 01=100Mbs */
1028	#define MII_AT001_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
1029
1030
1031	#endif /* _ATL1_E_H_ */

Note: See TracBrowser for help on using the repository browser.

Download in other formats: