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source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/e1000/e1000_hw.c

Last change on this file was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago
bootstuff
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File size: 317.5 KB

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1	/*******************************************************************************
2
3	Intel PRO/1000 Linux driver
4	Copyright(c) 1999 - 2006 Intel Corporation.
5
6	This program is free software; you can redistribute it and/or modify it
7	under the terms and conditions of the GNU General Public License,
8	version 2, as published by the Free Software Foundation.
9
10	This program is distributed in the hope it will be useful, but WITHOUT
11	ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12	FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13	more details.
14
15	You should have received a copy of the GNU General Public License along with
16	this program; if not, write to the Free Software Foundation, Inc.,
17	51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
18
19	The full GNU General Public License is included in this distribution in
20	the file called "COPYING".
21
22	Contact Information:
23	Linux NICS <linux.nics@intel.com>
24	e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25	Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26
27	*******************************************************************************/
28
29	FILE_LICENCE ( GPL2_ONLY );
30
31	/* e1000_hw.c
32	* Shared functions for accessing and configuring the MAC
33	*/
34
35
36	#include "e1000_hw.h"
37
38	static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
39	static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
40	static int32_t e1000_read_kmrn_reg(struct e1000_hw hw, uint32_t reg_addr, uint16_t data);
41	static int32_t e1000_write_kmrn_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
42	static int32_t e1000_get_software_semaphore(struct e1000_hw *hw);
43	static void e1000_release_software_semaphore(struct e1000_hw *hw);
44
45	static uint8_t e1000_arc_subsystem_valid(struct e1000_hw *hw);
46	static int32_t e1000_check_downshift(struct e1000_hw *hw);
47	static int32_t e1000_check_polarity(struct e1000_hw hw, e1000_rev_polarity polarity);
48	static void e1000_clear_hw_cntrs(struct e1000_hw *hw);
49	static void e1000_clear_vfta(struct e1000_hw *hw);
50	static int32_t e1000_commit_shadow_ram(struct e1000_hw *hw);
51	static int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
52	static int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
53	static int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
54	static int32_t e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank);
55	static int32_t e1000_get_auto_rd_done(struct e1000_hw *hw);
56	static int32_t e1000_get_cable_length(struct e1000_hw hw, uint16_t min_length, uint16_t *max_length);
57	static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
58	static int32_t e1000_get_phy_cfg_done(struct e1000_hw *hw);
59	static int32_t e1000_get_software_flag(struct e1000_hw *hw);
60	static int32_t e1000_ich8_cycle_init(struct e1000_hw *hw);
61	static int32_t e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout);
62	static int32_t e1000_id_led_init(struct e1000_hw *hw);
63	static int32_t e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw, uint32_t cnf_base_addr, uint32_t cnf_size);
64	static int32_t e1000_init_lcd_from_nvm(struct e1000_hw *hw);
65	static void e1000_init_rx_addrs(struct e1000_hw *hw);
66	static void e1000_initialize_hardware_bits(struct e1000_hw *hw);
67	static boolean_t e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw);
68	static int32_t e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw);
69	static int32_t e1000_mng_enable_host_if(struct e1000_hw *hw);
70	static int32_t e1000_mng_host_if_write(struct e1000_hw hw, uint8_t buffer, uint16_t length, uint16_t offset, uint8_t *sum);
71	static int32_t e1000_mng_write_cmd_header(struct e1000_hw* hw, struct e1000_host_mng_command_header* hdr);
72	static int32_t e1000_mng_write_commit(struct e1000_hw *hw);
73	static int32_t e1000_phy_ife_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
74	static int32_t e1000_phy_igp_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
75	static int32_t e1000_read_eeprom_eerd(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
76	static int32_t e1000_write_eeprom_eewr(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
77	static int32_t e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd);
78	static int32_t e1000_phy_m88_get_info(struct e1000_hw hw, struct e1000_phy_info phy_info);
79	static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
80	static int32_t e1000_read_ich8_byte(struct e1000_hw hw, uint32_t index, uint8_t data);
81	static int32_t e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
82	static int32_t e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte);
83	static int32_t e1000_read_ich8_word(struct e1000_hw hw, uint32_t index, uint16_t data);
84	static int32_t e1000_read_ich8_data(struct e1000_hw hw, uint32_t index, uint32_t size, uint16_t data);
85	static int32_t e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size, uint16_t data);
86	static int32_t e1000_read_eeprom_ich8(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
87	static int32_t e1000_write_eeprom_ich8(struct e1000_hw hw, uint16_t offset, uint16_t words, uint16_t data);
88	static void e1000_release_software_flag(struct e1000_hw *hw);
89	static int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
90	static int32_t e1000_set_d0_lplu_state(struct e1000_hw *hw, boolean_t active);
91	static int32_t e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop);
92	static void e1000_set_pci_express_master_disable(struct e1000_hw *hw);
93	static int32_t e1000_wait_autoneg(struct e1000_hw *hw);
94	static void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
95	static int32_t e1000_set_phy_type(struct e1000_hw *hw);
96	static void e1000_phy_init_script(struct e1000_hw *hw);
97	static int32_t e1000_setup_copper_link(struct e1000_hw *hw);
98	static int32_t e1000_setup_fiber_serdes_link(struct e1000_hw *hw);
99	static int32_t e1000_adjust_serdes_amplitude(struct e1000_hw *hw);
100	static int32_t e1000_phy_force_speed_duplex(struct e1000_hw *hw);
101	static int32_t e1000_config_mac_to_phy(struct e1000_hw *hw);
102	static void e1000_raise_mdi_clk(struct e1000_hw hw, uint32_t ctrl);
103	static void e1000_lower_mdi_clk(struct e1000_hw hw, uint32_t ctrl);
104	static void e1000_shift_out_mdi_bits(struct e1000_hw *hw, uint32_t data,
105	uint16_t count);
106	static uint16_t e1000_shift_in_mdi_bits(struct e1000_hw *hw);
107	static int32_t e1000_phy_reset_dsp(struct e1000_hw *hw);
108	static int32_t e1000_write_eeprom_spi(struct e1000_hw *hw, uint16_t offset,
109	uint16_t words, uint16_t *data);
110	static int32_t e1000_write_eeprom_microwire(struct e1000_hw *hw,
111	uint16_t offset, uint16_t words,
112	uint16_t *data);
113	static int32_t e1000_spi_eeprom_ready(struct e1000_hw *hw);
114	static void e1000_raise_ee_clk(struct e1000_hw hw, uint32_t eecd);
115	static void e1000_lower_ee_clk(struct e1000_hw hw, uint32_t eecd);
116	static void e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data,
117	uint16_t count);
118	static int32_t e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
119	uint16_t phy_data);
120	static int32_t e1000_read_phy_reg_ex(struct e1000_hw *hw,uint32_t reg_addr,
121	uint16_t *phy_data);
122	static uint16_t e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count);
123	static int32_t e1000_acquire_eeprom(struct e1000_hw *hw);
124	static void e1000_release_eeprom(struct e1000_hw *hw);
125	static void e1000_standby_eeprom(struct e1000_hw *hw);
126	static int32_t e1000_set_vco_speed(struct e1000_hw *hw);
127	static int32_t e1000_polarity_reversal_workaround(struct e1000_hw *hw);
128	static int32_t e1000_set_phy_mode(struct e1000_hw *hw);
129	static int32_t e1000_host_if_read_cookie(struct e1000_hw hw, uint8_t buffer);
130	static uint8_t e1000_calculate_mng_checksum(char *buffer, uint32_t length);
131	static int32_t e1000_configure_kmrn_for_10_100(struct e1000_hw *hw,
132	uint16_t duplex);
133	static int32_t e1000_configure_kmrn_for_1000(struct e1000_hw *hw);
134
135	/* IGP cable length table */
136	static const
137	uint16_t e1000_igp_cable_length_table[IGP01E1000_AGC_LENGTH_TABLE_SIZE] =
138	{ 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5,
139	5, 10, 10, 10, 10, 10, 10, 10, 20, 20, 20, 20, 20, 25, 25, 25,
140	25, 25, 25, 25, 30, 30, 30, 30, 40, 40, 40, 40, 40, 40, 40, 40,
141	40, 50, 50, 50, 50, 50, 50, 50, 60, 60, 60, 60, 60, 60, 60, 60,
142	60, 70, 70, 70, 70, 70, 70, 80, 80, 80, 80, 80, 80, 90, 90, 90,
143	90, 90, 90, 90, 90, 90, 100, 100, 100, 100, 100, 100, 100, 100, 100, 100,
144	100, 100, 100, 100, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110, 110,
145	110, 110, 110, 110, 110, 110, 120, 120, 120, 120, 120, 120, 120, 120, 120, 120};
146
147	static const
148	uint16_t e1000_igp_2_cable_length_table[IGP02E1000_AGC_LENGTH_TABLE_SIZE] =
149	{ 0, 0, 0, 0, 0, 0, 0, 0, 3, 5, 8, 11, 13, 16, 18, 21,
150	0, 0, 0, 3, 6, 10, 13, 16, 19, 23, 26, 29, 32, 35, 38, 41,
151	6, 10, 14, 18, 22, 26, 30, 33, 37, 41, 44, 48, 51, 54, 58, 61,
152	21, 26, 31, 35, 40, 44, 49, 53, 57, 61, 65, 68, 72, 75, 79, 82,
153	40, 45, 51, 56, 61, 66, 70, 75, 79, 83, 87, 91, 94, 98, 101, 104,
154	60, 66, 72, 77, 82, 87, 92, 96, 100, 104, 108, 111, 114, 117, 119, 121,
155	83, 89, 95, 100, 105, 109, 113, 116, 119, 122, 124,
156	104, 109, 114, 118, 121, 124};
157
158	/******************************************************************************
159	* Set the phy type member in the hw struct.
160	*
161	* hw - Struct containing variables accessed by shared code
162	*****************************************************************************/
163	static int32_t
164	e1000_set_phy_type(struct e1000_hw *hw)
165	{
166	DEBUGFUNC("e1000_set_phy_type");
167
168	if (hw->mac_type == e1000_undefined)
169	return -E1000_ERR_PHY_TYPE;
170
171	switch (hw->phy_id) {
172	case M88E1000_E_PHY_ID:
173	case M88E1000_I_PHY_ID:
174	case M88E1011_I_PHY_ID:
175	case M88E1111_I_PHY_ID:
176	hw->phy_type = e1000_phy_m88;
177	break;
178	case IGP01E1000_I_PHY_ID:
179	if (hw->mac_type == e1000_82541 \|\|
180	hw->mac_type == e1000_82541_rev_2 \|\|
181	hw->mac_type == e1000_82547 \|\|
182	hw->mac_type == e1000_82547_rev_2) {
183	hw->phy_type = e1000_phy_igp;
184	break;
185	}
186	case IGP03E1000_E_PHY_ID:
187	hw->phy_type = e1000_phy_igp_3;
188	break;
189	case IFE_E_PHY_ID:
190	case IFE_PLUS_E_PHY_ID:
191	case IFE_C_E_PHY_ID:
192	hw->phy_type = e1000_phy_ife;
193	break;
194	case GG82563_E_PHY_ID:
195	if (hw->mac_type == e1000_80003es2lan) {
196	hw->phy_type = e1000_phy_gg82563;
197	break;
198	}
199	/* Fall Through */
200	default:
201	/* Should never have loaded on this device */
202	hw->phy_type = e1000_phy_undefined;
203	return -E1000_ERR_PHY_TYPE;
204	}
205
206	return E1000_SUCCESS;
207	}
208
209	/******************************************************************************
210	* IGP phy init script - initializes the GbE PHY
211	*
212	* hw - Struct containing variables accessed by shared code
213	*****************************************************************************/
214	static void
215	e1000_phy_init_script(struct e1000_hw *hw)
216	{
217	uint32_t ret_val;
218	uint16_t phy_saved_data;
219
220	DEBUGFUNC("e1000_phy_init_script");
221
222	if (hw->phy_init_script) {
223	msleep(20);
224
225	/* Save off the current value of register 0x2F5B to be restored at
226	* the end of this routine. */
227	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
228
229	/* Disabled the PHY transmitter */
230	e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
231
232	msleep(20);
233
234	e1000_write_phy_reg(hw,0x0000,0x0140);
235
236	msleep(5);
237
238	switch (hw->mac_type) {
239	case e1000_82541:
240	case e1000_82547:
241	e1000_write_phy_reg(hw, 0x1F95, 0x0001);
242
243	e1000_write_phy_reg(hw, 0x1F71, 0xBD21);
244
245	e1000_write_phy_reg(hw, 0x1F79, 0x0018);
246
247	e1000_write_phy_reg(hw, 0x1F30, 0x1600);
248
249	e1000_write_phy_reg(hw, 0x1F31, 0x0014);
250
251	e1000_write_phy_reg(hw, 0x1F32, 0x161C);
252
253	e1000_write_phy_reg(hw, 0x1F94, 0x0003);
254
255	e1000_write_phy_reg(hw, 0x1F96, 0x003F);
256
257	e1000_write_phy_reg(hw, 0x2010, 0x0008);
258	break;
259
260	case e1000_82541_rev_2:
261	case e1000_82547_rev_2:
262	e1000_write_phy_reg(hw, 0x1F73, 0x0099);
263	break;
264	default:
265	break;
266	}
267
268	e1000_write_phy_reg(hw, 0x0000, 0x3300);
269
270	msleep(20);
271
272	/* Now enable the transmitter */
273	e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
274
275	if (hw->mac_type == e1000_82547) {
276	uint16_t fused, fine, coarse;
277
278	/* Move to analog registers page */
279	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_SPARE_FUSE_STATUS, &fused);
280
281	if (!(fused & IGP01E1000_ANALOG_SPARE_FUSE_ENABLED)) {
282	e1000_read_phy_reg(hw, IGP01E1000_ANALOG_FUSE_STATUS, &fused);
283
284	fine = fused & IGP01E1000_ANALOG_FUSE_FINE_MASK;
285	coarse = fused & IGP01E1000_ANALOG_FUSE_COARSE_MASK;
286
287	if (coarse > IGP01E1000_ANALOG_FUSE_COARSE_THRESH) {
288	coarse -= IGP01E1000_ANALOG_FUSE_COARSE_10;
289	fine -= IGP01E1000_ANALOG_FUSE_FINE_1;
290	} else if (coarse == IGP01E1000_ANALOG_FUSE_COARSE_THRESH)
291	fine -= IGP01E1000_ANALOG_FUSE_FINE_10;
292
293	fused = (fused & IGP01E1000_ANALOG_FUSE_POLY_MASK) \|
294	(fine & IGP01E1000_ANALOG_FUSE_FINE_MASK) \|
295	(coarse & IGP01E1000_ANALOG_FUSE_COARSE_MASK);
296
297	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_CONTROL, fused);
298	e1000_write_phy_reg(hw, IGP01E1000_ANALOG_FUSE_BYPASS,
299	IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL);
300	}
301	}
302	}
303	}
304
305	/******************************************************************************
306	* Set the mac type member in the hw struct.
307	*
308	* hw - Struct containing variables accessed by shared code
309	*****************************************************************************/
310	int32_t
311	e1000_set_mac_type(struct e1000_hw *hw)
312	{
313	DEBUGFUNC("e1000_set_mac_type");
314
315	switch (hw->device_id) {
316	case E1000_DEV_ID_82542:
317	switch (hw->revision_id) {
318	case E1000_82542_2_0_REV_ID:
319	hw->mac_type = e1000_82542_rev2_0;
320	break;
321	case E1000_82542_2_1_REV_ID:
322	hw->mac_type = e1000_82542_rev2_1;
323	break;
324	default:
325	/* Invalid 82542 revision ID */
326	return -E1000_ERR_MAC_TYPE;
327	}
328	break;
329	case E1000_DEV_ID_82543GC_FIBER:
330	case E1000_DEV_ID_82543GC_COPPER:
331	hw->mac_type = e1000_82543;
332	break;
333	case E1000_DEV_ID_82544EI_COPPER:
334	case E1000_DEV_ID_82544EI_FIBER:
335	case E1000_DEV_ID_82544GC_COPPER:
336	case E1000_DEV_ID_82544GC_LOM:
337	hw->mac_type = e1000_82544;
338	break;
339	case E1000_DEV_ID_82540EM:
340	case E1000_DEV_ID_82540EM_LOM:
341	case E1000_DEV_ID_82540EP:
342	case E1000_DEV_ID_82540EP_LOM:
343	case E1000_DEV_ID_82540EP_LP:
344	hw->mac_type = e1000_82540;
345	break;
346	case E1000_DEV_ID_82545EM_COPPER:
347	case E1000_DEV_ID_82545EM_FIBER:
348	hw->mac_type = e1000_82545;
349	break;
350	case E1000_DEV_ID_82545GM_COPPER:
351	case E1000_DEV_ID_82545GM_FIBER:
352	case E1000_DEV_ID_82545GM_SERDES:
353	hw->mac_type = e1000_82545_rev_3;
354	break;
355	case E1000_DEV_ID_82546EB_COPPER:
356	case E1000_DEV_ID_82546EB_FIBER:
357	case E1000_DEV_ID_82546EB_QUAD_COPPER:
358	hw->mac_type = e1000_82546;
359	break;
360	case E1000_DEV_ID_82546GB_COPPER:
361	case E1000_DEV_ID_82546GB_FIBER:
362	case E1000_DEV_ID_82546GB_SERDES:
363	case E1000_DEV_ID_82546GB_PCIE:
364	case E1000_DEV_ID_82546GB_QUAD_COPPER:
365	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
366	hw->mac_type = e1000_82546_rev_3;
367	break;
368	case E1000_DEV_ID_82541EI:
369	case E1000_DEV_ID_82541EI_MOBILE:
370	case E1000_DEV_ID_82541ER_LOM:
371	hw->mac_type = e1000_82541;
372	break;
373	case E1000_DEV_ID_82541ER:
374	case E1000_DEV_ID_82541GI:
375	case E1000_DEV_ID_82541GI_LF:
376	case E1000_DEV_ID_82541GI_MOBILE:
377	hw->mac_type = e1000_82541_rev_2;
378	break;
379	case E1000_DEV_ID_82547EI:
380	case E1000_DEV_ID_82547EI_MOBILE:
381	hw->mac_type = e1000_82547;
382	break;
383	case E1000_DEV_ID_82547GI:
384	hw->mac_type = e1000_82547_rev_2;
385	break;
386	case E1000_DEV_ID_82571EB_COPPER:
387	case E1000_DEV_ID_82571EB_FIBER:
388	case E1000_DEV_ID_82571EB_SERDES:
389	case E1000_DEV_ID_82571EB_SERDES_DUAL:
390	case E1000_DEV_ID_82571EB_SERDES_QUAD:
391	case E1000_DEV_ID_82571EB_QUAD_COPPER:
392	case E1000_DEV_ID_82571EB_QUAD_FIBER:
393	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
394	hw->mac_type = e1000_82571;
395	break;
396	case E1000_DEV_ID_82572EI_COPPER:
397	case E1000_DEV_ID_82572EI_FIBER:
398	case E1000_DEV_ID_82572EI_SERDES:
399	case E1000_DEV_ID_82572EI:
400	hw->mac_type = e1000_82572;
401	break;
402	case E1000_DEV_ID_82573E:
403	case E1000_DEV_ID_82573E_IAMT:
404	case E1000_DEV_ID_82573L:
405	hw->mac_type = e1000_82573;
406	break;
407	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
408	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
409	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
410	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
411	hw->mac_type = e1000_80003es2lan;
412	break;
413	case E1000_DEV_ID_ICH8_IGP_M_AMT:
414	case E1000_DEV_ID_ICH8_IGP_AMT:
415	case E1000_DEV_ID_ICH8_IGP_C:
416	case E1000_DEV_ID_ICH8_IFE:
417	case E1000_DEV_ID_ICH8_IFE_GT:
418	case E1000_DEV_ID_ICH8_IFE_G:
419	case E1000_DEV_ID_ICH8_IGP_M:
420	hw->mac_type = e1000_ich8lan;
421	break;
422	case E1000_DEV_ID_82576:
423	hw->mac_type = e1000_82576;
424	break;
425	default:
426	/* Should never have loaded on this device */
427	return -E1000_ERR_MAC_TYPE;
428	}
429
430	switch (hw->mac_type) {
431	case e1000_ich8lan:
432	case e1000_82576:
433	hw->swfwhw_semaphore_present = TRUE;
434	hw->asf_firmware_present = TRUE;
435	break;
436	case e1000_80003es2lan:
437	hw->swfw_sync_present = TRUE;
438	/* fall through */
439	case e1000_82571:
440	case e1000_82572:
441	case e1000_82573:
442	hw->eeprom_semaphore_present = TRUE;
443	/* fall through */
444	case e1000_82541:
445	case e1000_82547:
446	case e1000_82541_rev_2:
447	case e1000_82547_rev_2:
448	hw->asf_firmware_present = TRUE;
449	break;
450	default:
451	break;
452	}
453
454	/* The 82543 chip does not count tx_carrier_errors properly in
455	* FD mode
456	*/
457	if (hw->mac_type == e1000_82543)
458	hw->bad_tx_carr_stats_fd = TRUE;
459
460	/* capable of receiving management packets to the host */
461	if (hw->mac_type >= e1000_82571)
462	hw->has_manc2h = TRUE;
463
464	/* In rare occasions, ESB2 systems would end up started without
465	* the RX unit being turned on.
466	*/
467	if (hw->mac_type == e1000_80003es2lan)
468	hw->rx_needs_kicking = TRUE;
469
470	if (hw->mac_type > e1000_82544)
471	hw->has_smbus = TRUE;
472
473	return E1000_SUCCESS;
474	}
475
476	/*****************************************************************************
477	* Set media type and TBI compatibility.
478	*
479	* hw - Struct containing variables accessed by shared code
480	* **************************************************************************/
481	void
482	e1000_set_media_type(struct e1000_hw *hw)
483	{
484	uint32_t status;
485
486	DEBUGFUNC("e1000_set_media_type");
487
488	if (hw->mac_type != e1000_82543) {
489	/* tbi_compatibility is only valid on 82543 */
490	hw->tbi_compatibility_en = FALSE;
491	}
492
493	switch (hw->device_id) {
494	case E1000_DEV_ID_82545GM_SERDES:
495	case E1000_DEV_ID_82546GB_SERDES:
496	case E1000_DEV_ID_82571EB_SERDES:
497	case E1000_DEV_ID_82571EB_SERDES_DUAL:
498	case E1000_DEV_ID_82571EB_SERDES_QUAD:
499	case E1000_DEV_ID_82572EI_SERDES:
500	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
501	hw->media_type = e1000_media_type_internal_serdes;
502	break;
503	default:
504	switch (hw->mac_type) {
505	case e1000_82542_rev2_0:
506	case e1000_82542_rev2_1:
507	hw->media_type = e1000_media_type_fiber;
508	break;
509	case e1000_ich8lan:
510	case e1000_82573:
511	case e1000_82576:
512	/* The STATUS_TBIMODE bit is reserved or reused for the this
513	* device.
514	*/
515	hw->media_type = e1000_media_type_copper;
516	break;
517	default:
518	status = E1000_READ_REG(hw, STATUS);
519	if (status & E1000_STATUS_TBIMODE) {
520	hw->media_type = e1000_media_type_fiber;
521	/* tbi_compatibility not valid on fiber */
522	hw->tbi_compatibility_en = FALSE;
523	} else {
524	hw->media_type = e1000_media_type_copper;
525	}
526	break;
527	}
528	}
529	}
530
531	/******************************************************************************
532	* Reset the transmit and receive units; mask and clear all interrupts.
533	*
534	* hw - Struct containing variables accessed by shared code
535	*****************************************************************************/
536	int32_t
537	e1000_reset_hw(struct e1000_hw *hw)
538	{
539	uint32_t ctrl;
540	uint32_t ctrl_ext;
541	uint32_t icr;
542	uint32_t manc;
543	uint32_t led_ctrl;
544	uint32_t timeout;
545	uint32_t extcnf_ctrl;
546	int32_t ret_val;
547
548	DEBUGFUNC("e1000_reset_hw");
549
550	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
551	if (hw->mac_type == e1000_82542_rev2_0) {
552	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
553	e1000_pci_clear_mwi(hw);
554	}
555
556	if (hw->bus_type == e1000_bus_type_pci_express) {
557	/* Prevent the PCI-E bus from sticking if there is no TLP connection
558	* on the last TLP read/write transaction when MAC is reset.
559	*/
560	if (e1000_disable_pciex_master(hw) != E1000_SUCCESS) {
561	DEBUGOUT("PCI-E Master disable polling has failed.\n");
562	}
563	}
564
565	/* Clear interrupt mask to stop board from generating interrupts */
566	DEBUGOUT("Masking off all interrupts\n");
567	E1000_WRITE_REG(hw, IMC, 0xffffffff);
568
569	/* Disable the Transmit and Receive units. Then delay to allow
570	* any pending transactions to complete before we hit the MAC with
571	* the global reset.
572	*/
573	E1000_WRITE_REG(hw, RCTL, 0);
574	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
575	E1000_WRITE_FLUSH(hw);
576
577	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
578	hw->tbi_compatibility_on = FALSE;
579
580	/* Delay to allow any outstanding PCI transactions to complete before
581	* resetting the device
582	*/
583	msleep(10);
584
585	ctrl = E1000_READ_REG(hw, CTRL);
586
587	/* Must reset the PHY before resetting the MAC */
588	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
589	E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_PHY_RST));
590	msleep(5);
591	}
592
593	/* Must acquire the MDIO ownership before MAC reset.
594	* Ownership defaults to firmware after a reset. */
595	if (hw->mac_type == e1000_82573) {
596	timeout = 10;
597
598	extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
599	extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
600
601	do {
602	E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
603	extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
604
605	if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
606	break;
607	else
608	extcnf_ctrl \|= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
609
610	msleep(2);
611	timeout--;
612	} while (timeout);
613	}
614
615	/* Workaround for ICH8 bit corruption issue in FIFO memory */
616	if (hw->mac_type == e1000_ich8lan) {
617	/* Set Tx and Rx buffer allocation to 8k apiece. */
618	E1000_WRITE_REG(hw, PBA, E1000_PBA_8K);
619	/* Set Packet Buffer Size to 16k. */
620	E1000_WRITE_REG(hw, PBS, E1000_PBS_16K);
621	}
622
623	/* Issue a global reset to the MAC. This will reset the chip's
624	* transmit, receive, DMA, and link units. It will not effect
625	* the current PCI configuration. The global reset bit is self-
626	* clearing, and should clear within a microsecond.
627	*/
628	DEBUGOUT("Issuing a global reset to MAC\n");
629
630	switch (hw->mac_type) {
631	case e1000_82544:
632	case e1000_82540:
633	case e1000_82545:
634	case e1000_82546:
635	case e1000_82541:
636	case e1000_82541_rev_2:
637	/* These controllers can't ack the 64-bit write when issuing the
638	* reset, so use IO-mapping as a workaround to issue the reset */
639	E1000_WRITE_REG_IO(hw, CTRL, (ctrl \| E1000_CTRL_RST));
640	break;
641	case e1000_82545_rev_3:
642	case e1000_82546_rev_3:
643	/* Reset is performed on a shadow of the control register */
644	E1000_WRITE_REG(hw, CTRL_DUP, (ctrl \| E1000_CTRL_RST));
645	break;
646	case e1000_ich8lan:
647	if (!hw->phy_reset_disable &&
648	e1000_check_phy_reset_block(hw) == E1000_SUCCESS) {
649	/* e1000_ich8lan PHY HW reset requires MAC CORE reset
650	* at the same time to make sure the interface between
651	* MAC and the external PHY is reset.
652	*/
653	ctrl \|= E1000_CTRL_PHY_RST;
654	}
655
656	e1000_get_software_flag(hw);
657	E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_RST));
658	msleep(5);
659	break;
660	default:
661	E1000_WRITE_REG(hw, CTRL, (ctrl \| E1000_CTRL_RST));
662	break;
663	}
664
665	/* After MAC reset, force reload of EEPROM to restore power-on settings to
666	* device. Later controllers reload the EEPROM automatically, so just wait
667	* for reload to complete.
668	*/
669	switch (hw->mac_type) {
670	case e1000_82542_rev2_0:
671	case e1000_82542_rev2_1:
672	case e1000_82543:
673	case e1000_82544:
674	/* Wait for reset to complete */
675	udelay(10);
676	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
677	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
678	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
679	E1000_WRITE_FLUSH(hw);
680	/* Wait for EEPROM reload */
681	msleep(2);
682	break;
683	case e1000_82541:
684	case e1000_82541_rev_2:
685	case e1000_82547:
686	case e1000_82547_rev_2:
687	/* Wait for EEPROM reload */
688	msleep(20);
689	break;
690	case e1000_82573:
691	if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
692	udelay(10);
693	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
694	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
695	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
696	E1000_WRITE_FLUSH(hw);
697	}
698	/* fall through */
699	default:
700	/* Auto read done will delay 5ms or poll based on mac type */
701	ret_val = e1000_get_auto_rd_done(hw);
702	if (ret_val)
703	return ret_val;
704	break;
705	}
706
707	/* Disable HW ARPs on ASF enabled adapters */
708	if (hw->mac_type >= e1000_82540 && hw->mac_type <= e1000_82547_rev_2) {
709	manc = E1000_READ_REG(hw, MANC);
710	manc &= ~(E1000_MANC_ARP_EN);
711	E1000_WRITE_REG(hw, MANC, manc);
712	}
713
714	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
715	e1000_phy_init_script(hw);
716
717	/* Configure activity LED after PHY reset */
718	led_ctrl = E1000_READ_REG(hw, LEDCTL);
719	led_ctrl &= IGP_ACTIVITY_LED_MASK;
720	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
721	E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
722	}
723
724	/* Clear interrupt mask to stop board from generating interrupts */
725	DEBUGOUT("Masking off all interrupts\n");
726	E1000_WRITE_REG(hw, IMC, 0xffffffff);
727
728	/* Clear any pending interrupt events. */
729	icr = E1000_READ_REG(hw, ICR);
730
731	if (hw->mac_type == e1000_82571 && hw->laa_is_present == TRUE) {
732	/*
733	* Hold a copy of the LAA in RAR[14] This is done so that
734	* between the time RAR[0] gets clobbered and the time it
735	* gets fixed, the actual LAA is in one of the RARs and no
736	* incoming packets directed to this port are dropped.
737	* Eventually the LAA will be in RAR[0] and RAR[14].
738	*/
739	e1000_rar_set(hw, hw->mac_addr, E1000_RAR_ENTRIES - 1);
740	}
741
742	/* If MWI was previously enabled, reenable it. */
743	if (hw->mac_type == e1000_82542_rev2_0) {
744	if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
745	e1000_pci_set_mwi(hw);
746	}
747
748	if (hw->mac_type == e1000_ich8lan) {
749	uint32_t kab = E1000_READ_REG(hw, KABGTXD);
750	kab \|= E1000_KABGTXD_BGSQLBIAS;
751	E1000_WRITE_REG(hw, KABGTXD, kab);
752	}
753
754	return E1000_SUCCESS;
755	}
756
757	/******************************************************************************
758	*
759	* Initialize a number of hardware-dependent bits
760	*
761	* hw: Struct containing variables accessed by shared code
762	*
763	* This function contains hardware limitation workarounds for PCI-E adapters
764	*
765	*****************************************************************************/
766	static void
767	e1000_initialize_hardware_bits(struct e1000_hw *hw)
768	{
769	if ((hw->mac_type >= e1000_82571 && hw->mac_type < e1000_82576) &&
770	(!hw->initialize_hw_bits_disable)) {
771	/* Settings common to all PCI-express silicon */
772	uint32_t reg_ctrl, reg_ctrl_ext;
773	uint32_t reg_tarc0, reg_tarc1;
774	uint32_t reg_tctl;
775	uint32_t reg_txdctl, reg_txdctl1;
776
777	/* link autonegotiation/sync workarounds */
778	reg_tarc0 = E1000_READ_REG(hw, TARC0);
779	reg_tarc0 &= ~((1 << 30)\|(1 << 29)\|(1 << 28)\|(1 << 27));
780
781	/* Enable not-done TX descriptor counting */
782	reg_txdctl = E1000_READ_REG(hw, TXDCTL);
783	reg_txdctl \|= E1000_TXDCTL_COUNT_DESC;
784	E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);
785	reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
786	reg_txdctl1 \|= E1000_TXDCTL_COUNT_DESC;
787	E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
788
789	switch (hw->mac_type) {
790	case e1000_82571:
791	case e1000_82572:
792	/* Clear PHY TX compatible mode bits */
793	reg_tarc1 = E1000_READ_REG(hw, TARC1);
794	reg_tarc1 &= ~((1 << 30)\|(1 << 29));
795
796	/* link autonegotiation/sync workarounds */
797	reg_tarc0 \|= ((1 << 26)\|(1 << 25)\|(1 << 24)\|(1 << 23));
798
799	/* TX ring control fixes */
800	reg_tarc1 \|= ((1 << 26)\|(1 << 25)\|(1 << 24));
801
802	/* Multiple read bit is reversed polarity */
803	reg_tctl = E1000_READ_REG(hw, TCTL);
804	if (reg_tctl & E1000_TCTL_MULR)
805	reg_tarc1 &= ~(1 << 28);
806	else
807	reg_tarc1 \|= (1 << 28);
808
809	E1000_WRITE_REG(hw, TARC1, reg_tarc1);
810	break;
811	case e1000_82573:
812	reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
813	reg_ctrl_ext &= ~(1 << 23);
814	reg_ctrl_ext \|= (1 << 22);
815
816	/* TX byte count fix */
817	reg_ctrl = E1000_READ_REG(hw, CTRL);
818	reg_ctrl &= ~(1 << 29);
819
820	E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
821	E1000_WRITE_REG(hw, CTRL, reg_ctrl);
822	break;
823	case e1000_80003es2lan:
824	/* improve small packet performace for fiber/serdes */
825	if ((hw->media_type == e1000_media_type_fiber) \|\|
826	(hw->media_type == e1000_media_type_internal_serdes)) {
827	reg_tarc0 &= ~(1 << 20);
828	}
829
830	/* Multiple read bit is reversed polarity */
831	reg_tctl = E1000_READ_REG(hw, TCTL);
832	reg_tarc1 = E1000_READ_REG(hw, TARC1);
833	if (reg_tctl & E1000_TCTL_MULR)
834	reg_tarc1 &= ~(1 << 28);
835	else
836	reg_tarc1 \|= (1 << 28);
837
838	E1000_WRITE_REG(hw, TARC1, reg_tarc1);
839	break;
840	case e1000_ich8lan:
841	/* Reduce concurrent DMA requests to 3 from 4 */
842	if ((hw->revision_id < 3) \|\|
843	((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
844	(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
845	reg_tarc0 \|= ((1 << 29)\|(1 << 28));
846
847	reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
848	reg_ctrl_ext \|= (1 << 22);
849	E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
850
851	/* workaround TX hang with TSO=on */
852	reg_tarc0 \|= ((1 << 27)\|(1 << 26)\|(1 << 24)\|(1 << 23));
853
854	/* Multiple read bit is reversed polarity */
855	reg_tctl = E1000_READ_REG(hw, TCTL);
856	reg_tarc1 = E1000_READ_REG(hw, TARC1);
857	if (reg_tctl & E1000_TCTL_MULR)
858	reg_tarc1 &= ~(1 << 28);
859	else
860	reg_tarc1 \|= (1 << 28);
861
862	/* workaround TX hang with TSO=on */
863	reg_tarc1 \|= ((1 << 30)\|(1 << 26)\|(1 << 24));
864
865	E1000_WRITE_REG(hw, TARC1, reg_tarc1);
866	break;
867	default:
868	break;
869	}
870
871	E1000_WRITE_REG(hw, TARC0, reg_tarc0);
872	}
873	}
874
875	/******************************************************************************
876	* Performs basic configuration of the adapter.
877	*
878	* hw - Struct containing variables accessed by shared code
879	*
880	* Assumes that the controller has previously been reset and is in a
881	* post-reset uninitialized state. Initializes the receive address registers,
882	* multicast table, and VLAN filter table. Calls routines to setup link
883	* configuration and flow control settings. Clears all on-chip counters. Leaves
884	* the transmit and receive units disabled and uninitialized.
885	*****************************************************************************/
886	int32_t
887	e1000_init_hw(struct e1000_hw *hw)
888	{
889	uint32_t ctrl;
890	uint32_t i;
891	int32_t ret_val;
892	uint16_t pcix_cmd_word;
893	uint16_t pcix_stat_hi_word;
894	uint16_t cmd_mmrbc;
895	uint16_t stat_mmrbc;
896	uint32_t mta_size;
897	uint32_t reg_data;
898	uint32_t ctrl_ext;
899
900	DEBUGFUNC("e1000_init_hw");
901
902	/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
903	if ((hw->mac_type == e1000_ich8lan) &&
904	((hw->revision_id < 3) \|\|
905	((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
906	(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
907	reg_data = E1000_READ_REG(hw, STATUS);
908	reg_data &= ~0x80000000;
909	E1000_WRITE_REG(hw, STATUS, reg_data);
910	}
911
912	/* Initialize Identification LED */
913	ret_val = e1000_id_led_init(hw);
914	if (ret_val) {
915	DEBUGOUT("Error Initializing Identification LED\n");
916	return ret_val;
917	}
918
919	/* Set the media type and TBI compatibility */
920	e1000_set_media_type(hw);
921
922	/* Must be called after e1000_set_media_type because media_type is used */
923	e1000_initialize_hardware_bits(hw);
924
925	/* Disabling VLAN filtering. */
926	DEBUGOUT("Initializing the IEEE VLAN\n");
927	switch (hw->mac_type) {
928	case e1000_ich8lan:
929	/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
930	break;
931	case e1000_82576:
932	/* There is no need to clear vfta on 82576 if VLANs are not used.
933	* - IntelÂ® 82576 Gigabit Ethernet Controller Datasheet r2.41
934	* Section 8.10.19 Table Array - VFTA
935	*
936	* Setting VET may also be unnecessary, however the documentation
937	* isn't specific on this point. The value used here is as advised in
938	* - IntelÂ® 82576 Gigabit Ethernet Controller Datasheet r2.41
939	* Section 8.2.7 VLAN Ether Type - VET
940	*/
941	E1000_WRITE_REG(hw, VET, ETHERNET_IEEE_VLAN_TYPE);
942	break;
943	default:
944	if (hw->mac_type < e1000_82545_rev_3)
945	E1000_WRITE_REG(hw, VET, 0);
946	e1000_clear_vfta(hw);
947	break;
948	}
949
950	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
951	if (hw->mac_type == e1000_82542_rev2_0) {
952	DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
953	e1000_pci_clear_mwi(hw);
954	E1000_WRITE_REG(hw, RCTL, E1000_RCTL_RST);
955	E1000_WRITE_FLUSH(hw);
956	msleep(5);
957	}
958
959	/* Setup the receive address. This involves initializing all of the Receive
960	* Address Registers (RARs 0 - 15).
961	*/
962	e1000_init_rx_addrs(hw);
963
964	/* For 82542 (rev 2.0), take the receiver out of reset and enable MWI */
965	if (hw->mac_type == e1000_82542_rev2_0) {
966	E1000_WRITE_REG(hw, RCTL, 0);
967	E1000_WRITE_FLUSH(hw);
968	msleep(1);
969	if (hw->pci_cmd_word & PCI_COMMAND_INVALIDATE)
970	e1000_pci_set_mwi(hw);
971	}
972
973	/* Zero out the Multicast HASH table */
974	DEBUGOUT("Zeroing the MTA\n");
975	mta_size = E1000_MC_TBL_SIZE;
976	if (hw->mac_type == e1000_ich8lan)
977	mta_size = E1000_MC_TBL_SIZE_ICH8LAN;
978	for (i = 0; i < mta_size; i++) {
979	E1000_WRITE_REG_ARRAY(hw, MTA, i, 0);
980	/* use write flush to prevent Memory Write Block (MWB) from
981	* occuring when accessing our register space */
982	E1000_WRITE_FLUSH(hw);
983	}
984
985	/* Set the PCI priority bit correctly in the CTRL register. This
986	* determines if the adapter gives priority to receives, or if it
987	* gives equal priority to transmits and receives. Valid only on
988	* 82542 and 82543 silicon.
989	*/
990	if (hw->dma_fairness && hw->mac_type <= e1000_82543) {
991	ctrl = E1000_READ_REG(hw, CTRL);
992	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PRIOR);
993	}
994
995	switch (hw->mac_type) {
996	case e1000_82545_rev_3:
997	case e1000_82546_rev_3:
998	break;
999	default:
1000	/* Workaround for PCI-X problem when BIOS sets MMRBC incorrectly. */
1001	if (hw->bus_type == e1000_bus_type_pcix) {
1002	e1000_read_pci_cfg(hw, PCIX_COMMAND_REGISTER, &pcix_cmd_word);
1003	e1000_read_pci_cfg(hw, PCIX_STATUS_REGISTER_HI,
1004	&pcix_stat_hi_word);
1005	cmd_mmrbc = (pcix_cmd_word & PCIX_COMMAND_MMRBC_MASK) >>
1006	PCIX_COMMAND_MMRBC_SHIFT;
1007	stat_mmrbc = (pcix_stat_hi_word & PCIX_STATUS_HI_MMRBC_MASK) >>
1008	PCIX_STATUS_HI_MMRBC_SHIFT;
1009	if (stat_mmrbc == PCIX_STATUS_HI_MMRBC_4K)
1010	stat_mmrbc = PCIX_STATUS_HI_MMRBC_2K;
1011	if (cmd_mmrbc > stat_mmrbc) {
1012	pcix_cmd_word &= ~PCIX_COMMAND_MMRBC_MASK;
1013	pcix_cmd_word \|= stat_mmrbc << PCIX_COMMAND_MMRBC_SHIFT;
1014	e1000_write_pci_cfg(hw, PCIX_COMMAND_REGISTER,
1015	&pcix_cmd_word);
1016	}
1017	}
1018	break;
1019	}
1020
1021	/* More time needed for PHY to initialize */
1022	if (hw->mac_type == e1000_ich8lan)
1023	msleep(15);
1024
1025	/* Call a subroutine to configure the link and setup flow control. */
1026	ret_val = e1000_setup_link(hw);
1027
1028	/* Set the transmit descriptor write-back policy */
1029	if (hw->mac_type > e1000_82544) {
1030	ctrl = E1000_READ_REG(hw, TXDCTL);
1031	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
1032	E1000_WRITE_REG(hw, TXDCTL, ctrl);
1033	}
1034
1035	if (hw->mac_type == e1000_82573) {
1036	e1000_enable_tx_pkt_filtering(hw);
1037	}
1038
1039	switch (hw->mac_type) {
1040	default:
1041	break;
1042	case e1000_80003es2lan:
1043	/* Enable retransmit on late collisions */
1044	reg_data = E1000_READ_REG(hw, TCTL);
1045	reg_data \|= E1000_TCTL_RTLC;
1046	E1000_WRITE_REG(hw, TCTL, reg_data);
1047
1048	/* Configure Gigabit Carry Extend Padding */
1049	reg_data = E1000_READ_REG(hw, TCTL_EXT);
1050	reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
1051	reg_data \|= DEFAULT_80003ES2LAN_TCTL_EXT_GCEX;
1052	E1000_WRITE_REG(hw, TCTL_EXT, reg_data);
1053
1054	/* Configure Transmit Inter-Packet Gap */
1055	reg_data = E1000_READ_REG(hw, TIPG);
1056	reg_data &= ~E1000_TIPG_IPGT_MASK;
1057	reg_data \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
1058	E1000_WRITE_REG(hw, TIPG, reg_data);
1059
1060	reg_data = E1000_READ_REG_ARRAY(hw, FFLT, 0x0001);
1061	reg_data &= ~0x00100000;
1062	E1000_WRITE_REG_ARRAY(hw, FFLT, 0x0001, reg_data);
1063	/* Fall through */
1064	case e1000_82571:
1065	case e1000_82572:
1066	case e1000_ich8lan:
1067	ctrl = E1000_READ_REG(hw, TXDCTL1);
1068	ctrl = (ctrl & ~E1000_TXDCTL_WTHRESH) \| E1000_TXDCTL_FULL_TX_DESC_WB;
1069	E1000_WRITE_REG(hw, TXDCTL1, ctrl);
1070	break;
1071	}
1072
1073
1074	if (hw->mac_type == e1000_82573) {
1075	uint32_t gcr = E1000_READ_REG(hw, GCR);
1076	gcr \|= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1077	E1000_WRITE_REG(hw, GCR, gcr);
1078	}
1079
1080	/* Clear all of the statistics registers (clear on read). It is
1081	* important that we do this after we have tried to establish link
1082	* because the symbol error count will increment wildly if there
1083	* is no link.
1084	*/
1085	e1000_clear_hw_cntrs(hw);
1086
1087	/* ICH8 No-snoop bits are opposite polarity.
1088	* Set to snoop by default after reset. */
1089	if (hw->mac_type == e1000_ich8lan)
1090	e1000_set_pci_ex_no_snoop(hw, PCI_EX_82566_SNOOP_ALL);
1091
1092	if (hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER \|\|
1093	hw->device_id == E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3) {
1094	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
1095	/* Relaxed ordering must be disabled to avoid a parity
1096	* error crash in a PCI slot. */
1097	ctrl_ext \|= E1000_CTRL_EXT_RO_DIS;
1098	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1099	}
1100
1101	return ret_val;
1102	}
1103
1104	/******************************************************************************
1105	* Adjust SERDES output amplitude based on EEPROM setting.
1106	*
1107	* hw - Struct containing variables accessed by shared code.
1108	*****************************************************************************/
1109	static int32_t
1110	e1000_adjust_serdes_amplitude(struct e1000_hw *hw)
1111	{
1112	uint16_t eeprom_data;
1113	int32_t ret_val;
1114
1115	DEBUGFUNC("e1000_adjust_serdes_amplitude");
1116
1117	if (hw->media_type != e1000_media_type_internal_serdes)
1118	return E1000_SUCCESS;
1119
1120	switch (hw->mac_type) {
1121	case e1000_82545_rev_3:
1122	case e1000_82546_rev_3:
1123	break;
1124	default:
1125	return E1000_SUCCESS;
1126	}
1127
1128	ret_val = e1000_read_eeprom(hw, EEPROM_SERDES_AMPLITUDE, 1, &eeprom_data);
1129	if (ret_val) {
1130	return ret_val;
1131	}
1132
1133	if (eeprom_data != EEPROM_RESERVED_WORD) {
1134	/* Adjust SERDES output amplitude only. */
1135	eeprom_data &= EEPROM_SERDES_AMPLITUDE_MASK;
1136	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_EXT_CTRL, eeprom_data);
1137	if (ret_val)
1138	return ret_val;
1139	}
1140
1141	return E1000_SUCCESS;
1142	}
1143
1144	/******************************************************************************
1145	* Configures flow control and link settings.
1146	*
1147	* hw - Struct containing variables accessed by shared code
1148	*
1149	* Determines which flow control settings to use. Calls the apropriate media-
1150	* specific link configuration function. Configures the flow control settings.
1151	* Assuming the adapter has a valid link partner, a valid link should be
1152	* established. Assumes the hardware has previously been reset and the
1153	* transmitter and receiver are not enabled.
1154	*****************************************************************************/
1155	int32_t
1156	e1000_setup_link(struct e1000_hw *hw)
1157	{
1158	uint32_t ctrl_ext;
1159	int32_t ret_val;
1160	uint16_t eeprom_data;
1161
1162	DEBUGFUNC("e1000_setup_link");
1163
1164	/* In the case of the phy reset being blocked, we already have a link.
1165	* We do not have to set it up again. */
1166	if (e1000_check_phy_reset_block(hw))
1167	return E1000_SUCCESS;
1168
1169	/* Read and store word 0x0F of the EEPROM. This word contains bits
1170	* that determine the hardware's default PAUSE (flow control) mode,
1171	* a bit that determines whether the HW defaults to enabling or
1172	* disabling auto-negotiation, and the direction of the
1173	* SW defined pins. If there is no SW over-ride of the flow
1174	* control setting, then the variable hw->fc will
1175	* be initialized based on a value in the EEPROM.
1176	*/
1177	if (hw->fc == E1000_FC_DEFAULT) {
1178	switch (hw->mac_type) {
1179	case e1000_ich8lan:
1180	case e1000_82573:
1181	hw->fc = E1000_FC_FULL;
1182	break;
1183	default:
1184	ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1185	1, &eeprom_data);
1186	if (ret_val) {
1187	DEBUGOUT("EEPROM Read Error\n");
1188	return -E1000_ERR_EEPROM;
1189	}
1190	if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) == 0)
1191	hw->fc = E1000_FC_NONE;
1192	else if ((eeprom_data & EEPROM_WORD0F_PAUSE_MASK) ==
1193	EEPROM_WORD0F_ASM_DIR)
1194	hw->fc = E1000_FC_TX_PAUSE;
1195	else
1196	hw->fc = E1000_FC_FULL;
1197	break;
1198	}
1199	}
1200
1201	/* We want to save off the original Flow Control configuration just
1202	* in case we get disconnected and then reconnected into a different
1203	* hub or switch with different Flow Control capabilities.
1204	*/
1205	if (hw->mac_type == e1000_82542_rev2_0)
1206	hw->fc &= (~E1000_FC_TX_PAUSE);
1207
1208	if ((hw->mac_type < e1000_82543) && (hw->report_tx_early == 1))
1209	hw->fc &= (~E1000_FC_RX_PAUSE);
1210
1211	hw->original_fc = hw->fc;
1212
1213	DEBUGOUT1("After fix-ups FlowControl is now = %x\n", hw->fc);
1214
1215	/* Take the 4 bits from EEPROM word 0x0F that determine the initial
1216	* polarity value for the SW controlled pins, and setup the
1217	* Extended Device Control reg with that info.
1218	* This is needed because one of the SW controlled pins is used for
1219	* signal detection. So this should be done before e1000_setup_pcs_link()
1220	* or e1000_phy_setup() is called.
1221	*/
1222	if (hw->mac_type == e1000_82543) {
1223	ret_val = e1000_read_eeprom(hw, EEPROM_INIT_CONTROL2_REG,
1224	1, &eeprom_data);
1225	if (ret_val) {
1226	DEBUGOUT("EEPROM Read Error\n");
1227	return -E1000_ERR_EEPROM;
1228	}
1229	ctrl_ext = ((eeprom_data & EEPROM_WORD0F_SWPDIO_EXT) <<
1230	SWDPIO__EXT_SHIFT);
1231	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
1232	}
1233
1234	/* Call the necessary subroutine to configure the link. */
1235	ret_val = (hw->media_type == e1000_media_type_copper) ?
1236	e1000_setup_copper_link(hw) :
1237	e1000_setup_fiber_serdes_link(hw);
1238
1239	/* Initialize the flow control address, type, and PAUSE timer
1240	* registers to their default values. This is done even if flow
1241	* control is disabled, because it does not hurt anything to
1242	* initialize these registers.
1243	*/
1244	DEBUGOUT("Initializing the Flow Control address, type and timer regs\n");
1245
1246	/* FCAL/H and FCT are hardcoded to standard values in e1000_ich8lan. */
1247	if (hw->mac_type != e1000_ich8lan) {
1248	E1000_WRITE_REG(hw, FCT, FLOW_CONTROL_TYPE);
1249	E1000_WRITE_REG(hw, FCAH, FLOW_CONTROL_ADDRESS_HIGH);
1250	E1000_WRITE_REG(hw, FCAL, FLOW_CONTROL_ADDRESS_LOW);
1251	}
1252
1253	E1000_WRITE_REG(hw, FCTTV, hw->fc_pause_time);
1254
1255	/* Set the flow control receive threshold registers. Normally,
1256	* these registers will be set to a default threshold that may be
1257	* adjusted later by the driver's runtime code. However, if the
1258	* ability to transmit pause frames in not enabled, then these
1259	* registers will be set to 0.
1260	*/
1261	if (!(hw->fc & E1000_FC_TX_PAUSE)) {
1262	E1000_WRITE_REG(hw, FCRTL, 0);
1263	E1000_WRITE_REG(hw, FCRTH, 0);
1264	} else {
1265	/* We need to set up the Receive Threshold high and low water marks
1266	* as well as (optionally) enabling the transmission of XON frames.
1267	*/
1268	if (hw->fc_send_xon) {
1269	E1000_WRITE_REG(hw, FCRTL, (hw->fc_low_water \| E1000_FCRTL_XONE));
1270	E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1271	} else {
1272	E1000_WRITE_REG(hw, FCRTL, hw->fc_low_water);
1273	E1000_WRITE_REG(hw, FCRTH, hw->fc_high_water);
1274	}
1275	}
1276	return ret_val;
1277	}
1278
1279	/******************************************************************************
1280	* Sets up link for a fiber based or serdes based adapter
1281	*
1282	* hw - Struct containing variables accessed by shared code
1283	*
1284	* Manipulates Physical Coding Sublayer functions in order to configure
1285	* link. Assumes the hardware has been previously reset and the transmitter
1286	* and receiver are not enabled.
1287	*****************************************************************************/
1288	static int32_t
1289	e1000_setup_fiber_serdes_link(struct e1000_hw *hw)
1290	{
1291	uint32_t ctrl;
1292	uint32_t status;
1293	uint32_t txcw = 0;
1294	uint32_t i;
1295	uint32_t signal = 0;
1296	int32_t ret_val;
1297
1298	DEBUGFUNC("e1000_setup_fiber_serdes_link");
1299
1300	/* On 82571 and 82572 Fiber connections, SerDes loopback mode persists
1301	* until explicitly turned off or a power cycle is performed. A read to
1302	* the register does not indicate its status. Therefore, we ensure
1303	* loopback mode is disabled during initialization.
1304	*/
1305	if (hw->mac_type == e1000_82571 \|\| hw->mac_type == e1000_82572)
1306	E1000_WRITE_REG(hw, SCTL, E1000_DISABLE_SERDES_LOOPBACK);
1307
1308	/* On adapters with a MAC newer than 82544, SWDP 1 will be
1309	* set when the optics detect a signal. On older adapters, it will be
1310	* cleared when there is a signal. This applies to fiber media only.
1311	* If we're on serdes media, adjust the output amplitude to value
1312	* set in the EEPROM.
1313	*/
1314	ctrl = E1000_READ_REG(hw, CTRL);
1315	if (hw->media_type == e1000_media_type_fiber)
1316	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
1317
1318	ret_val = e1000_adjust_serdes_amplitude(hw);
1319	if (ret_val)
1320	return ret_val;
1321
1322	/* Take the link out of reset */
1323	ctrl &= ~(E1000_CTRL_LRST);
1324
1325	/* Adjust VCO speed to improve BER performance */
1326	ret_val = e1000_set_vco_speed(hw);
1327	if (ret_val)
1328	return ret_val;
1329
1330	e1000_config_collision_dist(hw);
1331
1332	/* Check for a software override of the flow control settings, and setup
1333	* the device accordingly. If auto-negotiation is enabled, then software
1334	* will have to set the "PAUSE" bits to the correct value in the Tranmsit
1335	* Config Word Register (TXCW) and re-start auto-negotiation. However, if
1336	* auto-negotiation is disabled, then software will have to manually
1337	* configure the two flow control enable bits in the CTRL register.
1338	*
1339	* The possible values of the "fc" parameter are:
1340	* 0: Flow control is completely disabled
1341	* 1: Rx flow control is enabled (we can receive pause frames, but
1342	* not send pause frames).
1343	* 2: Tx flow control is enabled (we can send pause frames but we do
1344	* not support receiving pause frames).
1345	* 3: Both Rx and TX flow control (symmetric) are enabled.
1346	*/
1347	switch (hw->fc) {
1348	case E1000_FC_NONE:
1349	/* Flow control is completely disabled by a software over-ride. */
1350	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD);
1351	break;
1352	case E1000_FC_RX_PAUSE:
1353	/* RX Flow control is enabled and TX Flow control is disabled by a
1354	* software over-ride. Since there really isn't a way to advertise
1355	* that we are capable of RX Pause ONLY, we will advertise that we
1356	* support both symmetric and asymmetric RX PAUSE. Later, we will
1357	* disable the adapter's ability to send PAUSE frames.
1358	*/
1359	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
1360	break;
1361	case E1000_FC_TX_PAUSE:
1362	/* TX Flow control is enabled, and RX Flow control is disabled, by a
1363	* software over-ride.
1364	*/
1365	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_ASM_DIR);
1366	break;
1367	case E1000_FC_FULL:
1368	/* Flow control (both RX and TX) is enabled by a software over-ride. */
1369	txcw = (E1000_TXCW_ANE \| E1000_TXCW_FD \| E1000_TXCW_PAUSE_MASK);
1370	break;
1371	default:
1372	DEBUGOUT("Flow control param set incorrectly\n");
1373	return -E1000_ERR_CONFIG;
1374	break;
1375	}
1376
1377	/* Since auto-negotiation is enabled, take the link out of reset (the link
1378	* will be in reset, because we previously reset the chip). This will
1379	* restart auto-negotiation. If auto-neogtiation is successful then the
1380	* link-up status bit will be set and the flow control enable bits (RFCE
1381	* and TFCE) will be set according to their negotiated value.
1382	*/
1383	DEBUGOUT("Auto-negotiation enabled\n");
1384
1385	E1000_WRITE_REG(hw, TXCW, txcw);
1386	E1000_WRITE_REG(hw, CTRL, ctrl);
1387	E1000_WRITE_FLUSH(hw);
1388
1389	hw->txcw = txcw;
1390	msleep(1);
1391
1392	/* If we have a signal (the cable is plugged in) then poll for a "Link-Up"
1393	* indication in the Device Status Register. Time-out if a link isn't
1394	* seen in 500 milliseconds seconds (Auto-negotiation should complete in
1395	* less than 500 milliseconds even if the other end is doing it in SW).
1396	* For internal serdes, we just assume a signal is present, then poll.
1397	*/
1398	if (hw->media_type == e1000_media_type_internal_serdes \|\|
1399	(E1000_READ_REG(hw, CTRL) & E1000_CTRL_SWDPIN1) == signal) {
1400	DEBUGOUT("Looking for Link\n");
1401	for (i = 0; i < (LINK_UP_TIMEOUT / 10); i++) {
1402	msleep(10);
1403	status = E1000_READ_REG(hw, STATUS);
1404	if (status & E1000_STATUS_LU) break;
1405	}
1406	if (i == (LINK_UP_TIMEOUT / 10)) {
1407	DEBUGOUT("Never got a valid link from auto-neg!!!\n");
1408	hw->autoneg_failed = 1;
1409	/* AutoNeg failed to achieve a link, so we'll call
1410	* e1000_check_for_link. This routine will force the link up if
1411	* we detect a signal. This will allow us to communicate with
1412	* non-autonegotiating link partners.
1413	*/
1414	ret_val = e1000_check_for_link(hw);
1415	if (ret_val) {
1416	DEBUGOUT("Error while checking for link\n");
1417	return ret_val;
1418	}
1419	hw->autoneg_failed = 0;
1420	} else {
1421	hw->autoneg_failed = 0;
1422	DEBUGOUT("Valid Link Found\n");
1423	}
1424	} else {
1425	DEBUGOUT("No Signal Detected\n");
1426	}
1427	return E1000_SUCCESS;
1428	}
1429
1430	/******************************************************************************
1431	* Make sure we have a valid PHY and change PHY mode before link setup.
1432	*
1433	* hw - Struct containing variables accessed by shared code
1434	******************************************************************************/
1435	static int32_t
1436	e1000_copper_link_preconfig(struct e1000_hw *hw)
1437	{
1438	uint32_t ctrl;
1439	int32_t ret_val;
1440	uint16_t phy_data;
1441
1442	DEBUGFUNC("e1000_copper_link_preconfig");
1443
1444	ctrl = E1000_READ_REG(hw, CTRL);
1445	/* With 82543, we need to force speed and duplex on the MAC equal to what
1446	* the PHY speed and duplex configuration is. In addition, we need to
1447	* perform a hardware reset on the PHY to take it out of reset.
1448	*/
1449	if (hw->mac_type > e1000_82543) {
1450	ctrl \|= E1000_CTRL_SLU;
1451	ctrl &= ~(E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
1452	E1000_WRITE_REG(hw, CTRL, ctrl);
1453	} else {
1454	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX \| E1000_CTRL_SLU);
1455	E1000_WRITE_REG(hw, CTRL, ctrl);
1456	ret_val = e1000_phy_hw_reset(hw);
1457	if (ret_val)
1458	return ret_val;
1459	}
1460
1461	/* Make sure we have a valid PHY */
1462	ret_val = e1000_detect_gig_phy(hw);
1463	if (ret_val) {
1464	DEBUGOUT("Error, did not detect valid phy.\n");
1465	return ret_val;
1466	}
1467	DEBUGOUT1("Phy ID = %#08x \n", hw->phy_id);
1468
1469	/* Set PHY to class A mode (if necessary) */
1470	ret_val = e1000_set_phy_mode(hw);
1471	if (ret_val)
1472	return ret_val;
1473
1474	if ((hw->mac_type == e1000_82545_rev_3) \|\|
1475	(hw->mac_type == e1000_82546_rev_3)) {
1476	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1477	phy_data \|= 0x00000008;
1478	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1479	}
1480
1481	if (hw->mac_type <= e1000_82543 \|\|
1482	hw->mac_type == e1000_82541 \|\| hw->mac_type == e1000_82547 \|\|
1483	hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2)
1484	hw->phy_reset_disable = FALSE;
1485
1486	return E1000_SUCCESS;
1487	}
1488
1489
1490	/********************************************************************
1491	* Copper link setup for e1000_phy_igp series.
1492	*
1493	* hw - Struct containing variables accessed by shared code
1494	*********************************************************************/
1495	static int32_t
1496	e1000_copper_link_igp_setup(struct e1000_hw *hw)
1497	{
1498	uint32_t led_ctrl;
1499	int32_t ret_val;
1500	uint16_t phy_data;
1501
1502	DEBUGFUNC("e1000_copper_link_igp_setup");
1503
1504	if (hw->phy_reset_disable)
1505	return E1000_SUCCESS;
1506
1507	ret_val = e1000_phy_reset(hw);
1508	if (ret_val) {
1509	DEBUGOUT("Error Resetting the PHY\n");
1510	return ret_val;
1511	}
1512
1513	/*
1514	* Wait 100ms for MAC to configure PHY from NVM settings, to avoid
1515	* timeout issues when LFS is enabled.
1516	*/
1517	msleep(100);
1518
1519	if (hw->mac_type != e1000_ich8lan && hw->mac_type != e1000_82576) {
1520	/* Configure activity LED after PHY reset */
1521	led_ctrl = E1000_READ_REG(hw, LEDCTL);
1522	led_ctrl &= IGP_ACTIVITY_LED_MASK;
1523	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
1524	E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
1525	}
1526
1527	/* The NVM settings will configure LPLU in D3 for IGP2 and IGP3 PHYs */
1528	if (hw->phy_type == e1000_phy_igp) {
1529	/* disable lplu d3 during driver init */
1530	ret_val = e1000_set_d3_lplu_state(hw, FALSE);
1531	if (ret_val) {
1532	DEBUGOUT("Error Disabling LPLU D3\n");
1533	return ret_val;
1534	}
1535	}
1536
1537	/* disable lplu d0 during driver init */
1538	ret_val = e1000_set_d0_lplu_state(hw, FALSE);
1539	if (ret_val) {
1540	DEBUGOUT("Error Disabling LPLU D0\n");
1541	return ret_val;
1542	}
1543	/* Configure mdi-mdix settings */
1544	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
1545	if (ret_val)
1546	return ret_val;
1547
1548	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
1549	hw->dsp_config_state = e1000_dsp_config_disabled;
1550	/* Force MDI for earlier revs of the IGP PHY */
1551	phy_data &= ~(IGP01E1000_PSCR_AUTO_MDIX \| IGP01E1000_PSCR_FORCE_MDI_MDIX);
1552	hw->mdix = 1;
1553
1554	} else {
1555	hw->dsp_config_state = e1000_dsp_config_enabled;
1556	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
1557
1558	switch (hw->mdix) {
1559	case 1:
1560	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
1561	break;
1562	case 2:
1563	phy_data \|= IGP01E1000_PSCR_FORCE_MDI_MDIX;
1564	break;
1565	case 0:
1566	default:
1567	phy_data \|= IGP01E1000_PSCR_AUTO_MDIX;
1568	break;
1569	}
1570	}
1571	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
1572	if (ret_val)
1573	return ret_val;
1574
1575	/* set auto-master slave resolution settings */
1576	if (hw->autoneg) {
1577	e1000_ms_type phy_ms_setting = hw->master_slave;
1578
1579	if (hw->ffe_config_state == e1000_ffe_config_active)
1580	hw->ffe_config_state = e1000_ffe_config_enabled;
1581
1582	if (hw->dsp_config_state == e1000_dsp_config_activated)
1583	hw->dsp_config_state = e1000_dsp_config_enabled;
1584
1585	/* when autonegotiation advertisment is only 1000Mbps then we
1586	* should disable SmartSpeed and enable Auto MasterSlave
1587	* resolution as hardware default. */
1588	if (hw->autoneg_advertised == ADVERTISE_1000_FULL) {
1589	/* Disable SmartSpeed */
1590	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1591	&phy_data);
1592	if (ret_val)
1593	return ret_val;
1594	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
1595	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
1596	phy_data);
1597	if (ret_val)
1598	return ret_val;
1599	/* Set auto Master/Slave resolution process */
1600	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1601	if (ret_val)
1602	return ret_val;
1603	phy_data &= ~CR_1000T_MS_ENABLE;
1604	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1605	if (ret_val)
1606	return ret_val;
1607	}
1608
1609	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &phy_data);
1610	if (ret_val)
1611	return ret_val;
1612
1613	/* load defaults for future use */
1614	hw->original_master_slave = (phy_data & CR_1000T_MS_ENABLE) ?
1615	((phy_data & CR_1000T_MS_VALUE) ?
1616	e1000_ms_force_master :
1617	e1000_ms_force_slave) :
1618	e1000_ms_auto;
1619
1620	switch (phy_ms_setting) {
1621	case e1000_ms_force_master:
1622	phy_data \|= (CR_1000T_MS_ENABLE \| CR_1000T_MS_VALUE);
1623	break;
1624	case e1000_ms_force_slave:
1625	phy_data \|= CR_1000T_MS_ENABLE;
1626	phy_data &= ~(CR_1000T_MS_VALUE);
1627	break;
1628	case e1000_ms_auto:
1629	phy_data &= ~CR_1000T_MS_ENABLE;
1630	default:
1631	break;
1632	}
1633	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, phy_data);
1634	if (ret_val)
1635	return ret_val;
1636	}
1637
1638	return E1000_SUCCESS;
1639	}
1640
1641	/********************************************************************
1642	* Copper link setup for e1000_phy_gg82563 series.
1643	*
1644	* hw - Struct containing variables accessed by shared code
1645	*********************************************************************/
1646	static int32_t
1647	e1000_copper_link_ggp_setup(struct e1000_hw *hw)
1648	{
1649	int32_t ret_val;
1650	uint16_t phy_data;
1651	uint32_t reg_data;
1652
1653	DEBUGFUNC("e1000_copper_link_ggp_setup");
1654
1655	if (!hw->phy_reset_disable) {
1656
1657	/* Enable CRS on TX for half-duplex operation. */
1658	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1659	&phy_data);
1660	if (ret_val)
1661	return ret_val;
1662
1663	phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
1664	/* Use 25MHz for both link down and 1000BASE-T for Tx clock */
1665	phy_data \|= GG82563_MSCR_TX_CLK_1000MBPS_25MHZ;
1666
1667	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL,
1668	phy_data);
1669	if (ret_val)
1670	return ret_val;
1671
1672	/* Options:
1673	* MDI/MDI-X = 0 (default)
1674	* 0 - Auto for all speeds
1675	* 1 - MDI mode
1676	* 2 - MDI-X mode
1677	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1678	*/
1679	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL, &phy_data);
1680	if (ret_val)
1681	return ret_val;
1682
1683	phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
1684
1685	switch (hw->mdix) {
1686	case 1:
1687	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDI;
1688	break;
1689	case 2:
1690	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_MDIX;
1691	break;
1692	case 0:
1693	default:
1694	phy_data \|= GG82563_PSCR_CROSSOVER_MODE_AUTO;
1695	break;
1696	}
1697
1698	/* Options:
1699	* disable_polarity_correction = 0 (default)
1700	* Automatic Correction for Reversed Cable Polarity
1701	* 0 - Disabled
1702	* 1 - Enabled
1703	*/
1704	phy_data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1705	if (hw->disable_polarity_correction == 1)
1706	phy_data \|= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
1707	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL, phy_data);
1708
1709	if (ret_val)
1710	return ret_val;
1711
1712	/* SW Reset the PHY so all changes take effect */
1713	ret_val = e1000_phy_reset(hw);
1714	if (ret_val) {
1715	DEBUGOUT("Error Resetting the PHY\n");
1716	return ret_val;
1717	}
1718	} /* phy_reset_disable */
1719
1720	if (hw->mac_type == e1000_80003es2lan) {
1721	/* Bypass RX and TX FIFO's */
1722	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL,
1723	E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS \|
1724	E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS);
1725	if (ret_val)
1726	return ret_val;
1727
1728	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, &phy_data);
1729	if (ret_val)
1730	return ret_val;
1731
1732	phy_data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
1733	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_SPEC_CTRL_2, phy_data);
1734
1735	if (ret_val)
1736	return ret_val;
1737
1738	reg_data = E1000_READ_REG(hw, CTRL_EXT);
1739	reg_data &= ~(E1000_CTRL_EXT_LINK_MODE_MASK);
1740	E1000_WRITE_REG(hw, CTRL_EXT, reg_data);
1741
1742	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1743	&phy_data);
1744	if (ret_val)
1745	return ret_val;
1746
1747	/* Do not init these registers when the HW is in IAMT mode, since the
1748	* firmware will have already initialized them. We only initialize
1749	* them if the HW is not in IAMT mode.
1750	*/
1751	if (e1000_check_mng_mode(hw) == FALSE) {
1752	/* Enable Electrical Idle on the PHY */
1753	phy_data \|= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
1754	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_PWR_MGMT_CTRL,
1755	phy_data);
1756	if (ret_val)
1757	return ret_val;
1758
1759	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1760	&phy_data);
1761	if (ret_val)
1762	return ret_val;
1763
1764	phy_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1765	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL,
1766	phy_data);
1767
1768	if (ret_val)
1769	return ret_val;
1770	}
1771
1772	/* Workaround: Disable padding in Kumeran interface in the MAC
1773	* and in the PHY to avoid CRC errors.
1774	*/
1775	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1776	&phy_data);
1777	if (ret_val)
1778	return ret_val;
1779	phy_data \|= GG82563_ICR_DIS_PADDING;
1780	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_INBAND_CTRL,
1781	phy_data);
1782	if (ret_val)
1783	return ret_val;
1784	}
1785
1786	return E1000_SUCCESS;
1787	}
1788
1789	/********************************************************************
1790	* Copper link setup for e1000_phy_m88 series.
1791	*
1792	* hw - Struct containing variables accessed by shared code
1793	*********************************************************************/
1794	static int32_t
1795	e1000_copper_link_mgp_setup(struct e1000_hw *hw)
1796	{
1797	int32_t ret_val;
1798	uint16_t phy_data;
1799
1800	DEBUGFUNC("e1000_copper_link_mgp_setup");
1801
1802	if (hw->phy_reset_disable)
1803	return E1000_SUCCESS;
1804
1805	/* Enable CRS on TX. This must be set for half-duplex operation. */
1806	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
1807	if (ret_val)
1808	return ret_val;
1809
1810	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
1811
1812	/* Options:
1813	* MDI/MDI-X = 0 (default)
1814	* 0 - Auto for all speeds
1815	* 1 - MDI mode
1816	* 2 - MDI-X mode
1817	* 3 - Auto for 1000Base-T only (MDI-X for 10/100Base-T modes)
1818	*/
1819	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
1820
1821	switch (hw->mdix) {
1822	case 1:
1823	phy_data \|= M88E1000_PSCR_MDI_MANUAL_MODE;
1824	break;
1825	case 2:
1826	phy_data \|= M88E1000_PSCR_MDIX_MANUAL_MODE;
1827	break;
1828	case 3:
1829	phy_data \|= M88E1000_PSCR_AUTO_X_1000T;
1830	break;
1831	case 0:
1832	default:
1833	phy_data \|= M88E1000_PSCR_AUTO_X_MODE;
1834	break;
1835	}
1836
1837	/* Options:
1838	* disable_polarity_correction = 0 (default)
1839	* Automatic Correction for Reversed Cable Polarity
1840	* 0 - Disabled
1841	* 1 - Enabled
1842	*/
1843	phy_data &= ~M88E1000_PSCR_POLARITY_REVERSAL;
1844	if (hw->disable_polarity_correction == 1)
1845	phy_data \|= M88E1000_PSCR_POLARITY_REVERSAL;
1846	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
1847	if (ret_val)
1848	return ret_val;
1849
1850	if (hw->phy_revision < M88E1011_I_REV_4) {
1851	/* Force TX_CLK in the Extended PHY Specific Control Register
1852	* to 25MHz clock.
1853	*/
1854	ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
1855	if (ret_val)
1856	return ret_val;
1857
1858	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
1859
1860	if ((hw->phy_revision == E1000_REVISION_2) &&
1861	(hw->phy_id == M88E1111_I_PHY_ID)) {
1862	/* Vidalia Phy, set the downshift counter to 5x */
1863	phy_data &= ~(M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK);
1864	phy_data \|= M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X;
1865	ret_val = e1000_write_phy_reg(hw,
1866	M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1867	if (ret_val)
1868	return ret_val;
1869	} else {
1870	/* Configure Master and Slave downshift values */
1871	phy_data &= ~(M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK \|
1872	M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK);
1873	phy_data \|= (M88E1000_EPSCR_MASTER_DOWNSHIFT_1X \|
1874	M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X);
1875	ret_val = e1000_write_phy_reg(hw,
1876	M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
1877	if (ret_val)
1878	return ret_val;
1879	}
1880	}
1881
1882	/* SW Reset the PHY so all changes take effect */
1883	ret_val = e1000_phy_reset(hw);
1884	if (ret_val) {
1885	DEBUGOUT("Error Resetting the PHY\n");
1886	return ret_val;
1887	}
1888
1889	return E1000_SUCCESS;
1890	}
1891
1892	/********************************************************************
1893	* Setup auto-negotiation and flow control advertisements,
1894	* and then perform auto-negotiation.
1895	*
1896	* hw - Struct containing variables accessed by shared code
1897	*********************************************************************/
1898	static int32_t
1899	e1000_copper_link_autoneg(struct e1000_hw *hw)
1900	{
1901	int32_t ret_val;
1902	uint16_t phy_data;
1903
1904	DEBUGFUNC("e1000_copper_link_autoneg");
1905
1906	/* Perform some bounds checking on the hw->autoneg_advertised
1907	* parameter. If this variable is zero, then set it to the default.
1908	*/
1909	hw->autoneg_advertised &= AUTONEG_ADVERTISE_SPEED_DEFAULT;
1910
1911	/* If autoneg_advertised is zero, we assume it was not defaulted
1912	* by the calling code so we set to advertise full capability.
1913	*/
1914	if (hw->autoneg_advertised == 0)
1915	hw->autoneg_advertised = AUTONEG_ADVERTISE_SPEED_DEFAULT;
1916
1917	/* IFE phy only supports 10/100 */
1918	if (hw->phy_type == e1000_phy_ife)
1919	hw->autoneg_advertised &= AUTONEG_ADVERTISE_10_100_ALL;
1920
1921	DEBUGOUT("Reconfiguring auto-neg advertisement params\n");
1922	ret_val = e1000_phy_setup_autoneg(hw);
1923	if (ret_val) {
1924	DEBUGOUT("Error Setting up Auto-Negotiation\n");
1925	return ret_val;
1926	}
1927	DEBUGOUT("Restarting Auto-Neg\n");
1928
1929	/* Restart auto-negotiation by setting the Auto Neg Enable bit and
1930	* the Auto Neg Restart bit in the PHY control register.
1931	*/
1932	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
1933	if (ret_val)
1934	return ret_val;
1935
1936	phy_data \|= (MII_CR_AUTO_NEG_EN \| MII_CR_RESTART_AUTO_NEG);
1937	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
1938	if (ret_val)
1939	return ret_val;
1940
1941	/* Does the user want to wait for Auto-Neg to complete here, or
1942	* check at a later time (for example, callback routine).
1943	*/
1944	if (hw->wait_autoneg_complete) {
1945	ret_val = e1000_wait_autoneg(hw);
1946	if (ret_val) {
1947	DEBUGOUT("Error while waiting for autoneg to complete\n");
1948	return ret_val;
1949	}
1950	}
1951
1952	hw->get_link_status = TRUE;
1953
1954	return E1000_SUCCESS;
1955	}
1956
1957	/******************************************************************************
1958	* Config the MAC and the PHY after link is up.
1959	* 1) Set up the MAC to the current PHY speed/duplex
1960	* if we are on 82543. If we
1961	* are on newer silicon, we only need to configure
1962	* collision distance in the Transmit Control Register.
1963	* 2) Set up flow control on the MAC to that established with
1964	* the link partner.
1965	* 3) Config DSP to improve Gigabit link quality for some PHY revisions.
1966	*
1967	* hw - Struct containing variables accessed by shared code
1968	******************************************************************************/
1969	static int32_t
1970	e1000_copper_link_postconfig(struct e1000_hw *hw)
1971	{
1972	int32_t ret_val;
1973	DEBUGFUNC("e1000_copper_link_postconfig");
1974
1975	if (hw->mac_type >= e1000_82544) {
1976	e1000_config_collision_dist(hw);
1977	} else {
1978	ret_val = e1000_config_mac_to_phy(hw);
1979	if (ret_val) {
1980	DEBUGOUT("Error configuring MAC to PHY settings\n");
1981	return ret_val;
1982	}
1983	}
1984	ret_val = e1000_config_fc_after_link_up(hw);
1985	if (ret_val) {
1986	DEBUGOUT("Error Configuring Flow Control\n");
1987	return ret_val;
1988	}
1989
1990	/* Config DSP to improve Giga link quality */
1991	if (hw->phy_type == e1000_phy_igp) {
1992	ret_val = e1000_config_dsp_after_link_change(hw, TRUE);
1993	if (ret_val) {
1994	DEBUGOUT("Error Configuring DSP after link up\n");
1995	return ret_val;
1996	}
1997	}
1998
1999	return E1000_SUCCESS;
2000	}
2001
2002	/******************************************************************************
2003	* Detects which PHY is present and setup the speed and duplex
2004	*
2005	* hw - Struct containing variables accessed by shared code
2006	******************************************************************************/
2007	static int32_t
2008	e1000_setup_copper_link(struct e1000_hw *hw)
2009	{
2010	int32_t ret_val;
2011	uint16_t i;
2012	uint16_t phy_data;
2013	uint16_t reg_data;
2014
2015	DEBUGFUNC("e1000_setup_copper_link");
2016
2017	switch (hw->mac_type) {
2018	case e1000_80003es2lan:
2019	case e1000_ich8lan:
2020	/* Set the mac to wait the maximum time between each
2021	* iteration and increase the max iterations when
2022	* polling the phy; this fixes erroneous timeouts at 10Mbps. */
2023	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 4), 0xFFFF);
2024	if (ret_val)
2025	return ret_val;
2026	ret_val = e1000_read_kmrn_reg(hw, GG82563_REG(0x34, 9), &reg_data);
2027	if (ret_val)
2028	return ret_val;
2029	reg_data \|= 0x3F;
2030	ret_val = e1000_write_kmrn_reg(hw, GG82563_REG(0x34, 9), reg_data);
2031	if (ret_val)
2032	return ret_val;
2033	default:
2034	break;
2035	}
2036
2037	/* Check if it is a valid PHY and set PHY mode if necessary. */
2038	ret_val = e1000_copper_link_preconfig(hw);
2039	if (ret_val)
2040	return ret_val;
2041
2042	switch (hw->mac_type) {
2043	case e1000_80003es2lan:
2044	/* Kumeran registers are written-only */
2045	reg_data = E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT;
2046	reg_data \|= E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING;
2047	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_INB_CTRL,
2048	reg_data);
2049	if (ret_val)
2050	return ret_val;
2051	break;
2052	default:
2053	break;
2054	}
2055
2056	if (hw->phy_type == e1000_phy_igp \|\|
2057	hw->phy_type == e1000_phy_igp_3 \|\|
2058	hw->phy_type == e1000_phy_igp_2) {
2059	ret_val = e1000_copper_link_igp_setup(hw);
2060	if (ret_val)
2061	return ret_val;
2062	} else if (hw->phy_type == e1000_phy_m88) {
2063	ret_val = e1000_copper_link_mgp_setup(hw);
2064	if (ret_val)
2065	return ret_val;
2066	} else if (hw->phy_type == e1000_phy_gg82563) {
2067	ret_val = e1000_copper_link_ggp_setup(hw);
2068	if (ret_val)
2069	return ret_val;
2070	}
2071
2072	if (hw->autoneg) {
2073	/* Setup autoneg and flow control advertisement
2074	* and perform autonegotiation */
2075	ret_val = e1000_copper_link_autoneg(hw);
2076	if (ret_val)
2077	return ret_val;
2078	} else {
2079	/* PHY will be set to 10H, 10F, 100H,or 100F
2080	* depending on value from forced_speed_duplex. */
2081	DEBUGOUT("Forcing speed and duplex\n");
2082	ret_val = e1000_phy_force_speed_duplex(hw);
2083	if (ret_val) {
2084	DEBUGOUT("Error Forcing Speed and Duplex\n");
2085	return ret_val;
2086	}
2087	}
2088
2089	/* Check link status. Wait up to 100 microseconds for link to become
2090	* valid.
2091	*/
2092	for (i = 0; i < 10; i++) {
2093	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2094	if (ret_val)
2095	return ret_val;
2096	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
2097	if (ret_val)
2098	return ret_val;
2099
2100	if (phy_data & MII_SR_LINK_STATUS) {
2101	/* Config the MAC and PHY after link is up */
2102	ret_val = e1000_copper_link_postconfig(hw);
2103	if (ret_val)
2104	return ret_val;
2105
2106	DEBUGOUT("Valid link established!!!\n");
2107	return E1000_SUCCESS;
2108	}
2109	udelay(10);
2110	}
2111
2112	DEBUGOUT("Unable to establish link!!!\n");
2113	return E1000_SUCCESS;
2114	}
2115
2116	/******************************************************************************
2117	* Configure the MAC-to-PHY interface for 10/100Mbps
2118	*
2119	* hw - Struct containing variables accessed by shared code
2120	******************************************************************************/
2121	static int32_t
2122	e1000_configure_kmrn_for_10_100(struct e1000_hw *hw, uint16_t duplex)
2123	{
2124	int32_t ret_val = E1000_SUCCESS;
2125	uint32_t tipg;
2126	uint16_t reg_data;
2127
2128	DEBUGFUNC("e1000_configure_kmrn_for_10_100");
2129
2130	reg_data = E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT;
2131	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2132	reg_data);
2133	if (ret_val)
2134	return ret_val;
2135
2136	/* Configure Transmit Inter-Packet Gap */
2137	tipg = E1000_READ_REG(hw, TIPG);
2138	tipg &= ~E1000_TIPG_IPGT_MASK;
2139	tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_10_100;
2140	E1000_WRITE_REG(hw, TIPG, tipg);
2141
2142	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2143
2144	if (ret_val)
2145	return ret_val;
2146
2147	if (duplex == HALF_DUPLEX)
2148	reg_data \|= GG82563_KMCR_PASS_FALSE_CARRIER;
2149	else
2150	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2151
2152	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2153
2154	return ret_val;
2155	}
2156
2157	static int32_t
2158	e1000_configure_kmrn_for_1000(struct e1000_hw *hw)
2159	{
2160	int32_t ret_val = E1000_SUCCESS;
2161	uint16_t reg_data;
2162	uint32_t tipg;
2163
2164	DEBUGFUNC("e1000_configure_kmrn_for_1000");
2165
2166	reg_data = E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT;
2167	ret_val = e1000_write_kmrn_reg(hw, E1000_KUMCTRLSTA_OFFSET_HD_CTRL,
2168	reg_data);
2169	if (ret_val)
2170	return ret_val;
2171
2172	/* Configure Transmit Inter-Packet Gap */
2173	tipg = E1000_READ_REG(hw, TIPG);
2174	tipg &= ~E1000_TIPG_IPGT_MASK;
2175	tipg \|= DEFAULT_80003ES2LAN_TIPG_IPGT_1000;
2176	E1000_WRITE_REG(hw, TIPG, tipg);
2177
2178	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, &reg_data);
2179
2180	if (ret_val)
2181	return ret_val;
2182
2183	reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
2184	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
2185
2186	return ret_val;
2187	}
2188
2189	/******************************************************************************
2190	* Configures PHY autoneg and flow control advertisement settings
2191	*
2192	* hw - Struct containing variables accessed by shared code
2193	******************************************************************************/
2194	int32_t
2195	e1000_phy_setup_autoneg(struct e1000_hw *hw)
2196	{
2197	int32_t ret_val;
2198	uint16_t mii_autoneg_adv_reg;
2199	uint16_t mii_1000t_ctrl_reg;
2200
2201	DEBUGFUNC("e1000_phy_setup_autoneg");
2202
2203	/* Read the MII Auto-Neg Advertisement Register (Address 4). */
2204	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV, &mii_autoneg_adv_reg);
2205	if (ret_val)
2206	return ret_val;
2207
2208	if (hw->phy_type != e1000_phy_ife) {
2209	/* Read the MII 1000Base-T Control Register (Address 9). */
2210	ret_val = e1000_read_phy_reg(hw, PHY_1000T_CTRL, &mii_1000t_ctrl_reg);
2211	if (ret_val)
2212	return ret_val;
2213	} else
2214	mii_1000t_ctrl_reg=0;
2215
2216	/* Need to parse both autoneg_advertised and fc and set up
2217	* the appropriate PHY registers. First we will parse for
2218	* autoneg_advertised software override. Since we can advertise
2219	* a plethora of combinations, we need to check each bit
2220	* individually.
2221	*/
2222
2223	/* First we clear all the 10/100 mb speed bits in the Auto-Neg
2224	* Advertisement Register (Address 4) and the 1000 mb speed bits in
2225	* the 1000Base-T Control Register (Address 9).
2226	*/
2227	mii_autoneg_adv_reg &= ~REG4_SPEED_MASK;
2228	mii_1000t_ctrl_reg &= ~REG9_SPEED_MASK;
2229
2230	DEBUGOUT1("autoneg_advertised %x\n", hw->autoneg_advertised);
2231
2232	/* Do we want to advertise 10 Mb Half Duplex? */
2233	if (hw->autoneg_advertised & ADVERTISE_10_HALF) {
2234	DEBUGOUT("Advertise 10mb Half duplex\n");
2235	mii_autoneg_adv_reg \|= NWAY_AR_10T_HD_CAPS;
2236	}
2237
2238	/* Do we want to advertise 10 Mb Full Duplex? */
2239	if (hw->autoneg_advertised & ADVERTISE_10_FULL) {
2240	DEBUGOUT("Advertise 10mb Full duplex\n");
2241	mii_autoneg_adv_reg \|= NWAY_AR_10T_FD_CAPS;
2242	}
2243
2244	/* Do we want to advertise 100 Mb Half Duplex? */
2245	if (hw->autoneg_advertised & ADVERTISE_100_HALF) {
2246	DEBUGOUT("Advertise 100mb Half duplex\n");
2247	mii_autoneg_adv_reg \|= NWAY_AR_100TX_HD_CAPS;
2248	}
2249
2250	/* Do we want to advertise 100 Mb Full Duplex? */
2251	if (hw->autoneg_advertised & ADVERTISE_100_FULL) {
2252	DEBUGOUT("Advertise 100mb Full duplex\n");
2253	mii_autoneg_adv_reg \|= NWAY_AR_100TX_FD_CAPS;
2254	}
2255
2256	/* We do not allow the Phy to advertise 1000 Mb Half Duplex */
2257	if (hw->autoneg_advertised & ADVERTISE_1000_HALF) {
2258	DEBUGOUT("Advertise 1000mb Half duplex requested, request denied!\n");
2259	}
2260
2261	/* Do we want to advertise 1000 Mb Full Duplex? */
2262	if (hw->autoneg_advertised & ADVERTISE_1000_FULL) {
2263	DEBUGOUT("Advertise 1000mb Full duplex\n");
2264	mii_1000t_ctrl_reg \|= CR_1000T_FD_CAPS;
2265	if (hw->phy_type == e1000_phy_ife) {
2266	DEBUGOUT("e1000_phy_ife is a 10/100 PHY. Gigabit speed is not supported.\n");
2267	}
2268	}
2269
2270	/* Check for a software override of the flow control settings, and
2271	* setup the PHY advertisement registers accordingly. If
2272	* auto-negotiation is enabled, then software will have to set the
2273	* "PAUSE" bits to the correct value in the Auto-Negotiation
2274	* Advertisement Register (PHY_AUTONEG_ADV) and re-start auto-negotiation.
2275	*
2276	* The possible values of the "fc" parameter are:
2277	* 0: Flow control is completely disabled
2278	* 1: Rx flow control is enabled (we can receive pause frames
2279	* but not send pause frames).
2280	* 2: Tx flow control is enabled (we can send pause frames
2281	* but we do not support receiving pause frames).
2282	* 3: Both Rx and TX flow control (symmetric) are enabled.
2283	* other: No software override. The flow control configuration
2284	* in the EEPROM is used.
2285	*/
2286	switch (hw->fc) {
2287	case E1000_FC_NONE: /* 0 */
2288	/* Flow control (RX & TX) is completely disabled by a
2289	* software over-ride.
2290	*/
2291	mii_autoneg_adv_reg &= ~(NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
2292	break;
2293	case E1000_FC_RX_PAUSE: /* 1 */
2294	/* RX Flow control is enabled, and TX Flow control is
2295	* disabled, by a software over-ride.
2296	*/
2297	/* Since there really isn't a way to advertise that we are
2298	* capable of RX Pause ONLY, we will advertise that we
2299	* support both symmetric and asymmetric RX PAUSE. Later
2300	* (in e1000_config_fc_after_link_up) we will disable the
2301	*hw's ability to send PAUSE frames.
2302	*/
2303	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
2304	break;
2305	case E1000_FC_TX_PAUSE: /* 2 */
2306	/* TX Flow control is enabled, and RX Flow control is
2307	* disabled, by a software over-ride.
2308	*/
2309	mii_autoneg_adv_reg \|= NWAY_AR_ASM_DIR;
2310	mii_autoneg_adv_reg &= ~NWAY_AR_PAUSE;
2311	break;
2312	case E1000_FC_FULL: /* 3 */
2313	/* Flow control (both RX and TX) is enabled by a software
2314	* over-ride.
2315	*/
2316	mii_autoneg_adv_reg \|= (NWAY_AR_ASM_DIR \| NWAY_AR_PAUSE);
2317	break;
2318	default:
2319	DEBUGOUT("Flow control param set incorrectly\n");
2320	return -E1000_ERR_CONFIG;
2321	}
2322
2323	ret_val = e1000_write_phy_reg(hw, PHY_AUTONEG_ADV, mii_autoneg_adv_reg);
2324	if (ret_val)
2325	return ret_val;
2326
2327	DEBUGOUT1("Auto-Neg Advertising %x\n", mii_autoneg_adv_reg);
2328
2329	if (hw->phy_type != e1000_phy_ife) {
2330	ret_val = e1000_write_phy_reg(hw, PHY_1000T_CTRL, mii_1000t_ctrl_reg);
2331	if (ret_val)
2332	return ret_val;
2333	}
2334
2335	return E1000_SUCCESS;
2336	}
2337
2338	/******************************************************************************
2339	* Force PHY speed and duplex settings to hw->forced_speed_duplex
2340	*
2341	* hw - Struct containing variables accessed by shared code
2342	******************************************************************************/
2343	static int32_t
2344	e1000_phy_force_speed_duplex(struct e1000_hw *hw)
2345	{
2346	uint32_t ctrl;
2347	int32_t ret_val;
2348	uint16_t mii_ctrl_reg;
2349	uint16_t mii_status_reg;
2350	uint16_t phy_data;
2351	uint16_t i;
2352
2353	DEBUGFUNC("e1000_phy_force_speed_duplex");
2354
2355	/* Turn off Flow control if we are forcing speed and duplex. */
2356	hw->fc = E1000_FC_NONE;
2357
2358	DEBUGOUT1("hw->fc = %d\n", hw->fc);
2359
2360	/* Read the Device Control Register. */
2361	ctrl = E1000_READ_REG(hw, CTRL);
2362
2363	/* Set the bits to Force Speed and Duplex in the Device Ctrl Reg. */
2364	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
2365	ctrl &= ~(DEVICE_SPEED_MASK);
2366
2367	/* Clear the Auto Speed Detect Enable bit. */
2368	ctrl &= ~E1000_CTRL_ASDE;
2369
2370	/* Read the MII Control Register. */
2371	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &mii_ctrl_reg);
2372	if (ret_val)
2373	return ret_val;
2374
2375	/* We need to disable autoneg in order to force link and duplex. */
2376
2377	mii_ctrl_reg &= ~MII_CR_AUTO_NEG_EN;
2378
2379	/* Are we forcing Full or Half Duplex? */
2380	if (hw->forced_speed_duplex == e1000_100_full \|\|
2381	hw->forced_speed_duplex == e1000_10_full) {
2382	/* We want to force full duplex so we SET the full duplex bits in the
2383	* Device and MII Control Registers.
2384	*/
2385	ctrl \|= E1000_CTRL_FD;
2386	mii_ctrl_reg \|= MII_CR_FULL_DUPLEX;
2387	DEBUGOUT("Full Duplex\n");
2388	} else {
2389	/* We want to force half duplex so we CLEAR the full duplex bits in
2390	* the Device and MII Control Registers.
2391	*/
2392	ctrl &= ~E1000_CTRL_FD;
2393	mii_ctrl_reg &= ~MII_CR_FULL_DUPLEX;
2394	DEBUGOUT("Half Duplex\n");
2395	}
2396
2397	/* Are we forcing 100Mbps??? */
2398	if (hw->forced_speed_duplex == e1000_100_full \|\|
2399	hw->forced_speed_duplex == e1000_100_half) {
2400	/* Set the 100Mb bit and turn off the 1000Mb and 10Mb bits. */
2401	ctrl \|= E1000_CTRL_SPD_100;
2402	mii_ctrl_reg \|= MII_CR_SPEED_100;
2403	mii_ctrl_reg &= ~(MII_CR_SPEED_1000 \| MII_CR_SPEED_10);
2404	DEBUGOUT("Forcing 100mb ");
2405	} else {
2406	/* Set the 10Mb bit and turn off the 1000Mb and 100Mb bits. */
2407	ctrl &= ~(E1000_CTRL_SPD_1000 \| E1000_CTRL_SPD_100);
2408	mii_ctrl_reg \|= MII_CR_SPEED_10;
2409	mii_ctrl_reg &= ~(MII_CR_SPEED_1000 \| MII_CR_SPEED_100);
2410	DEBUGOUT("Forcing 10mb ");
2411	}
2412
2413	e1000_config_collision_dist(hw);
2414
2415	/* Write the configured values back to the Device Control Reg. */
2416	E1000_WRITE_REG(hw, CTRL, ctrl);
2417
2418	if ((hw->phy_type == e1000_phy_m88) \|\|
2419	(hw->phy_type == e1000_phy_gg82563)) {
2420	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2421	if (ret_val)
2422	return ret_val;
2423
2424	/* Clear Auto-Crossover to force MDI manually. M88E1000 requires MDI
2425	* forced whenever speed are duplex are forced.
2426	*/
2427	phy_data &= ~M88E1000_PSCR_AUTO_X_MODE;
2428	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2429	if (ret_val)
2430	return ret_val;
2431
2432	DEBUGOUT1("M88E1000 PSCR: %x \n", phy_data);
2433
2434	/* Need to reset the PHY or these changes will be ignored */
2435	mii_ctrl_reg \|= MII_CR_RESET;
2436
2437	/* Disable MDI-X support for 10/100 */
2438	} else if (hw->phy_type == e1000_phy_ife) {
2439	ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
2440	if (ret_val)
2441	return ret_val;
2442
2443	phy_data &= ~IFE_PMC_AUTO_MDIX;
2444	phy_data &= ~IFE_PMC_FORCE_MDIX;
2445
2446	ret_val = e1000_write_phy_reg(hw, IFE_PHY_MDIX_CONTROL, phy_data);
2447	if (ret_val)
2448	return ret_val;
2449
2450	} else {
2451	/* Clear Auto-Crossover to force MDI manually. IGP requires MDI
2452	* forced whenever speed or duplex are forced.
2453	*/
2454	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, &phy_data);
2455	if (ret_val)
2456	return ret_val;
2457
2458	phy_data &= ~IGP01E1000_PSCR_AUTO_MDIX;
2459	phy_data &= ~IGP01E1000_PSCR_FORCE_MDI_MDIX;
2460
2461	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CTRL, phy_data);
2462	if (ret_val)
2463	return ret_val;
2464	}
2465
2466	/* Write back the modified PHY MII control register. */
2467	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, mii_ctrl_reg);
2468	if (ret_val)
2469	return ret_val;
2470
2471	udelay(1);
2472
2473	/* The wait_autoneg_complete flag may be a little misleading here.
2474	* Since we are forcing speed and duplex, Auto-Neg is not enabled.
2475	* But we do want to delay for a period while forcing only so we
2476	* don't generate false No Link messages. So we will wait here
2477	* only if the user has set wait_autoneg_complete to 1, which is
2478	* the default.
2479	*/
2480	if (hw->wait_autoneg_complete) {
2481	/* We will wait for autoneg to complete. */
2482	DEBUGOUT("Waiting for forced speed/duplex link.\n");
2483	mii_status_reg = 0;
2484
2485	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
2486	for (i = PHY_FORCE_TIME; i > 0; i--) {
2487	/* Read the MII Status Register and wait for Auto-Neg Complete bit
2488	* to be set.
2489	*/
2490	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2491	if (ret_val)
2492	return ret_val;
2493
2494	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2495	if (ret_val)
2496	return ret_val;
2497
2498	if (mii_status_reg & MII_SR_LINK_STATUS) break;
2499	msleep(100);
2500	}
2501	if ((i == 0) &&
2502	((hw->phy_type == e1000_phy_m88) \|\|
2503	(hw->phy_type == e1000_phy_gg82563))) {
2504	/* We didn't get link. Reset the DSP and wait again for link. */
2505	ret_val = e1000_phy_reset_dsp(hw);
2506	if (ret_val) {
2507	DEBUGOUT("Error Resetting PHY DSP\n");
2508	return ret_val;
2509	}
2510	}
2511	/* This loop will early-out if the link condition has been met. */
2512	for (i = PHY_FORCE_TIME; i > 0; i--) {
2513	if (mii_status_reg & MII_SR_LINK_STATUS) break;
2514	msleep(100);
2515	/* Read the MII Status Register and wait for Auto-Neg Complete bit
2516	* to be set.
2517	*/
2518	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2519	if (ret_val)
2520	return ret_val;
2521
2522	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2523	if (ret_val)
2524	return ret_val;
2525	}
2526	}
2527
2528	if (hw->phy_type == e1000_phy_m88) {
2529	/* Because we reset the PHY above, we need to re-force TX_CLK in the
2530	* Extended PHY Specific Control Register to 25MHz clock. This value
2531	* defaults back to a 2.5MHz clock when the PHY is reset.
2532	*/
2533	ret_val = e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_data);
2534	if (ret_val)
2535	return ret_val;
2536
2537	phy_data \|= M88E1000_EPSCR_TX_CLK_25;
2538	ret_val = e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_data);
2539	if (ret_val)
2540	return ret_val;
2541
2542	/* In addition, because of the s/w reset above, we need to enable CRS on
2543	* TX. This must be set for both full and half duplex operation.
2544	*/
2545	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
2546	if (ret_val)
2547	return ret_val;
2548
2549	phy_data \|= M88E1000_PSCR_ASSERT_CRS_ON_TX;
2550	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_data);
2551	if (ret_val)
2552	return ret_val;
2553
2554	if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
2555	(!hw->autoneg) && (hw->forced_speed_duplex == e1000_10_full \|\|
2556	hw->forced_speed_duplex == e1000_10_half)) {
2557	ret_val = e1000_polarity_reversal_workaround(hw);
2558	if (ret_val)
2559	return ret_val;
2560	}
2561	} else if (hw->phy_type == e1000_phy_gg82563) {
2562	/* The TX_CLK of the Extended PHY Specific Control Register defaults
2563	* to 2.5MHz on a reset. We need to re-force it back to 25MHz, if
2564	* we're not in a forced 10/duplex configuration. */
2565	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
2566	if (ret_val)
2567	return ret_val;
2568
2569	phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
2570	if ((hw->forced_speed_duplex == e1000_10_full) \|\|
2571	(hw->forced_speed_duplex == e1000_10_half))
2572	phy_data \|= GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ;
2573	else
2574	phy_data \|= GG82563_MSCR_TX_CLK_100MBPS_25MHZ;
2575
2576	/* Also due to the reset, we need to enable CRS on Tx. */
2577	phy_data \|= GG82563_MSCR_ASSERT_CRS_ON_TX;
2578
2579	ret_val = e1000_write_phy_reg(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
2580	if (ret_val)
2581	return ret_val;
2582	}
2583	return E1000_SUCCESS;
2584	}
2585
2586	/******************************************************************************
2587	* Sets the collision distance in the Transmit Control register
2588	*
2589	* hw - Struct containing variables accessed by shared code
2590	*
2591	* Link should have been established previously. Reads the speed and duplex
2592	* information from the Device Status register.
2593	******************************************************************************/
2594	void
2595	e1000_config_collision_dist(struct e1000_hw *hw)
2596	{
2597	uint32_t tctl, coll_dist;
2598
2599	DEBUGFUNC("e1000_config_collision_dist");
2600
2601	if (hw->mac_type < e1000_82543)
2602	coll_dist = E1000_COLLISION_DISTANCE_82542;
2603	else
2604	coll_dist = E1000_COLLISION_DISTANCE;
2605
2606	tctl = E1000_READ_REG(hw, TCTL);
2607
2608	tctl &= ~E1000_TCTL_COLD;
2609	tctl \|= coll_dist << E1000_COLD_SHIFT;
2610
2611	E1000_WRITE_REG(hw, TCTL, tctl);
2612	E1000_WRITE_FLUSH(hw);
2613	}
2614
2615	/******************************************************************************
2616	* Sets MAC speed and duplex settings to reflect the those in the PHY
2617	*
2618	* hw - Struct containing variables accessed by shared code
2619	* mii_reg - data to write to the MII control register
2620	*
2621	* The contents of the PHY register containing the needed information need to
2622	* be passed in.
2623	******************************************************************************/
2624	static int32_t
2625	e1000_config_mac_to_phy(struct e1000_hw *hw)
2626	{
2627	uint32_t ctrl;
2628	int32_t ret_val;
2629	uint16_t phy_data;
2630
2631	DEBUGFUNC("e1000_config_mac_to_phy");
2632
2633	/* 82544 or newer MAC, Auto Speed Detection takes care of
2634	* MAC speed/duplex configuration.*/
2635	if (hw->mac_type >= e1000_82544)
2636	return E1000_SUCCESS;
2637
2638	/* Read the Device Control Register and set the bits to Force Speed
2639	* and Duplex.
2640	*/
2641	ctrl = E1000_READ_REG(hw, CTRL);
2642	ctrl \|= (E1000_CTRL_FRCSPD \| E1000_CTRL_FRCDPX);
2643	ctrl &= ~(E1000_CTRL_SPD_SEL \| E1000_CTRL_ILOS);
2644
2645	/* Set up duplex in the Device Control and Transmit Control
2646	* registers depending on negotiated values.
2647	*/
2648	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
2649	if (ret_val)
2650	return ret_val;
2651
2652	if (phy_data & M88E1000_PSSR_DPLX)
2653	ctrl \|= E1000_CTRL_FD;
2654	else
2655	ctrl &= ~E1000_CTRL_FD;
2656
2657	e1000_config_collision_dist(hw);
2658
2659	/* Set up speed in the Device Control register depending on
2660	* negotiated values.
2661	*/
2662	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS)
2663	ctrl \|= E1000_CTRL_SPD_1000;
2664	else if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_100MBS)
2665	ctrl \|= E1000_CTRL_SPD_100;
2666
2667	/* Write the configured values back to the Device Control Reg. */
2668	E1000_WRITE_REG(hw, CTRL, ctrl);
2669	return E1000_SUCCESS;
2670	}
2671
2672	/******************************************************************************
2673	* Forces the MAC's flow control settings.
2674	*
2675	* hw - Struct containing variables accessed by shared code
2676	*
2677	* Sets the TFCE and RFCE bits in the device control register to reflect
2678	* the adapter settings. TFCE and RFCE need to be explicitly set by
2679	* software when a Copper PHY is used because autonegotiation is managed
2680	* by the PHY rather than the MAC. Software must also configure these
2681	* bits when link is forced on a fiber connection.
2682	*****************************************************************************/
2683	int32_t
2684	e1000_force_mac_fc(struct e1000_hw *hw)
2685	{
2686	uint32_t ctrl;
2687
2688	DEBUGFUNC("e1000_force_mac_fc");
2689
2690	/* Get the current configuration of the Device Control Register */
2691	ctrl = E1000_READ_REG(hw, CTRL);
2692
2693	/* Because we didn't get link via the internal auto-negotiation
2694	* mechanism (we either forced link or we got link via PHY
2695	* auto-neg), we have to manually enable/disable transmit an
2696	* receive flow control.
2697	*
2698	* The "Case" statement below enables/disable flow control
2699	* according to the "hw->fc" parameter.
2700	*
2701	* The possible values of the "fc" parameter are:
2702	* 0: Flow control is completely disabled
2703	* 1: Rx flow control is enabled (we can receive pause
2704	* frames but not send pause frames).
2705	* 2: Tx flow control is enabled (we can send pause frames
2706	* frames but we do not receive pause frames).
2707	* 3: Both Rx and TX flow control (symmetric) is enabled.
2708	* other: No other values should be possible at this point.
2709	*/
2710
2711	switch (hw->fc) {
2712	case E1000_FC_NONE:
2713	ctrl &= (~(E1000_CTRL_TFCE \| E1000_CTRL_RFCE));
2714	break;
2715	case E1000_FC_RX_PAUSE:
2716	ctrl &= (~E1000_CTRL_TFCE);
2717	ctrl \|= E1000_CTRL_RFCE;
2718	break;
2719	case E1000_FC_TX_PAUSE:
2720	ctrl &= (~E1000_CTRL_RFCE);
2721	ctrl \|= E1000_CTRL_TFCE;
2722	break;
2723	case E1000_FC_FULL:
2724	ctrl \|= (E1000_CTRL_TFCE \| E1000_CTRL_RFCE);
2725	break;
2726	default:
2727	DEBUGOUT("Flow control param set incorrectly\n");
2728	return -E1000_ERR_CONFIG;
2729	}
2730
2731	/* Disable TX Flow Control for 82542 (rev 2.0) */
2732	if (hw->mac_type == e1000_82542_rev2_0)
2733	ctrl &= (~E1000_CTRL_TFCE);
2734
2735	E1000_WRITE_REG(hw, CTRL, ctrl);
2736	return E1000_SUCCESS;
2737	}
2738
2739	/******************************************************************************
2740	* Configures flow control settings after link is established
2741	*
2742	* hw - Struct containing variables accessed by shared code
2743	*
2744	* Should be called immediately after a valid link has been established.
2745	* Forces MAC flow control settings if link was forced. When in MII/GMII mode
2746	* and autonegotiation is enabled, the MAC flow control settings will be set
2747	* based on the flow control negotiated by the PHY. In TBI mode, the TFCE
2748	* and RFCE bits will be automaticaly set to the negotiated flow control mode.
2749	*****************************************************************************/
2750	static int32_t
2751	e1000_config_fc_after_link_up(struct e1000_hw *hw)
2752	{
2753	int32_t ret_val;
2754	uint16_t mii_status_reg;
2755	uint16_t mii_nway_adv_reg;
2756	uint16_t mii_nway_lp_ability_reg;
2757	uint16_t speed;
2758	uint16_t duplex;
2759
2760	DEBUGFUNC("e1000_config_fc_after_link_up");
2761
2762	/* Check for the case where we have fiber media and auto-neg failed
2763	* so we had to force link. In this case, we need to force the
2764	* configuration of the MAC to match the "fc" parameter.
2765	*/
2766	if (((hw->media_type == e1000_media_type_fiber) && (hw->autoneg_failed)) \|\|
2767	((hw->media_type == e1000_media_type_internal_serdes) &&
2768	(hw->autoneg_failed)) \|\|
2769	((hw->media_type == e1000_media_type_copper) && (!hw->autoneg))) {
2770	ret_val = e1000_force_mac_fc(hw);
2771	if (ret_val) {
2772	DEBUGOUT("Error forcing flow control settings\n");
2773	return ret_val;
2774	}
2775	}
2776
2777	/* Check for the case where we have copper media and auto-neg is
2778	* enabled. In this case, we need to check and see if Auto-Neg
2779	* has completed, and if so, how the PHY and link partner has
2780	* flow control configured.
2781	*/
2782	if ((hw->media_type == e1000_media_type_copper) && hw->autoneg) {
2783	/* Read the MII Status Register and check to see if AutoNeg
2784	* has completed. We read this twice because this reg has
2785	* some "sticky" (latched) bits.
2786	*/
2787	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2788	if (ret_val)
2789	return ret_val;
2790	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
2791	if (ret_val)
2792	return ret_val;
2793
2794	if (mii_status_reg & MII_SR_AUTONEG_COMPLETE) {
2795	/* The AutoNeg process has completed, so we now need to
2796	* read both the Auto Negotiation Advertisement Register
2797	* (Address 4) and the Auto_Negotiation Base Page Ability
2798	* Register (Address 5) to determine how flow control was
2799	* negotiated.
2800	*/
2801	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_ADV,
2802	&mii_nway_adv_reg);
2803	if (ret_val)
2804	return ret_val;
2805	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY,
2806	&mii_nway_lp_ability_reg);
2807	if (ret_val)
2808	return ret_val;
2809
2810	/* Two bits in the Auto Negotiation Advertisement Register
2811	* (Address 4) and two bits in the Auto Negotiation Base
2812	* Page Ability Register (Address 5) determine flow control
2813	* for both the PHY and the link partner. The following
2814	* table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
2815	* 1999, describes these PAUSE resolution bits and how flow
2816	* control is determined based upon these settings.
2817	* NOTE: DC = Don't Care
2818	*
2819	* LOCAL DEVICE \| LINK PARTNER
2820	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| NIC Resolution
2821	*-------\|---------\|-------\|---------\|--------------------
2822	* 0 \| 0 \| DC \| DC \| E1000_FC_NONE
2823	* 0 \| 1 \| 0 \| DC \| E1000_FC_NONE
2824	* 0 \| 1 \| 1 \| 0 \| E1000_FC_NONE
2825	* 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
2826	* 1 \| 0 \| 0 \| DC \| E1000_FC_NONE
2827	* 1 \| DC \| 1 \| DC \| E1000_FC_FULL
2828	* 1 \| 1 \| 0 \| 0 \| E1000_FC_NONE
2829	* 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
2830	*
2831	*/
2832	/* Are both PAUSE bits set to 1? If so, this implies
2833	* Symmetric Flow Control is enabled at both ends. The
2834	* ASM_DIR bits are irrelevant per the spec.
2835	*
2836	* For Symmetric Flow Control:
2837	*
2838	* LOCAL DEVICE \| LINK PARTNER
2839	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
2840	*-------\|---------\|-------\|---------\|--------------------
2841	* 1 \| DC \| 1 \| DC \| E1000_FC_FULL
2842	*
2843	*/
2844	if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2845	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
2846	/* Now we need to check if the user selected RX ONLY
2847	* of pause frames. In this case, we had to advertise
2848	* FULL flow control because we could not advertise RX
2849	* ONLY. Hence, we must now check to see if we need to
2850	* turn OFF the TRANSMISSION of PAUSE frames.
2851	*/
2852	if (hw->original_fc == E1000_FC_FULL) {
2853	hw->fc = E1000_FC_FULL;
2854	DEBUGOUT("Flow Control = FULL.\n");
2855	} else {
2856	hw->fc = E1000_FC_RX_PAUSE;
2857	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2858	}
2859	}
2860	/* For receiving PAUSE frames ONLY.
2861	*
2862	* LOCAL DEVICE \| LINK PARTNER
2863	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
2864	*-------\|---------\|-------\|---------\|--------------------
2865	* 0 \| 1 \| 1 \| 1 \| E1000_FC_TX_PAUSE
2866	*
2867	*/
2868	else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2869	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2870	(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2871	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2872	hw->fc = E1000_FC_TX_PAUSE;
2873	DEBUGOUT("Flow Control = TX PAUSE frames only.\n");
2874	}
2875	/* For transmitting PAUSE frames ONLY.
2876	*
2877	* LOCAL DEVICE \| LINK PARTNER
2878	* PAUSE \| ASM_DIR \| PAUSE \| ASM_DIR \| Result
2879	*-------\|---------\|-------\|---------\|--------------------
2880	* 1 \| 1 \| 0 \| 1 \| E1000_FC_RX_PAUSE
2881	*
2882	*/
2883	else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
2884	(mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
2885	!(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
2886	(mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
2887	hw->fc = E1000_FC_RX_PAUSE;
2888	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2889	}
2890	/* Per the IEEE spec, at this point flow control should be
2891	* disabled. However, we want to consider that we could
2892	* be connected to a legacy switch that doesn't advertise
2893	* desired flow control, but can be forced on the link
2894	* partner. So if we advertised no flow control, that is
2895	* what we will resolve to. If we advertised some kind of
2896	* receive capability (Rx Pause Only or Full Flow Control)
2897	* and the link partner advertised none, we will configure
2898	* ourselves to enable Rx Flow Control only. We can do
2899	* this safely for two reasons: If the link partner really
2900	* didn't want flow control enabled, and we enable Rx, no
2901	* harm done since we won't be receiving any PAUSE frames
2902	* anyway. If the intent on the link partner was to have
2903	* flow control enabled, then by us enabling RX only, we
2904	* can at least receive pause frames and process them.
2905	* This is a good idea because in most cases, since we are
2906	* predominantly a server NIC, more times than not we will
2907	* be asked to delay transmission of packets than asking
2908	* our link partner to pause transmission of frames.
2909	*/
2910	else if ((hw->original_fc == E1000_FC_NONE \|\|
2911	hw->original_fc == E1000_FC_TX_PAUSE) \|\|
2912	hw->fc_strict_ieee) {
2913	hw->fc = E1000_FC_NONE;
2914	DEBUGOUT("Flow Control = NONE.\n");
2915	} else {
2916	hw->fc = E1000_FC_RX_PAUSE;
2917	DEBUGOUT("Flow Control = RX PAUSE frames only.\n");
2918	}
2919
2920	/* Now we need to do one last check... If we auto-
2921	* negotiated to HALF DUPLEX, flow control should not be
2922	* enabled per IEEE 802.3 spec.
2923	*/
2924	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
2925	if (ret_val) {
2926	DEBUGOUT("Error getting link speed and duplex\n");
2927	return ret_val;
2928	}
2929
2930	if (duplex == HALF_DUPLEX)
2931	hw->fc = E1000_FC_NONE;
2932
2933	/* Now we call a subroutine to actually force the MAC
2934	* controller to use the correct flow control settings.
2935	*/
2936	ret_val = e1000_force_mac_fc(hw);
2937	if (ret_val) {
2938	DEBUGOUT("Error forcing flow control settings\n");
2939	return ret_val;
2940	}
2941	} else {
2942	DEBUGOUT("Copper PHY and Auto Neg has not completed.\n");
2943	}
2944	}
2945	return E1000_SUCCESS;
2946	}
2947
2948	/******************************************************************************
2949	* Checks to see if the link status of the hardware has changed.
2950	*
2951	* hw - Struct containing variables accessed by shared code
2952	*
2953	* Called by any function that needs to check the link status of the adapter.
2954	*****************************************************************************/
2955	int32_t
2956	e1000_check_for_link(struct e1000_hw *hw)
2957	{
2958	uint32_t rxcw = 0;
2959	uint32_t ctrl;
2960	uint32_t status;
2961	uint32_t rctl;
2962	uint32_t icr;
2963	uint32_t signal = 0;
2964	int32_t ret_val;
2965	uint16_t phy_data;
2966
2967	DEBUGFUNC("e1000_check_for_link");
2968
2969	ctrl = E1000_READ_REG(hw, CTRL);
2970	status = E1000_READ_REG(hw, STATUS);
2971
2972	/* On adapters with a MAC newer than 82544, SW Defineable pin 1 will be
2973	* set when the optics detect a signal. On older adapters, it will be
2974	* cleared when there is a signal. This applies to fiber media only.
2975	*/
2976	if ((hw->media_type == e1000_media_type_fiber) \|\|
2977	(hw->media_type == e1000_media_type_internal_serdes)) {
2978	rxcw = E1000_READ_REG(hw, RXCW);
2979
2980	if (hw->media_type == e1000_media_type_fiber) {
2981	signal = (hw->mac_type > e1000_82544) ? E1000_CTRL_SWDPIN1 : 0;
2982	if (status & E1000_STATUS_LU)
2983	hw->get_link_status = FALSE;
2984	}
2985	}
2986
2987	/* If we have a copper PHY then we only want to go out to the PHY
2988	* registers to see if Auto-Neg has completed and/or if our link
2989	* status has changed. The get_link_status flag will be set if we
2990	* receive a Link Status Change interrupt or we have Rx Sequence
2991	* Errors.
2992	*/
2993	if ((hw->media_type == e1000_media_type_copper) && hw->get_link_status) {
2994	/* First we want to see if the MII Status Register reports
2995	* link. If so, then we want to get the current speed/duplex
2996	* of the PHY.
2997	* Read the register twice since the link bit is sticky.
2998	*/
2999	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3000	if (ret_val)
3001	return ret_val;
3002	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3003	if (ret_val)
3004	return ret_val;
3005
3006	if (phy_data & MII_SR_LINK_STATUS) {
3007	hw->get_link_status = FALSE;
3008	/* Check if there was DownShift, must be checked immediately after
3009	* link-up */
3010	e1000_check_downshift(hw);
3011
3012	/* If we are on 82544 or 82543 silicon and speed/duplex
3013	* are forced to 10H or 10F, then we will implement the polarity
3014	* reversal workaround. We disable interrupts first, and upon
3015	* returning, place the devices interrupt state to its previous
3016	* value except for the link status change interrupt which will
3017	* happen due to the execution of this workaround.
3018	*/
3019
3020	if ((hw->mac_type == e1000_82544 \|\| hw->mac_type == e1000_82543) &&
3021	(!hw->autoneg) &&
3022	(hw->forced_speed_duplex == e1000_10_full \|\|
3023	hw->forced_speed_duplex == e1000_10_half)) {
3024	E1000_WRITE_REG(hw, IMC, 0xffffffff);
3025	ret_val = e1000_polarity_reversal_workaround(hw);
3026	icr = E1000_READ_REG(hw, ICR);
3027	E1000_WRITE_REG(hw, ICS, (icr & ~E1000_ICS_LSC));
3028	E1000_WRITE_REG(hw, IMS, IMS_ENABLE_MASK);
3029	}
3030
3031	} else {
3032	/* No link detected */
3033	e1000_config_dsp_after_link_change(hw, FALSE);
3034	return 0;
3035	}
3036
3037	/* If we are forcing speed/duplex, then we simply return since
3038	* we have already determined whether we have link or not.
3039	*/
3040	if (!hw->autoneg) return -E1000_ERR_CONFIG;
3041
3042	/* optimize the dsp settings for the igp phy */
3043	e1000_config_dsp_after_link_change(hw, TRUE);
3044
3045	/* We have a M88E1000 PHY and Auto-Neg is enabled. If we
3046	* have Si on board that is 82544 or newer, Auto
3047	* Speed Detection takes care of MAC speed/duplex
3048	* configuration. So we only need to configure Collision
3049	* Distance in the MAC. Otherwise, we need to force
3050	* speed/duplex on the MAC to the current PHY speed/duplex
3051	* settings.
3052	*/
3053	if (hw->mac_type >= e1000_82544)
3054	e1000_config_collision_dist(hw);
3055	else {
3056	ret_val = e1000_config_mac_to_phy(hw);
3057	if (ret_val) {
3058	DEBUGOUT("Error configuring MAC to PHY settings\n");
3059	return ret_val;
3060	}
3061	}
3062
3063	/* Configure Flow Control now that Auto-Neg has completed. First, we
3064	* need to restore the desired flow control settings because we may
3065	* have had to re-autoneg with a different link partner.
3066	*/
3067	ret_val = e1000_config_fc_after_link_up(hw);
3068	if (ret_val) {
3069	DEBUGOUT("Error configuring flow control\n");
3070	return ret_val;
3071	}
3072
3073	/* At this point we know that we are on copper and we have
3074	* auto-negotiated link. These are conditions for checking the link
3075	* partner capability register. We use the link speed to determine if
3076	* TBI compatibility needs to be turned on or off. If the link is not
3077	* at gigabit speed, then TBI compatibility is not needed. If we are
3078	* at gigabit speed, we turn on TBI compatibility.
3079	*/
3080	if (hw->tbi_compatibility_en) {
3081	uint16_t speed, duplex;
3082	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
3083	if (ret_val) {
3084	DEBUGOUT("Error getting link speed and duplex\n");
3085	return ret_val;
3086	}
3087	if (speed != SPEED_1000) {
3088	/* If link speed is not set to gigabit speed, we do not need
3089	* to enable TBI compatibility.
3090	*/
3091	if (hw->tbi_compatibility_on) {
3092	/* If we previously were in the mode, turn it off. */
3093	rctl = E1000_READ_REG(hw, RCTL);
3094	rctl &= ~E1000_RCTL_SBP;
3095	E1000_WRITE_REG(hw, RCTL, rctl);
3096	hw->tbi_compatibility_on = FALSE;
3097	}
3098	} else {
3099	/* If TBI compatibility is was previously off, turn it on. For
3100	* compatibility with a TBI link partner, we will store bad
3101	* packets. Some frames have an additional byte on the end and
3102	* will look like CRC errors to to the hardware.
3103	*/
3104	if (!hw->tbi_compatibility_on) {
3105	hw->tbi_compatibility_on = TRUE;
3106	rctl = E1000_READ_REG(hw, RCTL);
3107	rctl \|= E1000_RCTL_SBP;
3108	E1000_WRITE_REG(hw, RCTL, rctl);
3109	}
3110	}
3111	}
3112	}
3113	/* If we don't have link (auto-negotiation failed or link partner cannot
3114	* auto-negotiate), the cable is plugged in (we have signal), and our
3115	* link partner is not trying to auto-negotiate with us (we are receiving
3116	* idles or data), we need to force link up. We also need to give
3117	* auto-negotiation time to complete, in case the cable was just plugged
3118	* in. The autoneg_failed flag does this.
3119	*/
3120	else if ((((hw->media_type == e1000_media_type_fiber) &&
3121	((ctrl & E1000_CTRL_SWDPIN1) == signal)) \|\|
3122	(hw->media_type == e1000_media_type_internal_serdes)) &&
3123	(!(status & E1000_STATUS_LU)) &&
3124	(!(rxcw & E1000_RXCW_C))) {
3125	if (hw->autoneg_failed == 0) {
3126	hw->autoneg_failed = 1;
3127	return 0;
3128	}
3129	DEBUGOUT("NOT RXing /C/, disable AutoNeg and force link.\n");
3130
3131	/* Disable auto-negotiation in the TXCW register */
3132	E1000_WRITE_REG(hw, TXCW, (hw->txcw & ~E1000_TXCW_ANE));
3133
3134	/* Force link-up and also force full-duplex. */
3135	ctrl = E1000_READ_REG(hw, CTRL);
3136	ctrl \|= (E1000_CTRL_SLU \| E1000_CTRL_FD);
3137	E1000_WRITE_REG(hw, CTRL, ctrl);
3138
3139	/* Configure Flow Control after forcing link up. */
3140	ret_val = e1000_config_fc_after_link_up(hw);
3141	if (ret_val) {
3142	DEBUGOUT("Error configuring flow control\n");
3143	return ret_val;
3144	}
3145	}
3146	/* If we are forcing link and we are receiving /C/ ordered sets, re-enable
3147	* auto-negotiation in the TXCW register and disable forced link in the
3148	* Device Control register in an attempt to auto-negotiate with our link
3149	* partner.
3150	*/
3151	else if (((hw->media_type == e1000_media_type_fiber) \|\|
3152	(hw->media_type == e1000_media_type_internal_serdes)) &&
3153	(ctrl & E1000_CTRL_SLU) && (rxcw & E1000_RXCW_C)) {
3154	DEBUGOUT("RXing /C/, enable AutoNeg and stop forcing link.\n");
3155	E1000_WRITE_REG(hw, TXCW, hw->txcw);
3156	E1000_WRITE_REG(hw, CTRL, (ctrl & ~E1000_CTRL_SLU));
3157
3158	hw->serdes_link_down = FALSE;
3159	}
3160	/* If we force link for non-auto-negotiation switch, check link status
3161	* based on MAC synchronization for internal serdes media type.
3162	*/
3163	else if ((hw->media_type == e1000_media_type_internal_serdes) &&
3164	!(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3165	/* SYNCH bit and IV bit are sticky. */
3166	udelay(10);
3167	if (E1000_RXCW_SYNCH & E1000_READ_REG(hw, RXCW)) {
3168	if (!(rxcw & E1000_RXCW_IV)) {
3169	hw->serdes_link_down = FALSE;
3170	DEBUGOUT("SERDES: Link is up.\n");
3171	}
3172	} else {
3173	hw->serdes_link_down = TRUE;
3174	DEBUGOUT("SERDES: Link is down.\n");
3175	}
3176	}
3177	if ((hw->media_type == e1000_media_type_internal_serdes) &&
3178	(E1000_TXCW_ANE & E1000_READ_REG(hw, TXCW))) {
3179	hw->serdes_link_down = !(E1000_STATUS_LU & E1000_READ_REG(hw, STATUS));
3180	}
3181	return E1000_SUCCESS;
3182	}
3183
3184	/******************************************************************************
3185	* Detects the current speed and duplex settings of the hardware.
3186	*
3187	* hw - Struct containing variables accessed by shared code
3188	* speed - Speed of the connection
3189	* duplex - Duplex setting of the connection
3190	*****************************************************************************/
3191	int32_t
3192	e1000_get_speed_and_duplex(struct e1000_hw *hw,
3193	uint16_t *speed,
3194	uint16_t *duplex)
3195	{
3196	uint32_t status;
3197	int32_t ret_val;
3198	uint16_t phy_data;
3199
3200	DEBUGFUNC("e1000_get_speed_and_duplex");
3201
3202	if (hw->mac_type >= e1000_82543) {
3203	status = E1000_READ_REG(hw, STATUS);
3204	if (status & E1000_STATUS_SPEED_1000) {
3205	*speed = SPEED_1000;
3206	DEBUGOUT("1000 Mbs, ");
3207	} else if (status & E1000_STATUS_SPEED_100) {
3208	*speed = SPEED_100;
3209	DEBUGOUT("100 Mbs, ");
3210	} else {
3211	*speed = SPEED_10;
3212	DEBUGOUT("10 Mbs, ");
3213	}
3214
3215	if (status & E1000_STATUS_FD) {
3216	*duplex = FULL_DUPLEX;
3217	DEBUGOUT("Full Duplex\n");
3218	} else {
3219	*duplex = HALF_DUPLEX;
3220	DEBUGOUT(" Half Duplex\n");
3221	}
3222	} else {
3223	DEBUGOUT("1000 Mbs, Full Duplex\n");
3224	*speed = SPEED_1000;
3225	*duplex = FULL_DUPLEX;
3226	}
3227
3228	/* IGP01 PHY may advertise full duplex operation after speed downgrade even
3229	* if it is operating at half duplex. Here we set the duplex settings to
3230	* match the duplex in the link partner's capabilities.
3231	*/
3232	if (hw->phy_type == e1000_phy_igp && hw->speed_downgraded) {
3233	ret_val = e1000_read_phy_reg(hw, PHY_AUTONEG_EXP, &phy_data);
3234	if (ret_val)
3235	return ret_val;
3236
3237	if (!(phy_data & NWAY_ER_LP_NWAY_CAPS))
3238	*duplex = HALF_DUPLEX;
3239	else {
3240	ret_val = e1000_read_phy_reg(hw, PHY_LP_ABILITY, &phy_data);
3241	if (ret_val)
3242	return ret_val;
3243	if ((*speed == SPEED_100 && !(phy_data & NWAY_LPAR_100TX_FD_CAPS)) \|\|
3244	(*speed == SPEED_10 && !(phy_data & NWAY_LPAR_10T_FD_CAPS)))
3245	*duplex = HALF_DUPLEX;
3246	}
3247	}
3248
3249	if ((hw->mac_type == e1000_80003es2lan) &&
3250	(hw->media_type == e1000_media_type_copper)) {
3251	if (*speed == SPEED_1000)
3252	ret_val = e1000_configure_kmrn_for_1000(hw);
3253	else
3254	ret_val = e1000_configure_kmrn_for_10_100(hw, *duplex);
3255	if (ret_val)
3256	return ret_val;
3257	}
3258
3259	if ((hw->phy_type == e1000_phy_igp_3) && (*speed == SPEED_1000)) {
3260	ret_val = e1000_kumeran_lock_loss_workaround(hw);
3261	if (ret_val)
3262	return ret_val;
3263	}
3264
3265	return E1000_SUCCESS;
3266	}
3267
3268	/******************************************************************************
3269	* Blocks until autoneg completes or times out (~4.5 seconds)
3270	*
3271	* hw - Struct containing variables accessed by shared code
3272	******************************************************************************/
3273	static int32_t
3274	e1000_wait_autoneg(struct e1000_hw *hw)
3275	{
3276	int32_t ret_val;
3277	uint16_t i;
3278	uint16_t phy_data;
3279
3280	DEBUGFUNC("e1000_wait_autoneg");
3281	DEBUGOUT("Waiting for Auto-Neg to complete.\n");
3282
3283	/* We will wait for autoneg to complete or 4.5 seconds to expire. */
3284	for (i = PHY_AUTO_NEG_TIME; i > 0; i--) {
3285	/* Read the MII Status Register and wait for Auto-Neg
3286	* Complete bit to be set.
3287	*/
3288	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3289	if (ret_val)
3290	return ret_val;
3291	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
3292	if (ret_val)
3293	return ret_val;
3294	if (phy_data & MII_SR_AUTONEG_COMPLETE) {
3295	return E1000_SUCCESS;
3296	}
3297	msleep(100);
3298	}
3299	return E1000_SUCCESS;
3300	}
3301
3302	/******************************************************************************
3303	* Raises the Management Data Clock
3304	*
3305	* hw - Struct containing variables accessed by shared code
3306	* ctrl - Device control register's current value
3307	******************************************************************************/
3308	static void
3309	e1000_raise_mdi_clk(struct e1000_hw *hw,
3310	uint32_t *ctrl)
3311	{
3312	/* Raise the clock input to the Management Data Clock (by setting the MDC
3313	* bit), and then delay 10 microseconds.
3314	*/
3315	E1000_WRITE_REG(hw, CTRL, (*ctrl \| E1000_CTRL_MDC));
3316	E1000_WRITE_FLUSH(hw);
3317	udelay(10);
3318	}
3319
3320	/******************************************************************************
3321	* Lowers the Management Data Clock
3322	*
3323	* hw - Struct containing variables accessed by shared code
3324	* ctrl - Device control register's current value
3325	******************************************************************************/
3326	static void
3327	e1000_lower_mdi_clk(struct e1000_hw *hw,
3328	uint32_t *ctrl)
3329	{
3330	/* Lower the clock input to the Management Data Clock (by clearing the MDC
3331	* bit), and then delay 10 microseconds.
3332	*/
3333	E1000_WRITE_REG(hw, CTRL, (*ctrl & ~E1000_CTRL_MDC));
3334	E1000_WRITE_FLUSH(hw);
3335	udelay(10);
3336	}
3337
3338	/******************************************************************************
3339	* Shifts data bits out to the PHY
3340	*
3341	* hw - Struct containing variables accessed by shared code
3342	* data - Data to send out to the PHY
3343	* count - Number of bits to shift out
3344	*
3345	* Bits are shifted out in MSB to LSB order.
3346	******************************************************************************/
3347	static void
3348	e1000_shift_out_mdi_bits(struct e1000_hw *hw,
3349	uint32_t data,
3350	uint16_t count)
3351	{
3352	uint32_t ctrl;
3353	uint32_t mask;
3354
3355	/* We need to shift "count" number of bits out to the PHY. So, the value
3356	* in the "data" parameter will be shifted out to the PHY one bit at a
3357	* time. In order to do this, "data" must be broken down into bits.
3358	*/
3359	mask = 0x01;
3360	mask <<= (count - 1);
3361
3362	ctrl = E1000_READ_REG(hw, CTRL);
3363
3364	/* Set MDIO_DIR and MDC_DIR direction bits to be used as output pins. */
3365	ctrl \|= (E1000_CTRL_MDIO_DIR \| E1000_CTRL_MDC_DIR);
3366
3367	while (mask) {
3368	/* A "1" is shifted out to the PHY by setting the MDIO bit to "1" and
3369	* then raising and lowering the Management Data Clock. A "0" is
3370	* shifted out to the PHY by setting the MDIO bit to "0" and then
3371	* raising and lowering the clock.
3372	*/
3373	if (data & mask)
3374	ctrl \|= E1000_CTRL_MDIO;
3375	else
3376	ctrl &= ~E1000_CTRL_MDIO;
3377
3378	E1000_WRITE_REG(hw, CTRL, ctrl);
3379	E1000_WRITE_FLUSH(hw);
3380
3381	udelay(10);
3382
3383	e1000_raise_mdi_clk(hw, &ctrl);
3384	e1000_lower_mdi_clk(hw, &ctrl);
3385
3386	mask = mask >> 1;
3387	}
3388	}
3389
3390	/******************************************************************************
3391	* Shifts data bits in from the PHY
3392	*
3393	* hw - Struct containing variables accessed by shared code
3394	*
3395	* Bits are shifted in in MSB to LSB order.
3396	******************************************************************************/
3397	static uint16_t
3398	e1000_shift_in_mdi_bits(struct e1000_hw *hw)
3399	{
3400	uint32_t ctrl;
3401	uint16_t data = 0;
3402	uint8_t i;
3403
3404	/* In order to read a register from the PHY, we need to shift in a total
3405	* of 18 bits from the PHY. The first two bit (turnaround) times are used
3406	* to avoid contention on the MDIO pin when a read operation is performed.
3407	* These two bits are ignored by us and thrown away. Bits are "shifted in"
3408	* by raising the input to the Management Data Clock (setting the MDC bit),
3409	* and then reading the value of the MDIO bit.
3410	*/
3411	ctrl = E1000_READ_REG(hw, CTRL);
3412
3413	/* Clear MDIO_DIR (SWDPIO1) to indicate this bit is to be used as input. */
3414	ctrl &= ~E1000_CTRL_MDIO_DIR;
3415	ctrl &= ~E1000_CTRL_MDIO;
3416
3417	E1000_WRITE_REG(hw, CTRL, ctrl);
3418	E1000_WRITE_FLUSH(hw);
3419
3420	/* Raise and Lower the clock before reading in the data. This accounts for
3421	* the turnaround bits. The first clock occurred when we clocked out the
3422	* last bit of the Register Address.
3423	*/
3424	e1000_raise_mdi_clk(hw, &ctrl);
3425	e1000_lower_mdi_clk(hw, &ctrl);
3426
3427	for (data = 0, i = 0; i < 16; i++) {
3428	data = data << 1;
3429	e1000_raise_mdi_clk(hw, &ctrl);
3430	ctrl = E1000_READ_REG(hw, CTRL);
3431	/* Check to see if we shifted in a "1". */
3432	if (ctrl & E1000_CTRL_MDIO)
3433	data \|= 1;
3434	e1000_lower_mdi_clk(hw, &ctrl);
3435	}
3436
3437	e1000_raise_mdi_clk(hw, &ctrl);
3438	e1000_lower_mdi_clk(hw, &ctrl);
3439
3440	return data;
3441	}
3442
3443	static int32_t
3444	e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
3445	{
3446	uint32_t swfw_sync = 0;
3447	uint32_t swmask = mask;
3448	uint32_t fwmask = mask << 16;
3449	int32_t timeout = 200;
3450
3451	DEBUGFUNC("e1000_swfw_sync_acquire");
3452
3453	if (hw->swfwhw_semaphore_present)
3454	return e1000_get_software_flag(hw);
3455
3456	if (!hw->swfw_sync_present)
3457	return e1000_get_hw_eeprom_semaphore(hw);
3458
3459	while (timeout) {
3460	if (e1000_get_hw_eeprom_semaphore(hw))
3461	return -E1000_ERR_SWFW_SYNC;
3462
3463	swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3464	if (!(swfw_sync & (fwmask \| swmask))) {
3465	break;
3466	}
3467
3468	/* firmware currently using resource (fwmask) */
3469	/* or other software thread currently using resource (swmask) */
3470	e1000_put_hw_eeprom_semaphore(hw);
3471	mdelay(5);
3472	timeout--;
3473	}
3474
3475	if (!timeout) {
3476	DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
3477	return -E1000_ERR_SWFW_SYNC;
3478	}
3479
3480	swfw_sync \|= swmask;
3481	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3482
3483	e1000_put_hw_eeprom_semaphore(hw);
3484	return E1000_SUCCESS;
3485	}
3486
3487	static void
3488	e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
3489	{
3490	uint32_t swfw_sync;
3491	uint32_t swmask = mask;
3492
3493	DEBUGFUNC("e1000_swfw_sync_release");
3494
3495	if (hw->swfwhw_semaphore_present) {
3496	e1000_release_software_flag(hw);
3497	return;
3498	}
3499
3500	if (!hw->swfw_sync_present) {
3501	e1000_put_hw_eeprom_semaphore(hw);
3502	return;
3503	}
3504
3505	/* if (e1000_get_hw_eeprom_semaphore(hw))
3506	* return -E1000_ERR_SWFW_SYNC; */
3507	while (e1000_get_hw_eeprom_semaphore(hw) != E1000_SUCCESS);
3508	/* empty */
3509
3510	swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
3511	swfw_sync &= ~swmask;
3512	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);
3513
3514	e1000_put_hw_eeprom_semaphore(hw);
3515	}
3516
3517	/*****************************************************************************
3518	* Reads the value from a PHY register, if the value is on a specific non zero
3519	* page, sets the page first.
3520	* hw - Struct containing variables accessed by shared code
3521	* reg_addr - address of the PHY register to read
3522	******************************************************************************/
3523	int32_t
3524	e1000_read_phy_reg(struct e1000_hw *hw,
3525	uint32_t reg_addr,
3526	uint16_t *phy_data)
3527	{
3528	uint32_t ret_val;
3529	uint16_t swfw;
3530
3531	DEBUGFUNC("e1000_read_phy_reg");
3532
3533	if ((hw->mac_type == e1000_80003es2lan \|\| hw->mac_type == e1000_82576) &&
3534	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3535	swfw = E1000_SWFW_PHY1_SM;
3536	} else {
3537	swfw = E1000_SWFW_PHY0_SM;
3538	}
3539	if (e1000_swfw_sync_acquire(hw, swfw))
3540	return -E1000_ERR_SWFW_SYNC;
3541
3542	if ((hw->phy_type == e1000_phy_igp \|\|
3543	hw->phy_type == e1000_phy_igp_3 \|\|
3544	hw->phy_type == e1000_phy_igp_2) &&
3545	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3546	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3547	(uint16_t)reg_addr);
3548	if (ret_val) {
3549	e1000_swfw_sync_release(hw, swfw);
3550	return ret_val;
3551	}
3552	} else if (hw->phy_type == e1000_phy_gg82563) {
3553	if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
3554	(hw->mac_type == e1000_80003es2lan)) {
3555	/* Select Configuration Page */
3556	if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3557	ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3558	(uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3559	} else {
3560	/* Use Alternative Page Select register to access
3561	* registers 30 and 31
3562	*/
3563	ret_val = e1000_write_phy_reg_ex(hw,
3564	GG82563_PHY_PAGE_SELECT_ALT,
3565	(uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3566	}
3567
3568	if (ret_val) {
3569	e1000_swfw_sync_release(hw, swfw);
3570	return ret_val;
3571	}
3572	}
3573	}
3574
3575	ret_val = e1000_read_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3576	phy_data);
3577
3578	e1000_swfw_sync_release(hw, swfw);
3579	return ret_val;
3580	}
3581
3582	static int32_t
3583	e1000_read_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3584	uint16_t *phy_data)
3585	{
3586	uint32_t i;
3587	uint32_t mdic = 0;
3588	const uint32_t phy_addr = 1;
3589
3590	DEBUGFUNC("e1000_read_phy_reg_ex");
3591
3592	if (reg_addr > MAX_PHY_REG_ADDRESS) {
3593	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3594	return -E1000_ERR_PARAM;
3595	}
3596
3597	if (hw->mac_type > e1000_82543) {
3598	/* Set up Op-code, Phy Address, and register address in the MDI
3599	* Control register. The MAC will take care of interfacing with the
3600	* PHY to retrieve the desired data.
3601	*/
3602	mdic = ((reg_addr << E1000_MDIC_REG_SHIFT) \|
3603	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
3604	(E1000_MDIC_OP_READ));
3605
3606	E1000_WRITE_REG(hw, MDIC, mdic);
3607
3608	/* Poll the ready bit to see if the MDI read completed */
3609	for (i = 0; i < 64; i++) {
3610	udelay(50);
3611	mdic = E1000_READ_REG(hw, MDIC);
3612	if (mdic & E1000_MDIC_READY) break;
3613	}
3614	if (!(mdic & E1000_MDIC_READY)) {
3615	DEBUGOUT("MDI Read did not complete\n");
3616	return -E1000_ERR_PHY;
3617	}
3618	if (mdic & E1000_MDIC_ERROR) {
3619	DEBUGOUT("MDI Error\n");
3620	return -E1000_ERR_PHY;
3621	}
3622	*phy_data = (uint16_t) mdic;
3623	} else {
3624	/* We must first send a preamble through the MDIO pin to signal the
3625	* beginning of an MII instruction. This is done by sending 32
3626	* consecutive "1" bits.
3627	*/
3628	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3629
3630	/* Now combine the next few fields that are required for a read
3631	* operation. We use this method instead of calling the
3632	* e1000_shift_out_mdi_bits routine five different times. The format of
3633	* a MII read instruction consists of a shift out of 14 bits and is
3634	* defined as follows:
3635	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr>
3636	* followed by a shift in of 18 bits. This first two bits shifted in
3637	* are TurnAround bits used to avoid contention on the MDIO pin when a
3638	* READ operation is performed. These two bits are thrown away
3639	* followed by a shift in of 16 bits which contains the desired data.
3640	*/
3641	mdic = ((reg_addr) \| (phy_addr << 5) \|
3642	(PHY_OP_READ << 10) \| (PHY_SOF << 12));
3643
3644	e1000_shift_out_mdi_bits(hw, mdic, 14);
3645
3646	/* Now that we've shifted out the read command to the MII, we need to
3647	* "shift in" the 16-bit value (18 total bits) of the requested PHY
3648	* register address.
3649	*/
3650	*phy_data = e1000_shift_in_mdi_bits(hw);
3651	}
3652	return E1000_SUCCESS;
3653	}
3654
3655	/******************************************************************************
3656	* Writes a value to a PHY register
3657	*
3658	* hw - Struct containing variables accessed by shared code
3659	* reg_addr - address of the PHY register to write
3660	* data - data to write to the PHY
3661	******************************************************************************/
3662	int32_t
3663	e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
3664	uint16_t phy_data)
3665	{
3666	uint32_t ret_val;
3667	uint16_t swfw;
3668
3669	DEBUGFUNC("e1000_write_phy_reg");
3670
3671	if ((hw->mac_type == e1000_80003es2lan \|\| hw->mac_type == e1000_82576) &&
3672	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3673	swfw = E1000_SWFW_PHY1_SM;
3674	} else {
3675	swfw = E1000_SWFW_PHY0_SM;
3676	}
3677	if (e1000_swfw_sync_acquire(hw, swfw))
3678	return -E1000_ERR_SWFW_SYNC;
3679
3680	if ((hw->phy_type == e1000_phy_igp \|\|
3681	hw->phy_type == e1000_phy_igp_3 \|\|
3682	hw->phy_type == e1000_phy_igp_2) &&
3683	(reg_addr > MAX_PHY_MULTI_PAGE_REG)) {
3684	ret_val = e1000_write_phy_reg_ex(hw, IGP01E1000_PHY_PAGE_SELECT,
3685	(uint16_t)reg_addr);
3686	if (ret_val) {
3687	e1000_swfw_sync_release(hw, swfw);
3688	return ret_val;
3689	}
3690	} else if (hw->phy_type == e1000_phy_gg82563) {
3691	if (((reg_addr & MAX_PHY_REG_ADDRESS) > MAX_PHY_MULTI_PAGE_REG) \|\|
3692	(hw->mac_type == e1000_80003es2lan)) {
3693	/* Select Configuration Page */
3694	if ((reg_addr & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
3695	ret_val = e1000_write_phy_reg_ex(hw, GG82563_PHY_PAGE_SELECT,
3696	(uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3697	} else {
3698	/* Use Alternative Page Select register to access
3699	* registers 30 and 31
3700	*/
3701	ret_val = e1000_write_phy_reg_ex(hw,
3702	GG82563_PHY_PAGE_SELECT_ALT,
3703	(uint16_t)((uint16_t)reg_addr >> GG82563_PAGE_SHIFT));
3704	}
3705
3706	if (ret_val) {
3707	e1000_swfw_sync_release(hw, swfw);
3708	return ret_val;
3709	}
3710	}
3711	}
3712
3713	ret_val = e1000_write_phy_reg_ex(hw, MAX_PHY_REG_ADDRESS & reg_addr,
3714	phy_data);
3715
3716	e1000_swfw_sync_release(hw, swfw);
3717	return ret_val;
3718	}
3719
3720	static int32_t
3721	e1000_write_phy_reg_ex(struct e1000_hw *hw, uint32_t reg_addr,
3722	uint16_t phy_data)
3723	{
3724	uint32_t i;
3725	uint32_t mdic = 0;
3726	const uint32_t phy_addr = 1;
3727
3728	DEBUGFUNC("e1000_write_phy_reg_ex");
3729
3730	if (reg_addr > MAX_PHY_REG_ADDRESS) {
3731	DEBUGOUT1("PHY Address %d is out of range\n", reg_addr);
3732	return -E1000_ERR_PARAM;
3733	}
3734
3735	if (hw->mac_type > e1000_82543) {
3736	/* Set up Op-code, Phy Address, register address, and data intended
3737	* for the PHY register in the MDI Control register. The MAC will take
3738	* care of interfacing with the PHY to send the desired data.
3739	*/
3740	mdic = (((uint32_t) phy_data) \|
3741	(reg_addr << E1000_MDIC_REG_SHIFT) \|
3742	(phy_addr << E1000_MDIC_PHY_SHIFT) \|
3743	(E1000_MDIC_OP_WRITE));
3744
3745	E1000_WRITE_REG(hw, MDIC, mdic);
3746
3747	/* Poll the ready bit to see if the MDI read completed */
3748	for (i = 0; i < 641; i++) {
3749	udelay(5);
3750	mdic = E1000_READ_REG(hw, MDIC);
3751	if (mdic & E1000_MDIC_READY) break;
3752	}
3753	if (!(mdic & E1000_MDIC_READY)) {
3754	DEBUGOUT("MDI Write did not complete\n");
3755	return -E1000_ERR_PHY;
3756	}
3757	} else {
3758	/* We'll need to use the SW defined pins to shift the write command
3759	* out to the PHY. We first send a preamble to the PHY to signal the
3760	* beginning of the MII instruction. This is done by sending 32
3761	* consecutive "1" bits.
3762	*/
3763	e1000_shift_out_mdi_bits(hw, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
3764
3765	/* Now combine the remaining required fields that will indicate a
3766	* write operation. We use this method instead of calling the
3767	* e1000_shift_out_mdi_bits routine for each field in the command. The
3768	* format of a MII write instruction is as follows:
3769	* <Preamble><SOF><Op Code><Phy Addr><Reg Addr><Turnaround><Data>.
3770	*/
3771	mdic = ((PHY_TURNAROUND) \| (reg_addr << 2) \| (phy_addr << 7) \|
3772	(PHY_OP_WRITE << 12) \| (PHY_SOF << 14));
3773	mdic <<= 16;
3774	mdic \|= (uint32_t) phy_data;
3775
3776	e1000_shift_out_mdi_bits(hw, mdic, 32);
3777	}
3778
3779	return E1000_SUCCESS;
3780	}
3781
3782	static int32_t
3783	e1000_read_kmrn_reg(struct e1000_hw *hw,
3784	uint32_t reg_addr,
3785	uint16_t *data)
3786	{
3787	uint32_t reg_val;
3788	uint16_t swfw;
3789	DEBUGFUNC("e1000_read_kmrn_reg");
3790
3791	if ((hw->mac_type == e1000_80003es2lan \|\| hw->mac_type == e1000_82576) &&
3792	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3793	swfw = E1000_SWFW_PHY1_SM;
3794	} else {
3795	swfw = E1000_SWFW_PHY0_SM;
3796	}
3797	if (e1000_swfw_sync_acquire(hw, swfw))
3798	return -E1000_ERR_SWFW_SYNC;
3799
3800	/* Write register address */
3801	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3802	E1000_KUMCTRLSTA_OFFSET) \|
3803	E1000_KUMCTRLSTA_REN;
3804	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3805	udelay(2);
3806
3807	/* Read the data returned */
3808	reg_val = E1000_READ_REG(hw, KUMCTRLSTA);
3809	*data = (uint16_t)reg_val;
3810
3811	e1000_swfw_sync_release(hw, swfw);
3812	return E1000_SUCCESS;
3813	}
3814
3815	static int32_t
3816	e1000_write_kmrn_reg(struct e1000_hw *hw,
3817	uint32_t reg_addr,
3818	uint16_t data)
3819	{
3820	uint32_t reg_val;
3821	uint16_t swfw;
3822	DEBUGFUNC("e1000_write_kmrn_reg");
3823
3824	if ((hw->mac_type == e1000_80003es2lan \|\| hw->mac_type == e1000_82576) &&
3825	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3826	swfw = E1000_SWFW_PHY1_SM;
3827	} else {
3828	swfw = E1000_SWFW_PHY0_SM;
3829	}
3830	if (e1000_swfw_sync_acquire(hw, swfw))
3831	return -E1000_ERR_SWFW_SYNC;
3832
3833	reg_val = ((reg_addr << E1000_KUMCTRLSTA_OFFSET_SHIFT) &
3834	E1000_KUMCTRLSTA_OFFSET) \| data;
3835	E1000_WRITE_REG(hw, KUMCTRLSTA, reg_val);
3836	udelay(2);
3837
3838	e1000_swfw_sync_release(hw, swfw);
3839	return E1000_SUCCESS;
3840	}
3841
3842	/******************************************************************************
3843	* Returns the PHY to the power-on reset state
3844	*
3845	* hw - Struct containing variables accessed by shared code
3846	******************************************************************************/
3847	int32_t
3848	e1000_phy_hw_reset(struct e1000_hw *hw)
3849	{
3850	uint32_t ctrl, ctrl_ext;
3851	uint32_t led_ctrl;
3852	int32_t ret_val;
3853	uint16_t swfw;
3854
3855	DEBUGFUNC("e1000_phy_hw_reset");
3856
3857	/* In the case of the phy reset being blocked, it's not an error, we
3858	* simply return success without performing the reset. */
3859	ret_val = e1000_check_phy_reset_block(hw);
3860	if (ret_val)
3861	return E1000_SUCCESS;
3862
3863	DEBUGOUT("Resetting Phy...\n");
3864
3865	if (hw->mac_type > e1000_82543) {
3866	if ((hw->mac_type == e1000_80003es2lan \|\|
3867	hw->mac_type == e1000_82576) &&
3868	(E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)) {
3869	swfw = E1000_SWFW_PHY1_SM;
3870	} else {
3871	swfw = E1000_SWFW_PHY0_SM;
3872	}
3873	if (e1000_swfw_sync_acquire(hw, swfw)) {
3874	DEBUGOUT("Unable to acquire swfw sync\n");
3875	return -E1000_ERR_SWFW_SYNC;
3876	}
3877	/* Read the device control register and assert the E1000_CTRL_PHY_RST
3878	* bit. Then, take it out of reset.
3879	* For pre-e1000_82571 hardware, we delay for 10ms between the assert
3880	* and deassert. For e1000_82571 hardware and later, we instead delay
3881	* for 50us between and 10ms after the deassertion.
3882	*/
3883	ctrl = E1000_READ_REG(hw, CTRL);
3884	E1000_WRITE_REG(hw, CTRL, ctrl \| E1000_CTRL_PHY_RST);
3885	E1000_WRITE_FLUSH(hw);
3886
3887	if (hw->mac_type < e1000_82571)
3888	msleep(10);
3889	else
3890	udelay(100);
3891
3892	E1000_WRITE_REG(hw, CTRL, ctrl);
3893	E1000_WRITE_FLUSH(hw);
3894
3895	if (hw->mac_type >= e1000_82571)
3896	mdelay(10);
3897
3898	e1000_swfw_sync_release(hw, swfw);
3899	} else {
3900	/* Read the Extended Device Control Register, assert the PHY_RESET_DIR
3901	* bit to put the PHY into reset. Then, take it out of reset.
3902	*/
3903	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
3904	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DIR;
3905	ctrl_ext &= ~E1000_CTRL_EXT_SDP4_DATA;
3906	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3907	E1000_WRITE_FLUSH(hw);
3908	msleep(10);
3909	ctrl_ext \|= E1000_CTRL_EXT_SDP4_DATA;
3910	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
3911	E1000_WRITE_FLUSH(hw);
3912	}
3913	udelay(150);
3914
3915	if ((hw->mac_type == e1000_82541) \|\| (hw->mac_type == e1000_82547)) {
3916	/* Configure activity LED after PHY reset */
3917	led_ctrl = E1000_READ_REG(hw, LEDCTL);
3918	led_ctrl &= IGP_ACTIVITY_LED_MASK;
3919	led_ctrl \|= (IGP_ACTIVITY_LED_ENABLE \| IGP_LED3_MODE);
3920	E1000_WRITE_REG(hw, LEDCTL, led_ctrl);
3921	}
3922
3923	/* Wait for FW to finish PHY configuration. */
3924	ret_val = e1000_get_phy_cfg_done(hw);
3925	if (ret_val != E1000_SUCCESS)
3926	return ret_val;
3927	e1000_release_software_semaphore(hw);
3928
3929	if ((hw->mac_type == e1000_ich8lan) && (hw->phy_type == e1000_phy_igp_3))
3930	ret_val = e1000_init_lcd_from_nvm(hw);
3931
3932	return ret_val;
3933	}
3934
3935	/******************************************************************************
3936	* Resets the PHY
3937	*
3938	* hw - Struct containing variables accessed by shared code
3939	*
3940	* Sets bit 15 of the MII Control register
3941	******************************************************************************/
3942	int32_t
3943	e1000_phy_reset(struct e1000_hw *hw)
3944	{
3945	int32_t ret_val;
3946	uint16_t phy_data;
3947
3948	DEBUGFUNC("e1000_phy_reset");
3949
3950	/* In the case of the phy reset being blocked, it's not an error, we
3951	* simply return success without performing the reset. */
3952	ret_val = e1000_check_phy_reset_block(hw);
3953	if (ret_val)
3954	return E1000_SUCCESS;
3955
3956	switch (hw->phy_type) {
3957	case e1000_phy_igp:
3958	case e1000_phy_igp_2:
3959	case e1000_phy_igp_3:
3960	case e1000_phy_ife:
3961	ret_val = e1000_phy_hw_reset(hw);
3962	if (ret_val)
3963	return ret_val;
3964	break;
3965	default:
3966	ret_val = e1000_read_phy_reg(hw, PHY_CTRL, &phy_data);
3967	if (ret_val)
3968	return ret_val;
3969
3970	phy_data \|= MII_CR_RESET;
3971	ret_val = e1000_write_phy_reg(hw, PHY_CTRL, phy_data);
3972	if (ret_val)
3973	return ret_val;
3974
3975	udelay(1);
3976	break;
3977	}
3978
3979	if (hw->phy_type == e1000_phy_igp \|\| hw->phy_type == e1000_phy_igp_2)
3980	e1000_phy_init_script(hw);
3981
3982	return E1000_SUCCESS;
3983	}
3984
3985	/******************************************************************************
3986	* Work-around for 82566 power-down: on D3 entry-
3987	* 1) disable gigabit link
3988	* 2) write VR power-down enable
3989	* 3) read it back
3990	* if successful continue, else issue LCD reset and repeat
3991	*
3992	* hw - struct containing variables accessed by shared code
3993	******************************************************************************/
3994	void
3995	e1000_phy_powerdown_workaround(struct e1000_hw *hw)
3996	{
3997	int32_t reg;
3998	uint16_t phy_data;
3999	int32_t retry = 0;
4000
4001	DEBUGFUNC("e1000_phy_powerdown_workaround");
4002
4003	if (hw->phy_type != e1000_phy_igp_3)
4004	return;
4005
4006	do {
4007	/* Disable link */
4008	reg = E1000_READ_REG(hw, PHY_CTRL);
4009	E1000_WRITE_REG(hw, PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
4010	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4011
4012	/* Write VR power-down enable - bits 9:8 should be 10b */
4013	e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
4014	phy_data \|= (1 << 9);
4015	phy_data &= ~(1 << 8);
4016	e1000_write_phy_reg(hw, IGP3_VR_CTRL, phy_data);
4017
4018	/* Read it back and test */
4019	e1000_read_phy_reg(hw, IGP3_VR_CTRL, &phy_data);
4020	if (((phy_data & IGP3_VR_CTRL_MODE_MASK) == IGP3_VR_CTRL_MODE_SHUT) \|\| retry)
4021	break;
4022
4023	/* Issue PHY reset and repeat at most one more time */
4024	reg = E1000_READ_REG(hw, CTRL);
4025	E1000_WRITE_REG(hw, CTRL, reg \| E1000_CTRL_PHY_RST);
4026	retry++;
4027	} while (retry);
4028
4029	return;
4030
4031	}
4032
4033	/******************************************************************************
4034	* Work-around for 82566 Kumeran PCS lock loss:
4035	* On link status change (i.e. PCI reset, speed change) and link is up and
4036	* speed is gigabit-
4037	* 0) if workaround is optionally disabled do nothing
4038	* 1) wait 1ms for Kumeran link to come up
4039	* 2) check Kumeran Diagnostic register PCS lock loss bit
4040	* 3) if not set the link is locked (all is good), otherwise...
4041	* 4) reset the PHY
4042	* 5) repeat up to 10 times
4043	* Note: this is only called for IGP3 copper when speed is 1gb.
4044	*
4045	* hw - struct containing variables accessed by shared code
4046	******************************************************************************/
4047	static int32_t
4048	e1000_kumeran_lock_loss_workaround(struct e1000_hw *hw)
4049	{
4050	int32_t ret_val;
4051	int32_t reg;
4052	int32_t cnt;
4053	uint16_t phy_data;
4054
4055	if (hw->kmrn_lock_loss_workaround_disabled)
4056	return E1000_SUCCESS;
4057
4058	/* Make sure link is up before proceeding. If not just return.
4059	* Attempting this while link is negotiating fouled up link
4060	* stability */
4061	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4062	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4063
4064	if (phy_data & MII_SR_LINK_STATUS) {
4065	for (cnt = 0; cnt < 10; cnt++) {
4066	/* read once to clear */
4067	ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4068	if (ret_val)
4069	return ret_val;
4070	/* and again to get new status */
4071	ret_val = e1000_read_phy_reg(hw, IGP3_KMRN_DIAG, &phy_data);
4072	if (ret_val)
4073	return ret_val;
4074
4075	/* check for PCS lock */
4076	if (!(phy_data & IGP3_KMRN_DIAG_PCS_LOCK_LOSS))
4077	return E1000_SUCCESS;
4078
4079	/* Issue PHY reset */
4080	e1000_phy_hw_reset(hw);
4081	mdelay(5);
4082	}
4083	/* Disable GigE link negotiation */
4084	reg = E1000_READ_REG(hw, PHY_CTRL);
4085	E1000_WRITE_REG(hw, PHY_CTRL, reg \| E1000_PHY_CTRL_GBE_DISABLE \|
4086	E1000_PHY_CTRL_NOND0A_GBE_DISABLE);
4087
4088	/* unable to acquire PCS lock */
4089	return E1000_ERR_PHY;
4090	}
4091
4092	return E1000_SUCCESS;
4093	}
4094
4095	/******************************************************************************
4096	* Probes the expected PHY address for known PHY IDs
4097	*
4098	* hw - Struct containing variables accessed by shared code
4099	******************************************************************************/
4100	static int32_t
4101	e1000_detect_gig_phy(struct e1000_hw *hw)
4102	{
4103	int32_t phy_init_status, ret_val;
4104	uint16_t phy_id_high, phy_id_low;
4105	boolean_t match = FALSE;
4106
4107	DEBUGFUNC("e1000_detect_gig_phy");
4108
4109	if (hw->phy_id != 0)
4110	return E1000_SUCCESS;
4111
4112	/* The 82571 firmware may still be configuring the PHY. In this
4113	* case, we cannot access the PHY until the configuration is done. So
4114	* we explicitly set the PHY values. */
4115	if (hw->mac_type == e1000_82571 \|\|
4116	hw->mac_type == e1000_82572) {
4117	hw->phy_id = IGP01E1000_I_PHY_ID;
4118	hw->phy_type = e1000_phy_igp_2;
4119	return E1000_SUCCESS;
4120	}
4121
4122	/* ESB-2 PHY reads require e1000_phy_gg82563 to be set because of a work-
4123	* around that forces PHY page 0 to be set or the reads fail. The rest of
4124	* the code in this routine uses e1000_read_phy_reg to read the PHY ID.
4125	* So for ESB-2 we need to have this set so our reads won't fail. If the
4126	* attached PHY is not a e1000_phy_gg82563, the routines below will figure
4127	* this out as well. */
4128	if (hw->mac_type == e1000_80003es2lan)
4129	hw->phy_type = e1000_phy_gg82563;
4130
4131	/* Read the PHY ID Registers to identify which PHY is onboard. */
4132	ret_val = e1000_read_phy_reg(hw, PHY_ID1, &phy_id_high);
4133	if (ret_val)
4134	return ret_val;
4135
4136	hw->phy_id = (uint32_t) (phy_id_high << 16);
4137	udelay(20);
4138	ret_val = e1000_read_phy_reg(hw, PHY_ID2, &phy_id_low);
4139	if (ret_val)
4140	return ret_val;
4141
4142	hw->phy_id \|= (uint32_t) (phy_id_low & PHY_REVISION_MASK);
4143	hw->phy_revision = (uint32_t) phy_id_low & ~PHY_REVISION_MASK;
4144
4145	switch (hw->mac_type) {
4146	case e1000_82543:
4147	if (hw->phy_id == M88E1000_E_PHY_ID) match = TRUE;
4148	break;
4149	case e1000_82544:
4150	if (hw->phy_id == M88E1000_I_PHY_ID) match = TRUE;
4151	break;
4152	case e1000_82540:
4153	case e1000_82545:
4154	case e1000_82545_rev_3:
4155	case e1000_82546:
4156	case e1000_82546_rev_3:
4157	if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE;
4158	break;
4159	case e1000_82541:
4160	case e1000_82541_rev_2:
4161	case e1000_82547:
4162	case e1000_82547_rev_2:
4163	if (hw->phy_id == IGP01E1000_I_PHY_ID) match = TRUE;
4164	break;
4165	case e1000_82573:
4166	if (hw->phy_id == M88E1111_I_PHY_ID) match = TRUE;
4167	break;
4168	case e1000_80003es2lan:
4169	if (hw->phy_id == GG82563_E_PHY_ID) match = TRUE;
4170	break;
4171	case e1000_ich8lan:
4172	if (hw->phy_id == IGP03E1000_E_PHY_ID) match = TRUE;
4173	if (hw->phy_id == IFE_E_PHY_ID) match = TRUE;
4174	if (hw->phy_id == IFE_PLUS_E_PHY_ID) match = TRUE;
4175	if (hw->phy_id == IFE_C_E_PHY_ID) match = TRUE;
4176	break;
4177	case e1000_82576:
4178	match = TRUE;
4179	break;
4180	default:
4181	DEBUGOUT1("Invalid MAC type %d\n", hw->mac_type);
4182	return -E1000_ERR_CONFIG;
4183	}
4184	phy_init_status = e1000_set_phy_type(hw);
4185
4186	if ((match) && (phy_init_status == E1000_SUCCESS)) {
4187	DEBUGOUT1("PHY ID %#08x detected\n", hw->phy_id);
4188	return E1000_SUCCESS;
4189	}
4190	DEBUGOUT1("Invalid PHY ID %#08x\n", hw->phy_id);
4191	return -E1000_ERR_PHY;
4192	}
4193
4194	/******************************************************************************
4195	* Resets the PHY's DSP
4196	*
4197	* hw - Struct containing variables accessed by shared code
4198	******************************************************************************/
4199	static int32_t
4200	e1000_phy_reset_dsp(struct e1000_hw *hw)
4201	{
4202	int32_t ret_val;
4203	DEBUGFUNC("e1000_phy_reset_dsp");
4204
4205	do {
4206	if (hw->phy_type != e1000_phy_gg82563) {
4207	ret_val = e1000_write_phy_reg(hw, 29, 0x001d);
4208	if (ret_val) break;
4209	}
4210	ret_val = e1000_write_phy_reg(hw, 30, 0x00c1);
4211	if (ret_val) break;
4212	ret_val = e1000_write_phy_reg(hw, 30, 0x0000);
4213	if (ret_val) break;
4214	ret_val = E1000_SUCCESS;
4215	} while (0);
4216
4217	return ret_val;
4218	}
4219
4220	/******************************************************************************
4221	* Get PHY information from various PHY registers for igp PHY only.
4222	*
4223	* hw - Struct containing variables accessed by shared code
4224	* phy_info - PHY information structure
4225	******************************************************************************/
4226	static int32_t
4227	e1000_phy_igp_get_info(struct e1000_hw *hw,
4228	struct e1000_phy_info *phy_info)
4229	{
4230	int32_t ret_val;
4231	uint16_t phy_data, min_length, max_length, average;
4232	e1000_rev_polarity polarity;
4233
4234	DEBUGFUNC("e1000_phy_igp_get_info");
4235
4236	/* The downshift status is checked only once, after link is established,
4237	* and it stored in the hw->speed_downgraded parameter. */
4238	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4239
4240	/* IGP01E1000 does not need to support it. */
4241	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4242
4243	/* IGP01E1000 always correct polarity reversal */
4244	phy_info->polarity_correction = e1000_polarity_reversal_enabled;
4245
4246	/* Check polarity status */
4247	ret_val = e1000_check_polarity(hw, &polarity);
4248	if (ret_val)
4249	return ret_val;
4250
4251	phy_info->cable_polarity = polarity;
4252
4253	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS, &phy_data);
4254	if (ret_val)
4255	return ret_val;
4256
4257	phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & IGP01E1000_PSSR_MDIX) >>
4258	IGP01E1000_PSSR_MDIX_SHIFT);
4259
4260	if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
4261	IGP01E1000_PSSR_SPEED_1000MBPS) {
4262	/* Local/Remote Receiver Information are only valid at 1000 Mbps */
4263	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4264	if (ret_val)
4265	return ret_val;
4266
4267	phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4268	SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4269	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4270	phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4271	SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4272	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4273
4274	/* Get cable length */
4275	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
4276	if (ret_val)
4277	return ret_val;
4278
4279	/* Translate to old method */
4280	average = (max_length + min_length) / 2;
4281
4282	if (average <= e1000_igp_cable_length_50)
4283	phy_info->cable_length = e1000_cable_length_50;
4284	else if (average <= e1000_igp_cable_length_80)
4285	phy_info->cable_length = e1000_cable_length_50_80;
4286	else if (average <= e1000_igp_cable_length_110)
4287	phy_info->cable_length = e1000_cable_length_80_110;
4288	else if (average <= e1000_igp_cable_length_140)
4289	phy_info->cable_length = e1000_cable_length_110_140;
4290	else
4291	phy_info->cable_length = e1000_cable_length_140;
4292	}
4293
4294	return E1000_SUCCESS;
4295	}
4296
4297	/******************************************************************************
4298	* Get PHY information from various PHY registers for ife PHY only.
4299	*
4300	* hw - Struct containing variables accessed by shared code
4301	* phy_info - PHY information structure
4302	******************************************************************************/
4303	static int32_t
4304	e1000_phy_ife_get_info(struct e1000_hw *hw,
4305	struct e1000_phy_info *phy_info)
4306	{
4307	int32_t ret_val;
4308	uint16_t phy_data;
4309	e1000_rev_polarity polarity;
4310
4311	DEBUGFUNC("e1000_phy_ife_get_info");
4312
4313	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4314	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_normal;
4315
4316	ret_val = e1000_read_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL, &phy_data);
4317	if (ret_val)
4318	return ret_val;
4319	phy_info->polarity_correction =
4320	((phy_data & IFE_PSC_AUTO_POLARITY_DISABLE) >>
4321	IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT) ?
4322	e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4323
4324	if (phy_info->polarity_correction == e1000_polarity_reversal_enabled) {
4325	ret_val = e1000_check_polarity(hw, &polarity);
4326	if (ret_val)
4327	return ret_val;
4328	} else {
4329	/* Polarity is forced. */
4330	polarity = ((phy_data & IFE_PSC_FORCE_POLARITY) >>
4331	IFE_PSC_FORCE_POLARITY_SHIFT) ?
4332	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
4333	}
4334	phy_info->cable_polarity = polarity;
4335
4336	ret_val = e1000_read_phy_reg(hw, IFE_PHY_MDIX_CONTROL, &phy_data);
4337	if (ret_val)
4338	return ret_val;
4339
4340	phy_info->mdix_mode = (e1000_auto_x_mode)
4341	((phy_data & (IFE_PMC_AUTO_MDIX \| IFE_PMC_FORCE_MDIX)) >>
4342	IFE_PMC_MDIX_MODE_SHIFT);
4343
4344	return E1000_SUCCESS;
4345	}
4346
4347	/******************************************************************************
4348	* Get PHY information from various PHY registers fot m88 PHY only.
4349	*
4350	* hw - Struct containing variables accessed by shared code
4351	* phy_info - PHY information structure
4352	******************************************************************************/
4353	static int32_t
4354	e1000_phy_m88_get_info(struct e1000_hw *hw,
4355	struct e1000_phy_info *phy_info)
4356	{
4357	int32_t ret_val;
4358	uint16_t phy_data;
4359	e1000_rev_polarity polarity;
4360
4361	DEBUGFUNC("e1000_phy_m88_get_info");
4362
4363	/* The downshift status is checked only once, after link is established,
4364	* and it stored in the hw->speed_downgraded parameter. */
4365	phy_info->downshift = (e1000_downshift)hw->speed_downgraded;
4366
4367	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
4368	if (ret_val)
4369	return ret_val;
4370
4371	phy_info->extended_10bt_distance =
4372	((phy_data & M88E1000_PSCR_10BT_EXT_DIST_ENABLE) >>
4373	M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT) ?
4374	e1000_10bt_ext_dist_enable_lower : e1000_10bt_ext_dist_enable_normal;
4375
4376	phy_info->polarity_correction =
4377	((phy_data & M88E1000_PSCR_POLARITY_REVERSAL) >>
4378	M88E1000_PSCR_POLARITY_REVERSAL_SHIFT) ?
4379	e1000_polarity_reversal_disabled : e1000_polarity_reversal_enabled;
4380
4381	/* Check polarity status */
4382	ret_val = e1000_check_polarity(hw, &polarity);
4383	if (ret_val)
4384	return ret_val;
4385	phy_info->cable_polarity = polarity;
4386
4387	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS, &phy_data);
4388	if (ret_val)
4389	return ret_val;
4390
4391	phy_info->mdix_mode = (e1000_auto_x_mode)((phy_data & M88E1000_PSSR_MDIX) >>
4392	M88E1000_PSSR_MDIX_SHIFT);
4393
4394	if ((phy_data & M88E1000_PSSR_SPEED) == M88E1000_PSSR_1000MBS) {
4395	/* Cable Length Estimation and Local/Remote Receiver Information
4396	* are only valid at 1000 Mbps.
4397	*/
4398	if (hw->phy_type != e1000_phy_gg82563) {
4399	phy_info->cable_length = (e1000_cable_length)((phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
4400	M88E1000_PSSR_CABLE_LENGTH_SHIFT);
4401	} else {
4402	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
4403	&phy_data);
4404	if (ret_val)
4405	return ret_val;
4406
4407	phy_info->cable_length = (e1000_cable_length)(phy_data & GG82563_DSPD_CABLE_LENGTH);
4408	}
4409
4410	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS, &phy_data);
4411	if (ret_val)
4412	return ret_val;
4413
4414	phy_info->local_rx = ((phy_data & SR_1000T_LOCAL_RX_STATUS) >>
4415	SR_1000T_LOCAL_RX_STATUS_SHIFT) ?
4416	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4417	phy_info->remote_rx = ((phy_data & SR_1000T_REMOTE_RX_STATUS) >>
4418	SR_1000T_REMOTE_RX_STATUS_SHIFT) ?
4419	e1000_1000t_rx_status_ok : e1000_1000t_rx_status_not_ok;
4420
4421	}
4422
4423	return E1000_SUCCESS;
4424	}
4425
4426	/******************************************************************************
4427	* Get PHY information from various PHY registers
4428	*
4429	* hw - Struct containing variables accessed by shared code
4430	* phy_info - PHY information structure
4431	******************************************************************************/
4432	int32_t
4433	e1000_phy_get_info(struct e1000_hw *hw,
4434	struct e1000_phy_info *phy_info)
4435	{
4436	int32_t ret_val;
4437	uint16_t phy_data;
4438
4439	DEBUGFUNC("e1000_phy_get_info");
4440
4441	phy_info->cable_length = e1000_cable_length_undefined;
4442	phy_info->extended_10bt_distance = e1000_10bt_ext_dist_enable_undefined;
4443	phy_info->cable_polarity = e1000_rev_polarity_undefined;
4444	phy_info->downshift = e1000_downshift_undefined;
4445	phy_info->polarity_correction = e1000_polarity_reversal_undefined;
4446	phy_info->mdix_mode = e1000_auto_x_mode_undefined;
4447	phy_info->local_rx = e1000_1000t_rx_status_undefined;
4448	phy_info->remote_rx = e1000_1000t_rx_status_undefined;
4449
4450	if (hw->media_type != e1000_media_type_copper) {
4451	DEBUGOUT("PHY info is only valid for copper media\n");
4452	return -E1000_ERR_CONFIG;
4453	}
4454
4455	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4456	if (ret_val)
4457	return ret_val;
4458
4459	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &phy_data);
4460	if (ret_val)
4461	return ret_val;
4462
4463	if ((phy_data & MII_SR_LINK_STATUS) != MII_SR_LINK_STATUS) {
4464	DEBUGOUT("PHY info is only valid if link is up\n");
4465	return -E1000_ERR_CONFIG;
4466	}
4467
4468	if (hw->phy_type == e1000_phy_igp \|\|
4469	hw->phy_type == e1000_phy_igp_3 \|\|
4470	hw->phy_type == e1000_phy_igp_2)
4471	return e1000_phy_igp_get_info(hw, phy_info);
4472	else if (hw->phy_type == e1000_phy_ife)
4473	return e1000_phy_ife_get_info(hw, phy_info);
4474	else
4475	return e1000_phy_m88_get_info(hw, phy_info);
4476	}
4477
4478	int32_t
4479	e1000_validate_mdi_setting(struct e1000_hw *hw)
4480	{
4481	DEBUGFUNC("e1000_validate_mdi_settings");
4482
4483	if (!hw->autoneg && (hw->mdix == 0 \|\| hw->mdix == 3)) {
4484	DEBUGOUT("Invalid MDI setting detected\n");
4485	hw->mdix = 1;
4486	return -E1000_ERR_CONFIG;
4487	}
4488	return E1000_SUCCESS;
4489	}
4490
4491
4492	/******************************************************************************
4493	* Sets up eeprom variables in the hw struct. Must be called after mac_type
4494	* is configured. Additionally, if this is ICH8, the flash controller GbE
4495	* registers must be mapped, or this will crash.
4496	*
4497	* hw - Struct containing variables accessed by shared code
4498	*****************************************************************************/
4499	int32_t
4500	e1000_init_eeprom_params(struct e1000_hw *hw)
4501	{
4502	struct e1000_eeprom_info *eeprom = &hw->eeprom;
4503	uint32_t eecd = E1000_READ_REG(hw, EECD);
4504	int32_t ret_val = E1000_SUCCESS;
4505	uint16_t eeprom_size;
4506
4507	DEBUGFUNC("e1000_init_eeprom_params");
4508
4509	switch (hw->mac_type) {
4510	case e1000_82542_rev2_0:
4511	case e1000_82542_rev2_1:
4512	case e1000_82543:
4513	case e1000_82544:
4514	eeprom->type = e1000_eeprom_microwire;
4515	eeprom->word_size = 64;
4516	eeprom->opcode_bits = 3;
4517	eeprom->address_bits = 6;
4518	eeprom->delay_usec = 50;
4519	eeprom->use_eerd = FALSE;
4520	eeprom->use_eewr = FALSE;
4521	break;
4522	case e1000_82540:
4523	case e1000_82545:
4524	case e1000_82545_rev_3:
4525	case e1000_82546:
4526	case e1000_82546_rev_3:
4527	eeprom->type = e1000_eeprom_microwire;
4528	eeprom->opcode_bits = 3;
4529	eeprom->delay_usec = 50;
4530	if (eecd & E1000_EECD_SIZE) {
4531	eeprom->word_size = 256;
4532	eeprom->address_bits = 8;
4533	} else {
4534	eeprom->word_size = 64;
4535	eeprom->address_bits = 6;
4536	}
4537	eeprom->use_eerd = FALSE;
4538	eeprom->use_eewr = FALSE;
4539	break;
4540	case e1000_82541:
4541	case e1000_82541_rev_2:
4542	case e1000_82547:
4543	case e1000_82547_rev_2:
4544	if (eecd & E1000_EECD_TYPE) {
4545	eeprom->type = e1000_eeprom_spi;
4546	eeprom->opcode_bits = 8;
4547	eeprom->delay_usec = 1;
4548	if (eecd & E1000_EECD_ADDR_BITS) {
4549	eeprom->page_size = 32;
4550	eeprom->address_bits = 16;
4551	} else {
4552	eeprom->page_size = 8;
4553	eeprom->address_bits = 8;
4554	}
4555	} else {
4556	eeprom->type = e1000_eeprom_microwire;
4557	eeprom->opcode_bits = 3;
4558	eeprom->delay_usec = 50;
4559	if (eecd & E1000_EECD_ADDR_BITS) {
4560	eeprom->word_size = 256;
4561	eeprom->address_bits = 8;
4562	} else {
4563	eeprom->word_size = 64;
4564	eeprom->address_bits = 6;
4565	}
4566	}
4567	eeprom->use_eerd = FALSE;
4568	eeprom->use_eewr = FALSE;
4569	break;
4570	case e1000_82571:
4571	case e1000_82572:
4572	eeprom->type = e1000_eeprom_spi;
4573	eeprom->opcode_bits = 8;
4574	eeprom->delay_usec = 1;
4575	if (eecd & E1000_EECD_ADDR_BITS) {
4576	eeprom->page_size = 32;
4577	eeprom->address_bits = 16;
4578	} else {
4579	eeprom->page_size = 8;
4580	eeprom->address_bits = 8;
4581	}
4582	eeprom->use_eerd = FALSE;
4583	eeprom->use_eewr = FALSE;
4584	break;
4585	case e1000_82573:
4586	eeprom->type = e1000_eeprom_spi;
4587	eeprom->opcode_bits = 8;
4588	eeprom->delay_usec = 1;
4589	if (eecd & E1000_EECD_ADDR_BITS) {
4590	eeprom->page_size = 32;
4591	eeprom->address_bits = 16;
4592	} else {
4593	eeprom->page_size = 8;
4594	eeprom->address_bits = 8;
4595	}
4596	eeprom->use_eerd = TRUE;
4597	eeprom->use_eewr = TRUE;
4598	if (e1000_is_onboard_nvm_eeprom(hw) == FALSE) {
4599	eeprom->type = e1000_eeprom_flash;
4600	eeprom->word_size = 2048;
4601
4602	/* Ensure that the Autonomous FLASH update bit is cleared due to
4603	* Flash update issue on parts which use a FLASH for NVM. */
4604	eecd &= ~E1000_EECD_AUPDEN;
4605	E1000_WRITE_REG(hw, EECD, eecd);
4606	}
4607	break;
4608	case e1000_80003es2lan:
4609	eeprom->type = e1000_eeprom_spi;
4610	eeprom->opcode_bits = 8;
4611	eeprom->delay_usec = 1;
4612	if (eecd & E1000_EECD_ADDR_BITS) {
4613	eeprom->page_size = 32;
4614	eeprom->address_bits = 16;
4615	} else {
4616	eeprom->page_size = 8;
4617	eeprom->address_bits = 8;
4618	}
4619	eeprom->use_eerd = TRUE;
4620	eeprom->use_eewr = FALSE;
4621	break;
4622	case e1000_ich8lan:
4623	{
4624	int32_t i = 0;
4625	uint32_t flash_size = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_GFPREG);
4626
4627	eeprom->type = e1000_eeprom_ich8;
4628	eeprom->use_eerd = FALSE;
4629	eeprom->use_eewr = FALSE;
4630	eeprom->word_size = E1000_SHADOW_RAM_WORDS;
4631
4632	/* Zero the shadow RAM structure. But don't load it from NVM
4633	* so as to save time for driver init */
4634	if (hw->eeprom_shadow_ram != NULL) {
4635	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
4636	hw->eeprom_shadow_ram[i].modified = FALSE;
4637	hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
4638	}
4639	}
4640
4641	hw->flash_base_addr = (flash_size & ICH_GFPREG_BASE_MASK) *
4642	ICH_FLASH_SECTOR_SIZE;
4643
4644	hw->flash_bank_size = ((flash_size >> 16) & ICH_GFPREG_BASE_MASK) + 1;
4645	hw->flash_bank_size -= (flash_size & ICH_GFPREG_BASE_MASK);
4646
4647	hw->flash_bank_size *= ICH_FLASH_SECTOR_SIZE;
4648
4649	hw->flash_bank_size /= 2 * sizeof(uint16_t);
4650
4651	break;
4652	}
4653	case e1000_82576:
4654	{
4655	uint16_t size;
4656
4657	eeprom->type = e1000_eeprom_spi;
4658	eeprom->opcode_bits = 8;
4659	eeprom->delay_usec = 1;
4660	if (eecd & E1000_EECD_ADDR_BITS) {
4661	eeprom->page_size = 32;
4662	eeprom->address_bits = 16;
4663	} else {
4664	eeprom->page_size = 8;
4665	eeprom->address_bits = 8;
4666	}
4667	eeprom->use_eerd = TRUE;
4668	eeprom->use_eewr = FALSE;
4669
4670	size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4671	E1000_EECD_SIZE_EX_SHIFT);
4672	/*
4673	* Added to a constant, "size" becomes the left-shift value
4674	* for setting word_size.
4675	*/
4676	size += EEPROM_WORD_SIZE_SHIFT;
4677
4678	/* EEPROM access above 16k is unsupported */
4679	if (size > 14)
4680	size = 14;
4681	eeprom->word_size = 1 << size;
4682
4683	break;
4684	}
4685	default:
4686	break;
4687	}
4688
4689	if (eeprom->type == e1000_eeprom_spi) {
4690	/* eeprom_size will be an enum [0..8] that maps to eeprom sizes 128B to
4691	* 32KB (incremented by powers of 2).
4692	*/
4693	if (hw->mac_type <= e1000_82547_rev_2) {
4694	/* Set to default value for initial eeprom read. */
4695	eeprom->word_size = 64;
4696	ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1, &eeprom_size);
4697	if (ret_val)
4698	return ret_val;
4699	eeprom_size = (eeprom_size & EEPROM_SIZE_MASK) >> EEPROM_SIZE_SHIFT;
4700	/* 256B eeprom size was not supported in earlier hardware, so we
4701	* bump eeprom_size up one to ensure that "1" (which maps to 256B)
4702	* is never the result used in the shifting logic below. */
4703	if (eeprom_size)
4704	eeprom_size++;
4705	} else {
4706	eeprom_size = (uint16_t)((eecd & E1000_EECD_SIZE_EX_MASK) >>
4707	E1000_EECD_SIZE_EX_SHIFT);
4708	}
4709
4710	eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
4711	}
4712	return ret_val;
4713	}
4714
4715	/******************************************************************************
4716	* Raises the EEPROM's clock input.
4717	*
4718	* hw - Struct containing variables accessed by shared code
4719	* eecd - EECD's current value
4720	*****************************************************************************/
4721	static void
4722	e1000_raise_ee_clk(struct e1000_hw *hw,
4723	uint32_t *eecd)
4724	{
4725	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
4726	* wait <delay> microseconds.
4727	*/
4728	eecd = eecd \| E1000_EECD_SK;
4729	E1000_WRITE_REG(hw, EECD, *eecd);
4730	E1000_WRITE_FLUSH(hw);
4731	udelay(hw->eeprom.delay_usec);
4732	}
4733
4734	/******************************************************************************
4735	* Lowers the EEPROM's clock input.
4736	*
4737	* hw - Struct containing variables accessed by shared code
4738	* eecd - EECD's current value
4739	*****************************************************************************/
4740	static void
4741	e1000_lower_ee_clk(struct e1000_hw *hw,
4742	uint32_t *eecd)
4743	{
4744	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
4745	* wait 50 microseconds.
4746	*/
4747	eecd = eecd & ~E1000_EECD_SK;
4748	E1000_WRITE_REG(hw, EECD, *eecd);
4749	E1000_WRITE_FLUSH(hw);
4750	udelay(hw->eeprom.delay_usec);
4751	}
4752
4753	/******************************************************************************
4754	* Shift data bits out to the EEPROM.
4755	*
4756	* hw - Struct containing variables accessed by shared code
4757	* data - data to send to the EEPROM
4758	* count - number of bits to shift out
4759	*****************************************************************************/
4760	static void
4761	e1000_shift_out_ee_bits(struct e1000_hw *hw,
4762	uint16_t data,
4763	uint16_t count)
4764	{
4765	struct e1000_eeprom_info *eeprom = &hw->eeprom;
4766	uint32_t eecd;
4767	uint32_t mask;
4768
4769	/* We need to shift "count" bits out to the EEPROM. So, value in the
4770	* "data" parameter will be shifted out to the EEPROM one bit at a time.
4771	* In order to do this, "data" must be broken down into bits.
4772	*/
4773	mask = 0x01 << (count - 1);
4774	eecd = E1000_READ_REG(hw, EECD);
4775	if (eeprom->type == e1000_eeprom_microwire) {
4776	eecd &= ~E1000_EECD_DO;
4777	} else if (eeprom->type == e1000_eeprom_spi) {
4778	eecd \|= E1000_EECD_DO;
4779	}
4780	do {
4781	/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
4782	* and then raising and then lowering the clock (the SK bit controls
4783	* the clock input to the EEPROM). A "0" is shifted out to the EEPROM
4784	* by setting "DI" to "0" and then raising and then lowering the clock.
4785	*/
4786	eecd &= ~E1000_EECD_DI;
4787
4788	if (data & mask)
4789	eecd \|= E1000_EECD_DI;
4790
4791	E1000_WRITE_REG(hw, EECD, eecd);
4792	E1000_WRITE_FLUSH(hw);
4793
4794	udelay(eeprom->delay_usec);
4795
4796	e1000_raise_ee_clk(hw, &eecd);
4797	e1000_lower_ee_clk(hw, &eecd);
4798
4799	mask = mask >> 1;
4800
4801	} while (mask);
4802
4803	/* We leave the "DI" bit set to "0" when we leave this routine. */
4804	eecd &= ~E1000_EECD_DI;
4805	E1000_WRITE_REG(hw, EECD, eecd);
4806	}
4807
4808	/******************************************************************************
4809	* Shift data bits in from the EEPROM
4810	*
4811	* hw - Struct containing variables accessed by shared code
4812	*****************************************************************************/
4813	static uint16_t
4814	e1000_shift_in_ee_bits(struct e1000_hw *hw,
4815	uint16_t count)
4816	{
4817	uint32_t eecd;
4818	uint32_t i;
4819	uint16_t data;
4820
4821	/* In order to read a register from the EEPROM, we need to shift 'count'
4822	* bits in from the EEPROM. Bits are "shifted in" by raising the clock
4823	* input to the EEPROM (setting the SK bit), and then reading the value of
4824	* the "DO" bit. During this "shifting in" process the "DI" bit should
4825	* always be clear.
4826	*/
4827
4828	eecd = E1000_READ_REG(hw, EECD);
4829
4830	eecd &= ~(E1000_EECD_DO \| E1000_EECD_DI);
4831	data = 0;
4832
4833	for (i = 0; i < count; i++) {
4834	data = data << 1;
4835	e1000_raise_ee_clk(hw, &eecd);
4836
4837	eecd = E1000_READ_REG(hw, EECD);
4838
4839	eecd &= ~(E1000_EECD_DI);
4840	if (eecd & E1000_EECD_DO)
4841	data \|= 1;
4842
4843	e1000_lower_ee_clk(hw, &eecd);
4844	}
4845
4846	return data;
4847	}
4848
4849	/******************************************************************************
4850	* Prepares EEPROM for access
4851	*
4852	* hw - Struct containing variables accessed by shared code
4853	*
4854	* Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
4855	* function should be called before issuing a command to the EEPROM.
4856	*****************************************************************************/
4857	static int32_t
4858	e1000_acquire_eeprom(struct e1000_hw *hw)
4859	{
4860	struct e1000_eeprom_info *eeprom = &hw->eeprom;
4861	uint32_t eecd, i=0;
4862
4863	DEBUGFUNC("e1000_acquire_eeprom");
4864
4865	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
4866	return -E1000_ERR_SWFW_SYNC;
4867	eecd = E1000_READ_REG(hw, EECD);
4868
4869	if (hw->mac_type != e1000_82573) {
4870	/* Request EEPROM Access */
4871	if (hw->mac_type > e1000_82544) {
4872	eecd \|= E1000_EECD_REQ;
4873	E1000_WRITE_REG(hw, EECD, eecd);
4874	eecd = E1000_READ_REG(hw, EECD);
4875	while ((!(eecd & E1000_EECD_GNT)) &&
4876	(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
4877	i++;
4878	udelay(5);
4879	eecd = E1000_READ_REG(hw, EECD);
4880	}
4881	if (!(eecd & E1000_EECD_GNT)) {
4882	eecd &= ~E1000_EECD_REQ;
4883	E1000_WRITE_REG(hw, EECD, eecd);
4884	DEBUGOUT("Could not acquire EEPROM grant\n");
4885	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
4886	return -E1000_ERR_EEPROM;
4887	}
4888	}
4889	}
4890
4891	/* Setup EEPROM for Read/Write */
4892
4893	if (eeprom->type == e1000_eeprom_microwire) {
4894	/* Clear SK and DI */
4895	eecd &= ~(E1000_EECD_DI \| E1000_EECD_SK);
4896	E1000_WRITE_REG(hw, EECD, eecd);
4897
4898	/* Set CS */
4899	eecd \|= E1000_EECD_CS;
4900	E1000_WRITE_REG(hw, EECD, eecd);
4901	} else if (eeprom->type == e1000_eeprom_spi) {
4902	/* Clear SK and CS */
4903	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
4904	E1000_WRITE_REG(hw, EECD, eecd);
4905	udelay(1);
4906	}
4907
4908	return E1000_SUCCESS;
4909	}
4910
4911	/******************************************************************************
4912	* Returns EEPROM to a "standby" state
4913	*
4914	* hw - Struct containing variables accessed by shared code
4915	*****************************************************************************/
4916	static void
4917	e1000_standby_eeprom(struct e1000_hw *hw)
4918	{
4919	struct e1000_eeprom_info *eeprom = &hw->eeprom;
4920	uint32_t eecd;
4921
4922	eecd = E1000_READ_REG(hw, EECD);
4923
4924	if (eeprom->type == e1000_eeprom_microwire) {
4925	eecd &= ~(E1000_EECD_CS \| E1000_EECD_SK);
4926	E1000_WRITE_REG(hw, EECD, eecd);
4927	E1000_WRITE_FLUSH(hw);
4928	udelay(eeprom->delay_usec);
4929
4930	/* Clock high */
4931	eecd \|= E1000_EECD_SK;
4932	E1000_WRITE_REG(hw, EECD, eecd);
4933	E1000_WRITE_FLUSH(hw);
4934	udelay(eeprom->delay_usec);
4935
4936	/* Select EEPROM */
4937	eecd \|= E1000_EECD_CS;
4938	E1000_WRITE_REG(hw, EECD, eecd);
4939	E1000_WRITE_FLUSH(hw);
4940	udelay(eeprom->delay_usec);
4941
4942	/* Clock low */
4943	eecd &= ~E1000_EECD_SK;
4944	E1000_WRITE_REG(hw, EECD, eecd);
4945	E1000_WRITE_FLUSH(hw);
4946	udelay(eeprom->delay_usec);
4947	} else if (eeprom->type == e1000_eeprom_spi) {
4948	/* Toggle CS to flush commands */
4949	eecd \|= E1000_EECD_CS;
4950	E1000_WRITE_REG(hw, EECD, eecd);
4951	E1000_WRITE_FLUSH(hw);
4952	udelay(eeprom->delay_usec);
4953	eecd &= ~E1000_EECD_CS;
4954	E1000_WRITE_REG(hw, EECD, eecd);
4955	E1000_WRITE_FLUSH(hw);
4956	udelay(eeprom->delay_usec);
4957	}
4958	}
4959
4960	/******************************************************************************
4961	* Terminates a command by inverting the EEPROM's chip select pin
4962	*
4963	* hw - Struct containing variables accessed by shared code
4964	*****************************************************************************/
4965	static void
4966	e1000_release_eeprom(struct e1000_hw *hw)
4967	{
4968	uint32_t eecd;
4969
4970	DEBUGFUNC("e1000_release_eeprom");
4971
4972	eecd = E1000_READ_REG(hw, EECD);
4973
4974	if (hw->eeprom.type == e1000_eeprom_spi) {
4975	eecd \|= E1000_EECD_CS; /* Pull CS high */
4976	eecd &= ~E1000_EECD_SK; /* Lower SCK */
4977
4978	E1000_WRITE_REG(hw, EECD, eecd);
4979
4980	udelay(hw->eeprom.delay_usec);
4981	} else if (hw->eeprom.type == e1000_eeprom_microwire) {
4982	/* cleanup eeprom */
4983
4984	/* CS on Microwire is active-high */
4985	eecd &= ~(E1000_EECD_CS \| E1000_EECD_DI);
4986
4987	E1000_WRITE_REG(hw, EECD, eecd);
4988
4989	/* Rising edge of clock */
4990	eecd \|= E1000_EECD_SK;
4991	E1000_WRITE_REG(hw, EECD, eecd);
4992	E1000_WRITE_FLUSH(hw);
4993	udelay(hw->eeprom.delay_usec);
4994
4995	/* Falling edge of clock */
4996	eecd &= ~E1000_EECD_SK;
4997	E1000_WRITE_REG(hw, EECD, eecd);
4998	E1000_WRITE_FLUSH(hw);
4999	udelay(hw->eeprom.delay_usec);
5000	}
5001
5002	/* Stop requesting EEPROM access */
5003	if (hw->mac_type > e1000_82544) {
5004	eecd &= ~E1000_EECD_REQ;
5005	E1000_WRITE_REG(hw, EECD, eecd);
5006	}
5007
5008	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5009	}
5010
5011	/******************************************************************************
5012	* Reads a 16 bit word from the EEPROM.
5013	*
5014	* hw - Struct containing variables accessed by shared code
5015	*****************************************************************************/
5016	static int32_t
5017	e1000_spi_eeprom_ready(struct e1000_hw *hw)
5018	{
5019	uint16_t retry_count = 0;
5020	uint8_t spi_stat_reg;
5021
5022	DEBUGFUNC("e1000_spi_eeprom_ready");
5023
5024	/* Read "Status Register" repeatedly until the LSB is cleared. The
5025	* EEPROM will signal that the command has been completed by clearing
5026	* bit 0 of the internal status register. If it's not cleared within
5027	* 5 milliseconds, then error out.
5028	*/
5029	retry_count = 0;
5030	do {
5031	e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
5032	hw->eeprom.opcode_bits);
5033	spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
5034	if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
5035	break;
5036
5037	udelay(5);
5038	retry_count += 5;
5039
5040	e1000_standby_eeprom(hw);
5041	} while (retry_count < EEPROM_MAX_RETRY_SPI);
5042
5043	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
5044	* only 0-5mSec on 5V devices)
5045	*/
5046	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
5047	DEBUGOUT("SPI EEPROM Status error\n");
5048	return -E1000_ERR_EEPROM;
5049	}
5050
5051	return E1000_SUCCESS;
5052	}
5053
5054	/******************************************************************************
5055	* Reads a 16 bit word from the EEPROM.
5056	*
5057	* hw - Struct containing variables accessed by shared code
5058	* offset - offset of word in the EEPROM to read
5059	* data - word read from the EEPROM
5060	* words - number of words to read
5061	*****************************************************************************/
5062	int32_t
5063	e1000_read_eeprom(struct e1000_hw *hw,
5064	uint16_t offset,
5065	uint16_t words,
5066	uint16_t *data)
5067	{
5068	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5069	uint32_t i = 0;
5070
5071	DEBUGFUNC("e1000_read_eeprom");
5072
5073	/* If eeprom is not yet detected, do so now */
5074	if (eeprom->word_size == 0)
5075	e1000_init_eeprom_params(hw);
5076
5077	/* A check for invalid values: offset too large, too many words, and not
5078	* enough words.
5079	*/
5080	if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
5081	(words == 0)) {
5082	DEBUGOUT2("\"words\" parameter out of bounds. Words = %d, size = %d\n", offset, eeprom->word_size);
5083	return -E1000_ERR_EEPROM;
5084	}
5085
5086	/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
5087	* directly. In this case, we need to acquire the EEPROM so that
5088	* FW or other port software does not interrupt.
5089	*/
5090	if (hw->eeprom.use_eerd == FALSE && e1000_is_onboard_nvm_eeprom(hw)) {
5091	/* Prepare the EEPROM for bit-bang reading */
5092	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5093	return -E1000_ERR_EEPROM;
5094	}
5095
5096	/* Eerd register EEPROM access requires no eeprom aquire/release */
5097	if (eeprom->use_eerd == TRUE)
5098	return e1000_read_eeprom_eerd(hw, offset, words, data);
5099
5100	/* ICH EEPROM access is done via the ICH flash controller */
5101	if (eeprom->type == e1000_eeprom_ich8)
5102	return e1000_read_eeprom_ich8(hw, offset, words, data);
5103
5104	/* Set up the SPI or Microwire EEPROM for bit-bang reading. We have
5105	* acquired the EEPROM at this point, so any returns should relase it */
5106	if (eeprom->type == e1000_eeprom_spi) {
5107	uint16_t word_in;
5108	uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;
5109
5110	if (e1000_spi_eeprom_ready(hw)) {
5111	e1000_release_eeprom(hw);
5112	return -E1000_ERR_EEPROM;
5113	}
5114
5115	e1000_standby_eeprom(hw);
5116
5117	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
5118	if ((eeprom->address_bits == 8) && (offset >= 128))
5119	read_opcode \|= EEPROM_A8_OPCODE_SPI;
5120
5121	/* Send the READ command (opcode + addr) */
5122	e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
5123	e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2), eeprom->address_bits);
5124
5125	/* Read the data. The address of the eeprom internally increments with
5126	* each byte (spi) being read, saving on the overhead of eeprom setup
5127	* and tear-down. The address counter will roll over if reading beyond
5128	* the size of the eeprom, thus allowing the entire memory to be read
5129	* starting from any offset. */
5130	for (i = 0; i < words; i++) {
5131	word_in = e1000_shift_in_ee_bits(hw, 16);
5132	data[i] = (word_in >> 8) \| (word_in << 8);
5133	}
5134	} else if (eeprom->type == e1000_eeprom_microwire) {
5135	for (i = 0; i < words; i++) {
5136	/* Send the READ command (opcode + addr) */
5137	e1000_shift_out_ee_bits(hw, EEPROM_READ_OPCODE_MICROWIRE,
5138	eeprom->opcode_bits);
5139	e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
5140	eeprom->address_bits);
5141
5142	/* Read the data. For microwire, each word requires the overhead
5143	* of eeprom setup and tear-down. */
5144	data[i] = e1000_shift_in_ee_bits(hw, 16);
5145	e1000_standby_eeprom(hw);
5146	}
5147	}
5148
5149	/* End this read operation */
5150	e1000_release_eeprom(hw);
5151
5152	return E1000_SUCCESS;
5153	}
5154
5155	/******************************************************************************
5156	* Reads a 16 bit word from the EEPROM using the EERD register.
5157	*
5158	* hw - Struct containing variables accessed by shared code
5159	* offset - offset of word in the EEPROM to read
5160	* data - word read from the EEPROM
5161	* words - number of words to read
5162	*****************************************************************************/
5163	static int32_t
5164	e1000_read_eeprom_eerd(struct e1000_hw *hw,
5165	uint16_t offset,
5166	uint16_t words,
5167	uint16_t *data)
5168	{
5169	uint32_t i, eerd = 0;
5170	int32_t error = 0;
5171
5172	for (i = 0; i < words; i++) {
5173	eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
5174	E1000_EEPROM_RW_REG_START;
5175
5176	E1000_WRITE_REG(hw, EERD, eerd);
5177	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);
5178
5179	if (error) {
5180	break;
5181	}
5182	data[i] = (E1000_READ_REG(hw, EERD) >> E1000_EEPROM_RW_REG_DATA);
5183
5184	}
5185
5186	return error;
5187	}
5188
5189	/******************************************************************************
5190	* Writes a 16 bit word from the EEPROM using the EEWR register.
5191	*
5192	* hw - Struct containing variables accessed by shared code
5193	* offset - offset of word in the EEPROM to read
5194	* data - word read from the EEPROM
5195	* words - number of words to read
5196	*****************************************************************************/
5197	static int32_t
5198	e1000_write_eeprom_eewr(struct e1000_hw *hw,
5199	uint16_t offset,
5200	uint16_t words,
5201	uint16_t *data)
5202	{
5203	uint32_t register_value = 0;
5204	uint32_t i = 0;
5205	int32_t error = 0;
5206
5207	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
5208	return -E1000_ERR_SWFW_SYNC;
5209
5210	for (i = 0; i < words; i++) {
5211	register_value = (data[i] << E1000_EEPROM_RW_REG_DATA) \|
5212	((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) \|
5213	E1000_EEPROM_RW_REG_START;
5214
5215	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5216	if (error) {
5217	break;
5218	}
5219
5220	E1000_WRITE_REG(hw, EEWR, register_value);
5221
5222	error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_WRITE);
5223
5224	if (error) {
5225	break;
5226	}
5227	}
5228
5229	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
5230	return error;
5231	}
5232
5233	/******************************************************************************
5234	* Polls the status bit (bit 1) of the EERD to determine when the read is done.
5235	*
5236	* hw - Struct containing variables accessed by shared code
5237	*****************************************************************************/
5238	static int32_t
5239	e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
5240	{
5241	uint32_t attempts = 100000;
5242	uint32_t i, reg = 0;
5243	int32_t done = E1000_ERR_EEPROM;
5244
5245	for (i = 0; i < attempts; i++) {
5246	if (eerd == E1000_EEPROM_POLL_READ)
5247	reg = E1000_READ_REG(hw, EERD);
5248	else
5249	reg = E1000_READ_REG(hw, EEWR);
5250
5251	if (reg & E1000_EEPROM_RW_REG_DONE) {
5252	done = E1000_SUCCESS;
5253	break;
5254	}
5255	udelay(5);
5256	}
5257
5258	return done;
5259	}
5260
5261	/***************************************************************************
5262	* Description: Determines if the onboard NVM is FLASH or EEPROM.
5263	*
5264	* hw - Struct containing variables accessed by shared code
5265	****************************************************************************/
5266	static boolean_t
5267	e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
5268	{
5269	uint32_t eecd = 0;
5270
5271	DEBUGFUNC("e1000_is_onboard_nvm_eeprom");
5272
5273	assert(hw->mac_type != e1000_82576);
5274
5275	if (hw->mac_type == e1000_ich8lan)
5276	return FALSE;
5277
5278	if (hw->mac_type == e1000_82573) {
5279	eecd = E1000_READ_REG(hw, EECD);
5280
5281	/* Isolate bits 15 & 16 */
5282	eecd = ((eecd >> 15) & 0x03);
5283
5284	/* If both bits are set, device is Flash type */
5285	if (eecd == 0x03) {
5286	return FALSE;
5287	}
5288	}
5289	return TRUE;
5290	}
5291
5292	/******************************************************************************
5293	* Verifies that the EEPROM has a valid checksum
5294	*
5295	* hw - Struct containing variables accessed by shared code
5296	*
5297	* Reads the first 64 16 bit words of the EEPROM and sums the values read.
5298	* If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
5299	* valid.
5300	*****************************************************************************/
5301	int32_t
5302	e1000_validate_eeprom_checksum(struct e1000_hw *hw)
5303	{
5304	uint16_t checksum = 0;
5305	uint16_t i, eeprom_data;
5306
5307	DEBUGFUNC("e1000_validate_eeprom_checksum");
5308
5309	if ((hw->mac_type == e1000_82573) &&
5310	(e1000_is_onboard_nvm_eeprom(hw) == FALSE)) {
5311	/* Check bit 4 of word 10h. If it is 0, firmware is done updating
5312	* 10h-12h. Checksum may need to be fixed. */
5313	e1000_read_eeprom(hw, 0x10, 1, &eeprom_data);
5314	if ((eeprom_data & 0x10) == 0) {
5315	/* Read 0x23 and check bit 15. This bit is a 1 when the checksum
5316	* has already been fixed. If the checksum is still wrong and this
5317	* bit is a 1, we need to return bad checksum. Otherwise, we need
5318	* to set this bit to a 1 and update the checksum. */
5319	e1000_read_eeprom(hw, 0x23, 1, &eeprom_data);
5320	if ((eeprom_data & 0x8000) == 0) {
5321	eeprom_data \|= 0x8000;
5322	e1000_write_eeprom(hw, 0x23, 1, &eeprom_data);
5323	e1000_update_eeprom_checksum(hw);
5324	}
5325	}
5326	}
5327
5328	if (hw->mac_type == e1000_ich8lan) {
5329	/* Drivers must allocate the shadow ram structure for the
5330	* EEPROM checksum to be updated. Otherwise, this bit as well
5331	* as the checksum must both be set correctly for this
5332	* validation to pass.
5333	*/
5334	e1000_read_eeprom(hw, 0x19, 1, &eeprom_data);
5335	if ((eeprom_data & 0x40) == 0) {
5336	eeprom_data \|= 0x40;
5337	e1000_write_eeprom(hw, 0x19, 1, &eeprom_data);
5338	e1000_update_eeprom_checksum(hw);
5339	}
5340	}
5341
5342	for (i = 0; i < (EEPROM_CHECKSUM_REG + 1); i++) {
5343	if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5344	DEBUGOUT("EEPROM Read Error\n");
5345	return -E1000_ERR_EEPROM;
5346	}
5347	checksum += eeprom_data;
5348	}
5349
5350	if (checksum == (uint16_t) EEPROM_SUM)
5351	return E1000_SUCCESS;
5352	else {
5353	DEBUGOUT("EEPROM Checksum Invalid\n");
5354	return -E1000_ERR_EEPROM;
5355	}
5356	}
5357
5358	/******************************************************************************
5359	* Calculates the EEPROM checksum and writes it to the EEPROM
5360	*
5361	* hw - Struct containing variables accessed by shared code
5362	*
5363	* Sums the first 63 16 bit words of the EEPROM. Subtracts the sum from 0xBABA.
5364	* Writes the difference to word offset 63 of the EEPROM.
5365	*****************************************************************************/
5366	int32_t
5367	e1000_update_eeprom_checksum(struct e1000_hw *hw)
5368	{
5369	uint32_t ctrl_ext;
5370	uint16_t checksum = 0;
5371	uint16_t i, eeprom_data;
5372
5373	DEBUGFUNC("e1000_update_eeprom_checksum");
5374
5375	for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
5376	if (e1000_read_eeprom(hw, i, 1, &eeprom_data) < 0) {
5377	DEBUGOUT("EEPROM Read Error\n");
5378	return -E1000_ERR_EEPROM;
5379	}
5380	checksum += eeprom_data;
5381	}
5382	checksum = (uint16_t) EEPROM_SUM - checksum;
5383	if (e1000_write_eeprom(hw, EEPROM_CHECKSUM_REG, 1, &checksum) < 0) {
5384	DEBUGOUT("EEPROM Write Error\n");
5385	return -E1000_ERR_EEPROM;
5386	} else if (hw->eeprom.type == e1000_eeprom_flash) {
5387	e1000_commit_shadow_ram(hw);
5388	} else if (hw->eeprom.type == e1000_eeprom_ich8) {
5389	e1000_commit_shadow_ram(hw);
5390	/* Reload the EEPROM, or else modifications will not appear
5391	* until after next adapter reset. */
5392	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
5393	ctrl_ext \|= E1000_CTRL_EXT_EE_RST;
5394	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
5395	msleep(10);
5396	}
5397	return E1000_SUCCESS;
5398	}
5399
5400	/******************************************************************************
5401	* Parent function for writing words to the different EEPROM types.
5402	*
5403	* hw - Struct containing variables accessed by shared code
5404	* offset - offset within the EEPROM to be written to
5405	* words - number of words to write
5406	* data - 16 bit word to be written to the EEPROM
5407	*
5408	* If e1000_update_eeprom_checksum is not called after this function, the
5409	* EEPROM will most likely contain an invalid checksum.
5410	*****************************************************************************/
5411	int32_t
5412	e1000_write_eeprom(struct e1000_hw *hw,
5413	uint16_t offset,
5414	uint16_t words,
5415	uint16_t *data)
5416	{
5417	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5418	int32_t status = 0;
5419
5420	DEBUGFUNC("e1000_write_eeprom");
5421
5422	/* If eeprom is not yet detected, do so now */
5423	if (eeprom->word_size == 0)
5424	e1000_init_eeprom_params(hw);
5425
5426	/* A check for invalid values: offset too large, too many words, and not
5427	* enough words.
5428	*/
5429	if ((offset >= eeprom->word_size) \|\| (words > eeprom->word_size - offset) \|\|
5430	(words == 0)) {
5431	DEBUGOUT("\"words\" parameter out of bounds\n");
5432	return -E1000_ERR_EEPROM;
5433	}
5434
5435	/* 82573 writes only through eewr */
5436	if (eeprom->use_eewr == TRUE)
5437	return e1000_write_eeprom_eewr(hw, offset, words, data);
5438
5439	if (eeprom->type == e1000_eeprom_ich8)
5440	return e1000_write_eeprom_ich8(hw, offset, words, data);
5441
5442	/* Prepare the EEPROM for writing */
5443	if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
5444	return -E1000_ERR_EEPROM;
5445
5446	if (eeprom->type == e1000_eeprom_microwire) {
5447	status = e1000_write_eeprom_microwire(hw, offset, words, data);
5448	} else {
5449	status = e1000_write_eeprom_spi(hw, offset, words, data);
5450	msleep(10);
5451	}
5452
5453	/* Done with writing */
5454	e1000_release_eeprom(hw);
5455
5456	return status;
5457	}
5458
5459	/******************************************************************************
5460	* Writes a 16 bit word to a given offset in an SPI EEPROM.
5461	*
5462	* hw - Struct containing variables accessed by shared code
5463	* offset - offset within the EEPROM to be written to
5464	* words - number of words to write
5465	* data - pointer to array of 8 bit words to be written to the EEPROM
5466	*
5467	*****************************************************************************/
5468	static int32_t
5469	e1000_write_eeprom_spi(struct e1000_hw *hw,
5470	uint16_t offset,
5471	uint16_t words,
5472	uint16_t *data)
5473	{
5474	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5475	uint16_t widx = 0;
5476
5477	DEBUGFUNC("e1000_write_eeprom_spi");
5478
5479	while (widx < words) {
5480	uint8_t write_opcode = EEPROM_WRITE_OPCODE_SPI;
5481
5482	if (e1000_spi_eeprom_ready(hw)) return -E1000_ERR_EEPROM;
5483
5484	e1000_standby_eeprom(hw);
5485
5486	/* Send the WRITE ENABLE command (8 bit opcode ) */
5487	e1000_shift_out_ee_bits(hw, EEPROM_WREN_OPCODE_SPI,
5488	eeprom->opcode_bits);
5489
5490	e1000_standby_eeprom(hw);
5491
5492	/* Some SPI eeproms use the 8th address bit embedded in the opcode */
5493	if ((eeprom->address_bits == 8) && (offset >= 128))
5494	write_opcode \|= EEPROM_A8_OPCODE_SPI;
5495
5496	/* Send the Write command (8-bit opcode + addr) */
5497	e1000_shift_out_ee_bits(hw, write_opcode, eeprom->opcode_bits);
5498
5499	e1000_shift_out_ee_bits(hw, (uint16_t)((offset + widx)*2),
5500	eeprom->address_bits);
5501
5502	/* Send the data */
5503
5504	/* Loop to allow for up to whole page write (32 bytes) of eeprom */
5505	while (widx < words) {
5506	uint16_t word_out = data[widx];
5507	word_out = (word_out >> 8) \| (word_out << 8);
5508	e1000_shift_out_ee_bits(hw, word_out, 16);
5509	widx++;
5510
5511	/* Some larger eeprom sizes are capable of a 32-byte PAGE WRITE
5512	* operation, while the smaller eeproms are capable of an 8-byte
5513	* PAGE WRITE operation. Break the inner loop to pass new address
5514	*/
5515	if ((((offset + widx)*2) % eeprom->page_size) == 0) {
5516	e1000_standby_eeprom(hw);
5517	break;
5518	}
5519	}
5520	}
5521
5522	return E1000_SUCCESS;
5523	}
5524
5525	/******************************************************************************
5526	* Writes a 16 bit word to a given offset in a Microwire EEPROM.
5527	*
5528	* hw - Struct containing variables accessed by shared code
5529	* offset - offset within the EEPROM to be written to
5530	* words - number of words to write
5531	* data - pointer to array of 16 bit words to be written to the EEPROM
5532	*
5533	*****************************************************************************/
5534	static int32_t
5535	e1000_write_eeprom_microwire(struct e1000_hw *hw,
5536	uint16_t offset,
5537	uint16_t words,
5538	uint16_t *data)
5539	{
5540	struct e1000_eeprom_info *eeprom = &hw->eeprom;
5541	uint32_t eecd;
5542	uint16_t words_written = 0;
5543	uint16_t i = 0;
5544
5545	DEBUGFUNC("e1000_write_eeprom_microwire");
5546
5547	/* Send the write enable command to the EEPROM (3-bit opcode plus
5548	* 6/8-bit dummy address beginning with 11). It's less work to include
5549	* the 11 of the dummy address as part of the opcode than it is to shift
5550	* it over the correct number of bits for the address. This puts the
5551	* EEPROM into write/erase mode.
5552	*/
5553	e1000_shift_out_ee_bits(hw, EEPROM_EWEN_OPCODE_MICROWIRE,
5554	(uint16_t)(eeprom->opcode_bits + 2));
5555
5556	e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5557
5558	/* Prepare the EEPROM */
5559	e1000_standby_eeprom(hw);
5560
5561	while (words_written < words) {
5562	/* Send the Write command (3-bit opcode + addr) */
5563	e1000_shift_out_ee_bits(hw, EEPROM_WRITE_OPCODE_MICROWIRE,
5564	eeprom->opcode_bits);
5565
5566	e1000_shift_out_ee_bits(hw, (uint16_t)(offset + words_written),
5567	eeprom->address_bits);
5568
5569	/* Send the data */
5570	e1000_shift_out_ee_bits(hw, data[words_written], 16);
5571
5572	/* Toggle the CS line. This in effect tells the EEPROM to execute
5573	* the previous command.
5574	*/
5575	e1000_standby_eeprom(hw);
5576
5577	/* Read DO repeatedly until it is high (equal to '1'). The EEPROM will
5578	* signal that the command has been completed by raising the DO signal.
5579	* If DO does not go high in 10 milliseconds, then error out.
5580	*/
5581	for (i = 0; i < 200; i++) {
5582	eecd = E1000_READ_REG(hw, EECD);
5583	if (eecd & E1000_EECD_DO) break;
5584	udelay(50);
5585	}
5586	if (i == 200) {
5587	DEBUGOUT("EEPROM Write did not complete\n");
5588	return -E1000_ERR_EEPROM;
5589	}
5590
5591	/* Recover from write */
5592	e1000_standby_eeprom(hw);
5593
5594	words_written++;
5595	}
5596
5597	/* Send the write disable command to the EEPROM (3-bit opcode plus
5598	* 6/8-bit dummy address beginning with 10). It's less work to include
5599	* the 10 of the dummy address as part of the opcode than it is to shift
5600	* it over the correct number of bits for the address. This takes the
5601	* EEPROM out of write/erase mode.
5602	*/
5603	e1000_shift_out_ee_bits(hw, EEPROM_EWDS_OPCODE_MICROWIRE,
5604	(uint16_t)(eeprom->opcode_bits + 2));
5605
5606	e1000_shift_out_ee_bits(hw, 0, (uint16_t)(eeprom->address_bits - 2));
5607
5608	return E1000_SUCCESS;
5609	}
5610
5611	/******************************************************************************
5612	* Flushes the cached eeprom to NVM. This is done by saving the modified values
5613	* in the eeprom cache and the non modified values in the currently active bank
5614	* to the new bank.
5615	*
5616	* hw - Struct containing variables accessed by shared code
5617	* offset - offset of word in the EEPROM to read
5618	* data - word read from the EEPROM
5619	* words - number of words to read
5620	*****************************************************************************/
5621	static int32_t
5622	e1000_commit_shadow_ram(struct e1000_hw *hw)
5623	{
5624	uint32_t attempts = 100000;
5625	uint32_t eecd = 0;
5626	uint32_t flop = 0;
5627	uint32_t i = 0;
5628	int32_t error = E1000_SUCCESS;
5629	uint32_t old_bank_offset = 0;
5630	uint32_t new_bank_offset = 0;
5631	uint8_t low_byte = 0;
5632	uint8_t high_byte = 0;
5633	boolean_t sector_write_failed = FALSE;
5634
5635	if (hw->mac_type == e1000_82573) {
5636	/* The flop register will be used to determine if flash type is STM */
5637	flop = E1000_READ_REG(hw, FLOP);
5638	for (i=0; i < attempts; i++) {
5639	eecd = E1000_READ_REG(hw, EECD);
5640	if ((eecd & E1000_EECD_FLUPD) == 0) {
5641	break;
5642	}
5643	udelay(5);
5644	}
5645
5646	if (i == attempts) {
5647	return -E1000_ERR_EEPROM;
5648	}
5649
5650	/* If STM opcode located in bits 15:8 of flop, reset firmware */
5651	if ((flop & 0xFF00) == E1000_STM_OPCODE) {
5652	E1000_WRITE_REG(hw, HICR, E1000_HICR_FW_RESET);
5653	}
5654
5655	/* Perform the flash update */
5656	E1000_WRITE_REG(hw, EECD, eecd \| E1000_EECD_FLUPD);
5657
5658	for (i=0; i < attempts; i++) {
5659	eecd = E1000_READ_REG(hw, EECD);
5660	if ((eecd & E1000_EECD_FLUPD) == 0) {
5661	break;
5662	}
5663	udelay(5);
5664	}
5665
5666	if (i == attempts) {
5667	return -E1000_ERR_EEPROM;
5668	}
5669	}
5670
5671	if (hw->mac_type == e1000_ich8lan && hw->eeprom_shadow_ram != NULL) {
5672	/* We're writing to the opposite bank so if we're on bank 1,
5673	* write to bank 0 etc. We also need to erase the segment that
5674	* is going to be written */
5675	if (!(E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL)) {
5676	new_bank_offset = hw->flash_bank_size * 2;
5677	old_bank_offset = 0;
5678	e1000_erase_ich8_4k_segment(hw, 1);
5679	} else {
5680	old_bank_offset = hw->flash_bank_size * 2;
5681	new_bank_offset = 0;
5682	e1000_erase_ich8_4k_segment(hw, 0);
5683	}
5684
5685	sector_write_failed = FALSE;
5686	/* Loop for every byte in the shadow RAM,
5687	* which is in units of words. */
5688	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5689	/* Determine whether to write the value stored
5690	* in the other NVM bank or a modified value stored
5691	* in the shadow RAM */
5692	if (hw->eeprom_shadow_ram[i].modified == TRUE) {
5693	low_byte = (uint8_t)hw->eeprom_shadow_ram[i].eeprom_word;
5694	udelay(100);
5695	error = e1000_verify_write_ich8_byte(hw,
5696	(i << 1) + new_bank_offset, low_byte);
5697
5698	if (error != E1000_SUCCESS)
5699	sector_write_failed = TRUE;
5700	else {
5701	high_byte =
5702	(uint8_t)(hw->eeprom_shadow_ram[i].eeprom_word >> 8);
5703	udelay(100);
5704	}
5705	} else {
5706	e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset,
5707	&low_byte);
5708	udelay(100);
5709	error = e1000_verify_write_ich8_byte(hw,
5710	(i << 1) + new_bank_offset, low_byte);
5711
5712	if (error != E1000_SUCCESS)
5713	sector_write_failed = TRUE;
5714	else {
5715	e1000_read_ich8_byte(hw, (i << 1) + old_bank_offset + 1,
5716	&high_byte);
5717	udelay(100);
5718	}
5719	}
5720
5721	/* If the write of the low byte was successful, go ahread and
5722	* write the high byte while checking to make sure that if it
5723	* is the signature byte, then it is handled properly */
5724	if (sector_write_failed == FALSE) {
5725	/* If the word is 0x13, then make sure the signature bits
5726	* (15:14) are 11b until the commit has completed.
5727	* This will allow us to write 10b which indicates the
5728	* signature is valid. We want to do this after the write
5729	* has completed so that we don't mark the segment valid
5730	* while the write is still in progress */
5731	if (i == E1000_ICH_NVM_SIG_WORD)
5732	high_byte = E1000_ICH_NVM_SIG_MASK \| high_byte;
5733
5734	error = e1000_verify_write_ich8_byte(hw,
5735	(i << 1) + new_bank_offset + 1, high_byte);
5736	if (error != E1000_SUCCESS)
5737	sector_write_failed = TRUE;
5738
5739	} else {
5740	/* If the write failed then break from the loop and
5741	* return an error */
5742	break;
5743	}
5744	}
5745
5746	/* Don't bother writing the segment valid bits if sector
5747	* programming failed. */
5748	if (sector_write_failed == FALSE) {
5749	/* Finally validate the new segment by setting bit 15:14
5750	* to 10b in word 0x13 , this can be done without an
5751	* erase as well since these bits are 11 to start with
5752	* and we need to change bit 14 to 0b */
5753	e1000_read_ich8_byte(hw,
5754	E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset,
5755	&high_byte);
5756	high_byte &= 0xBF;
5757	error = e1000_verify_write_ich8_byte(hw,
5758	E1000_ICH_NVM_SIG_WORD * 2 + 1 + new_bank_offset, high_byte);
5759	/* And invalidate the previously valid segment by setting
5760	* its signature word (0x13) high_byte to 0b. This can be
5761	* done without an erase because flash erase sets all bits
5762	* to 1's. We can write 1's to 0's without an erase */
5763	if (error == E1000_SUCCESS) {
5764	error = e1000_verify_write_ich8_byte(hw,
5765	E1000_ICH_NVM_SIG_WORD * 2 + 1 + old_bank_offset, 0);
5766	}
5767
5768	/* Clear the now not used entry in the cache */
5769	for (i = 0; i < E1000_SHADOW_RAM_WORDS; i++) {
5770	hw->eeprom_shadow_ram[i].modified = FALSE;
5771	hw->eeprom_shadow_ram[i].eeprom_word = 0xFFFF;
5772	}
5773	}
5774	}
5775
5776	return error;
5777	}
5778
5779	/******************************************************************************
5780	* Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
5781	* second function of dual function devices
5782	*
5783	* hw - Struct containing variables accessed by shared code
5784	*****************************************************************************/
5785	int32_t
5786	e1000_read_mac_addr(struct e1000_hw * hw)
5787	{
5788	uint16_t offset, mac_addr_offset = 0;
5789	uint16_t eeprom_data, i;
5790	int32_t ret_val;
5791
5792	DEBUGFUNC("e1000_read_mac_addr");
5793
5794	if (hw->mac_type == e1000_82571) {
5795	/* Check for an alternate MAC address. An alternate MAC
5796	* address can be setup by pre-boot software and must be
5797	* treated like a permanent address and must override the
5798	* actual permanent MAC address.*/
5799	ret_val = e1000_read_eeprom(hw, EEPROM_ALT_MAC_ADDR_PTR, 1,
5800	&mac_addr_offset);
5801	if (ret_val) {
5802	DEBUGOUT("EEPROM Read Error\n");
5803	return -E1000_ERR_EEPROM;
5804	}
5805	if (mac_addr_offset == 0xFFFF)
5806	mac_addr_offset = 0;
5807
5808	if (mac_addr_offset) {
5809	if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5810	mac_addr_offset += NODE_ADDRESS_SIZE/sizeof(u16);
5811
5812	/* make sure we have a valid mac address here
5813	* before using it */
5814	ret_val = e1000_read_eeprom(hw, mac_addr_offset, 1,
5815	&eeprom_data);
5816	if (ret_val) {
5817	DEBUGOUT("EEPROM Read Error\n");
5818	return -E1000_ERR_EEPROM;
5819	}
5820	if (eeprom_data & 0x0001)
5821	mac_addr_offset = 0;
5822	}
5823
5824	if (mac_addr_offset)
5825	hw->laa_is_present = TRUE;
5826	}
5827
5828	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
5829	offset = mac_addr_offset + (i >> 1);
5830	if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
5831	DEBUGOUT("EEPROM Read Error\n");
5832	return -E1000_ERR_EEPROM;
5833	}
5834	hw->perm_mac_addr[i] = (uint8_t) (eeprom_data & 0x00FF);
5835	hw->perm_mac_addr[i+1] = (uint8_t) (eeprom_data >> 8);
5836	}
5837
5838	switch (hw->mac_type) {
5839	default:
5840	break;
5841	case e1000_82546:
5842	case e1000_82546_rev_3:
5843	case e1000_82571:
5844	case e1000_82576:
5845	case e1000_80003es2lan:
5846	if (!mac_addr_offset &&
5847	E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
5848	hw->perm_mac_addr[5] ^= 0x01;
5849	break;
5850	}
5851
5852	for (i = 0; i < NODE_ADDRESS_SIZE; i++)
5853	hw->mac_addr[i] = hw->perm_mac_addr[i];
5854	return E1000_SUCCESS;
5855	}
5856
5857	/******************************************************************************
5858	* Initializes receive address filters.
5859	*
5860	* hw - Struct containing variables accessed by shared code
5861	*
5862	* Places the MAC address in receive address register 0 and clears the rest
5863	* of the receive addresss registers. Clears the multicast table. Assumes
5864	* the receiver is in reset when the routine is called.
5865	*****************************************************************************/
5866	static void
5867	e1000_init_rx_addrs(struct e1000_hw *hw)
5868	{
5869	uint32_t i;
5870	uint32_t rar_num;
5871
5872	DEBUGFUNC("e1000_init_rx_addrs");
5873
5874	/* Setup the receive address. */
5875	DEBUGOUT("Programming MAC Address into RAR[0]\n");
5876
5877	e1000_rar_set(hw, hw->mac_addr, 0);
5878
5879	rar_num = E1000_RAR_ENTRIES;
5880
5881	/* Reserve a spot for the Locally Administered Address to work around
5882	* an 82571 issue in which a reset on one port will reload the MAC on
5883	* the other port. */
5884	if ((hw->mac_type == e1000_82571) && (hw->laa_is_present == TRUE))
5885	rar_num -= 1;
5886	if (hw->mac_type == e1000_ich8lan)
5887	rar_num = E1000_RAR_ENTRIES_ICH8LAN;
5888
5889	/* Zero out the other 15 receive addresses. */
5890	DEBUGOUT("Clearing RAR[1-15]\n");
5891	for (i = 1; i < rar_num; i++) {
5892	E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
5893	E1000_WRITE_FLUSH(hw);
5894	E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
5895	E1000_WRITE_FLUSH(hw);
5896	}
5897	}
5898
5899	/******************************************************************************
5900	* Hashes an address to determine its location in the multicast table
5901	*
5902	* hw - Struct containing variables accessed by shared code
5903	* mc_addr - the multicast address to hash
5904	*****************************************************************************/
5905	uint32_t
5906	e1000_hash_mc_addr(struct e1000_hw *hw,
5907	uint8_t *mc_addr)
5908	{
5909	uint32_t hash_value = 0;
5910
5911	/* The portion of the address that is used for the hash table is
5912	* determined by the mc_filter_type setting.
5913	*/
5914	switch (hw->mc_filter_type) {
5915	/* [0] [1] [2] [3] [4] [5]
5916	* 01 AA 00 12 34 56
5917	* LSB MSB
5918	*/
5919	case 0:
5920	if (hw->mac_type == e1000_ich8lan) {
5921	/* [47:38] i.e. 0x158 for above example address */
5922	hash_value = ((mc_addr[4] >> 6) \| (((uint16_t) mc_addr[5]) << 2));
5923	} else {
5924	/* [47:36] i.e. 0x563 for above example address */
5925	hash_value = ((mc_addr[4] >> 4) \| (((uint16_t) mc_addr[5]) << 4));
5926	}
5927	break;
5928	case 1:
5929	if (hw->mac_type == e1000_ich8lan) {
5930	/* [46:37] i.e. 0x2B1 for above example address */
5931	hash_value = ((mc_addr[4] >> 5) \| (((uint16_t) mc_addr[5]) << 3));
5932	} else {
5933	/* [46:35] i.e. 0xAC6 for above example address */
5934	hash_value = ((mc_addr[4] >> 3) \| (((uint16_t) mc_addr[5]) << 5));
5935	}
5936	break;
5937	case 2:
5938	if (hw->mac_type == e1000_ich8lan) {
5939	/[45:36] i.e. 0x163 for above example address /
5940	hash_value = ((mc_addr[4] >> 4) \| (((uint16_t) mc_addr[5]) << 4));
5941	} else {
5942	/* [45:34] i.e. 0x5D8 for above example address */
5943	hash_value = ((mc_addr[4] >> 2) \| (((uint16_t) mc_addr[5]) << 6));
5944	}
5945	break;
5946	case 3:
5947	if (hw->mac_type == e1000_ich8lan) {
5948	/* [43:34] i.e. 0x18D for above example address */
5949	hash_value = ((mc_addr[4] >> 2) \| (((uint16_t) mc_addr[5]) << 6));
5950	} else {
5951	/* [43:32] i.e. 0x634 for above example address */
5952	hash_value = ((mc_addr[4]) \| (((uint16_t) mc_addr[5]) << 8));
5953	}
5954	break;
5955	}
5956
5957	hash_value &= 0xFFF;
5958	if (hw->mac_type == e1000_ich8lan)
5959	hash_value &= 0x3FF;
5960
5961	return hash_value;
5962	}
5963
5964	/******************************************************************************
5965	* Sets the bit in the multicast table corresponding to the hash value.
5966	*
5967	* hw - Struct containing variables accessed by shared code
5968	* hash_value - Multicast address hash value
5969	*****************************************************************************/
5970	void
5971	e1000_mta_set(struct e1000_hw *hw,
5972	uint32_t hash_value)
5973	{
5974	uint32_t hash_bit, hash_reg;
5975	uint32_t mta;
5976	uint32_t temp;
5977
5978	/* The MTA is a register array of 128 32-bit registers.
5979	* It is treated like an array of 4096 bits. We want to set
5980	* bit BitArray[hash_value]. So we figure out what register
5981	* the bit is in, read it, OR in the new bit, then write
5982	* back the new value. The register is determined by the
5983	* upper 7 bits of the hash value and the bit within that
5984	* register are determined by the lower 5 bits of the value.
5985	*/
5986	hash_reg = (hash_value >> 5) & 0x7F;
5987	if (hw->mac_type == e1000_ich8lan)
5988	hash_reg &= 0x1F;
5989
5990	hash_bit = hash_value & 0x1F;
5991
5992	mta = E1000_READ_REG_ARRAY(hw, MTA, hash_reg);
5993
5994	mta \|= (1 << hash_bit);
5995
5996	/* If we are on an 82544 and we are trying to write an odd offset
5997	* in the MTA, save off the previous entry before writing and
5998	* restore the old value after writing.
5999	*/
6000	if ((hw->mac_type == e1000_82544) && ((hash_reg & 0x1) == 1)) {
6001	temp = E1000_READ_REG_ARRAY(hw, MTA, (hash_reg - 1));
6002	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6003	E1000_WRITE_FLUSH(hw);
6004	E1000_WRITE_REG_ARRAY(hw, MTA, (hash_reg - 1), temp);
6005	E1000_WRITE_FLUSH(hw);
6006	} else {
6007	E1000_WRITE_REG_ARRAY(hw, MTA, hash_reg, mta);
6008	E1000_WRITE_FLUSH(hw);
6009	}
6010	}
6011
6012	/******************************************************************************
6013	* Puts an ethernet address into a receive address register.
6014	*
6015	* hw - Struct containing variables accessed by shared code
6016	* addr - Address to put into receive address register
6017	* index - Receive address register to write
6018	*****************************************************************************/
6019	void
6020	e1000_rar_set(struct e1000_hw *hw,
6021	uint8_t *addr,
6022	uint32_t index)
6023	{
6024	uint32_t rar_low, rar_high;
6025
6026	/* HW expects these in little endian so we reverse the byte order
6027	* from network order (big endian) to little endian
6028	*/
6029	rar_low = ((uint32_t) addr[0] \|
6030	((uint32_t) addr[1] << 8) \|
6031	((uint32_t) addr[2] << 16) \| ((uint32_t) addr[3] << 24));
6032	rar_high = ((uint32_t) addr[4] \| ((uint32_t) addr[5] << 8));
6033
6034	/* Disable Rx and flush all Rx frames before enabling RSS to avoid Rx
6035	* unit hang.
6036	*
6037	* Description:
6038	* If there are any Rx frames queued up or otherwise present in the HW
6039	* before RSS is enabled, and then we enable RSS, the HW Rx unit will
6040	* hang. To work around this issue, we have to disable receives and
6041	* flush out all Rx frames before we enable RSS. To do so, we modify we
6042	* redirect all Rx traffic to manageability and then reset the HW.
6043	* This flushes away Rx frames, and (since the redirections to
6044	* manageability persists across resets) keeps new ones from coming in
6045	* while we work. Then, we clear the Address Valid AV bit for all MAC
6046	* addresses and undo the re-direction to manageability.
6047	* Now, frames are coming in again, but the MAC won't accept them, so
6048	* far so good. We now proceed to initialize RSS (if necessary) and
6049	* configure the Rx unit. Last, we re-enable the AV bits and continue
6050	* on our merry way.
6051	*/
6052	switch (hw->mac_type) {
6053	case e1000_82571:
6054	case e1000_82572:
6055	case e1000_80003es2lan:
6056	if (hw->leave_av_bit_off == TRUE)
6057	break;
6058	case e1000_82576:
6059	/* If MAC address zero, no need to set the AV bit */
6060	if (rar_low \|\| rar_high)
6061	rar_high \|= E1000_RAH_AV;
6062	// Only neded when Multiple Receive Queues are enabmed in MRQC
6063	rar_high \|= E1000_RAH_POOL_1;
6064	break;
6065	default:
6066	/* Indicate to hardware the Address is Valid. */
6067	rar_high \|= E1000_RAH_AV;
6068	break;
6069	}
6070
6071	E1000_WRITE_REG_ARRAY(hw, RA, (index << 1), rar_low);
6072	E1000_WRITE_FLUSH(hw);
6073	E1000_WRITE_REG_ARRAY(hw, RA, ((index << 1) + 1), rar_high);
6074	E1000_WRITE_FLUSH(hw);
6075	}
6076
6077	/******************************************************************************
6078	* Writes a value to the specified offset in the VLAN filter table.
6079	*
6080	* hw - Struct containing variables accessed by shared code
6081	* offset - Offset in VLAN filer table to write
6082	* value - Value to write into VLAN filter table
6083	*****************************************************************************/
6084	void
6085	e1000_write_vfta(struct e1000_hw *hw,
6086	uint32_t offset,
6087	uint32_t value)
6088	{
6089	uint32_t temp;
6090
6091	if (hw->mac_type == e1000_ich8lan)
6092	return;
6093
6094	if ((hw->mac_type == e1000_82544) && ((offset & 0x1) == 1)) {
6095	temp = E1000_READ_REG_ARRAY(hw, VFTA, (offset - 1));
6096	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6097	E1000_WRITE_FLUSH(hw);
6098	E1000_WRITE_REG_ARRAY(hw, VFTA, (offset - 1), temp);
6099	E1000_WRITE_FLUSH(hw);
6100	} else {
6101	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, value);
6102	E1000_WRITE_FLUSH(hw);
6103	}
6104	}
6105
6106	/******************************************************************************
6107	* Clears the VLAN filer table
6108	*
6109	* hw - Struct containing variables accessed by shared code
6110	*****************************************************************************/
6111	static void
6112	e1000_clear_vfta(struct e1000_hw *hw)
6113	{
6114	uint32_t offset;
6115	uint32_t vfta_value = 0;
6116	uint32_t vfta_offset = 0;
6117	uint32_t vfta_bit_in_reg = 0;
6118
6119	if (hw->mac_type == e1000_ich8lan)
6120	return;
6121
6122	if (hw->mac_type == e1000_82573) {
6123	if (hw->mng_cookie.vlan_id != 0) {
6124	/* The VFTA is a 4096b bit-field, each identifying a single VLAN
6125	* ID. The following operations determine which 32b entry
6126	* (i.e. offset) into the array we want to set the VLAN ID
6127	* (i.e. bit) of the manageability unit. */
6128	vfta_offset = (hw->mng_cookie.vlan_id >>
6129	E1000_VFTA_ENTRY_SHIFT) &
6130	E1000_VFTA_ENTRY_MASK;
6131	vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
6132	E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
6133	}
6134	}
6135	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
6136	/* If the offset we want to clear is the same offset of the
6137	* manageability VLAN ID, then clear all bits except that of the
6138	* manageability unit */
6139	vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
6140	E1000_WRITE_REG_ARRAY(hw, VFTA, offset, vfta_value);
6141	E1000_WRITE_FLUSH(hw);
6142	}
6143	}
6144
6145	static int32_t
6146	e1000_id_led_init(struct e1000_hw * hw)
6147	{
6148	uint32_t ledctl;
6149	const uint32_t ledctl_mask = 0x000000FF;
6150	const uint32_t ledctl_on = E1000_LEDCTL_MODE_LED_ON;
6151	const uint32_t ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
6152	uint16_t eeprom_data, i, temp;
6153	const uint16_t led_mask = 0x0F;
6154
6155	DEBUGFUNC("e1000_id_led_init");
6156
6157	if (hw->mac_type < e1000_82540) {
6158	/* Nothing to do */
6159	return E1000_SUCCESS;
6160	}
6161
6162	ledctl = E1000_READ_REG(hw, LEDCTL);
6163	hw->ledctl_default = ledctl;
6164	hw->ledctl_mode1 = hw->ledctl_default;
6165	hw->ledctl_mode2 = hw->ledctl_default;
6166
6167	if (e1000_read_eeprom(hw, EEPROM_ID_LED_SETTINGS, 1, &eeprom_data) < 0) {
6168	DEBUGOUT("EEPROM Read Error\n");
6169	return -E1000_ERR_EEPROM;
6170	}
6171
6172	if ((hw->mac_type == e1000_82573) &&
6173	(eeprom_data == ID_LED_RESERVED_82573))
6174	eeprom_data = ID_LED_DEFAULT_82573;
6175	else if ((eeprom_data == ID_LED_RESERVED_0000) \|\|
6176	(eeprom_data == ID_LED_RESERVED_FFFF)) {
6177	if (hw->mac_type == e1000_ich8lan)
6178	eeprom_data = ID_LED_DEFAULT_ICH8LAN;
6179	else
6180	eeprom_data = ID_LED_DEFAULT;
6181	}
6182
6183	for (i = 0; i < 4; i++) {
6184	temp = (eeprom_data >> (i << 2)) & led_mask;
6185	switch (temp) {
6186	case ID_LED_ON1_DEF2:
6187	case ID_LED_ON1_ON2:
6188	case ID_LED_ON1_OFF2:
6189	hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6190	hw->ledctl_mode1 \|= ledctl_on << (i << 3);
6191	break;
6192	case ID_LED_OFF1_DEF2:
6193	case ID_LED_OFF1_ON2:
6194	case ID_LED_OFF1_OFF2:
6195	hw->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
6196	hw->ledctl_mode1 \|= ledctl_off << (i << 3);
6197	break;
6198	default:
6199	/* Do nothing */
6200	break;
6201	}
6202	switch (temp) {
6203	case ID_LED_DEF1_ON2:
6204	case ID_LED_ON1_ON2:
6205	case ID_LED_OFF1_ON2:
6206	hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6207	hw->ledctl_mode2 \|= ledctl_on << (i << 3);
6208	break;
6209	case ID_LED_DEF1_OFF2:
6210	case ID_LED_ON1_OFF2:
6211	case ID_LED_OFF1_OFF2:
6212	hw->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
6213	hw->ledctl_mode2 \|= ledctl_off << (i << 3);
6214	break;
6215	default:
6216	/* Do nothing */
6217	break;
6218	}
6219	}
6220	return E1000_SUCCESS;
6221	}
6222
6223	/******************************************************************************
6224	* Prepares SW controlable LED for use and saves the current state of the LED.
6225	*
6226	* hw - Struct containing variables accessed by shared code
6227	*****************************************************************************/
6228	int32_t
6229	e1000_setup_led(struct e1000_hw *hw)
6230	{
6231	uint32_t ledctl;
6232	int32_t ret_val = E1000_SUCCESS;
6233
6234	DEBUGFUNC("e1000_setup_led");
6235
6236	switch (hw->mac_type) {
6237	case e1000_82542_rev2_0:
6238	case e1000_82542_rev2_1:
6239	case e1000_82543:
6240	case e1000_82544:
6241	/* No setup necessary */
6242	break;
6243	case e1000_82541:
6244	case e1000_82547:
6245	case e1000_82541_rev_2:
6246	case e1000_82547_rev_2:
6247	/* Turn off PHY Smart Power Down (if enabled) */
6248	ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO,
6249	&hw->phy_spd_default);
6250	if (ret_val)
6251	return ret_val;
6252	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6253	(uint16_t)(hw->phy_spd_default &
6254	~IGP01E1000_GMII_SPD));
6255	if (ret_val)
6256	return ret_val;
6257	/* Fall Through */
6258	default:
6259	if (hw->media_type == e1000_media_type_fiber) {
6260	ledctl = E1000_READ_REG(hw, LEDCTL);
6261	/* Save current LEDCTL settings */
6262	hw->ledctl_default = ledctl;
6263	/* Turn off LED0 */
6264	ledctl &= ~(E1000_LEDCTL_LED0_IVRT \|
6265	E1000_LEDCTL_LED0_BLINK \|
6266	E1000_LEDCTL_LED0_MODE_MASK);
6267	ledctl \|= (E1000_LEDCTL_MODE_LED_OFF <<
6268	E1000_LEDCTL_LED0_MODE_SHIFT);
6269	E1000_WRITE_REG(hw, LEDCTL, ledctl);
6270	} else if (hw->media_type == e1000_media_type_copper)
6271	E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6272	break;
6273	}
6274
6275	return E1000_SUCCESS;
6276	}
6277
6278
6279	/******************************************************************************
6280	* Used on 82571 and later Si that has LED blink bits.
6281	* Callers must use their own timer and should have already called
6282	* e1000_id_led_init()
6283	* Call e1000_cleanup led() to stop blinking
6284	*
6285	* hw - Struct containing variables accessed by shared code
6286	*****************************************************************************/
6287	int32_t
6288	e1000_blink_led_start(struct e1000_hw *hw)
6289	{
6290	int16_t i;
6291	uint32_t ledctl_blink = 0;
6292
6293	DEBUGFUNC("e1000_id_led_blink_on");
6294
6295	if (hw->mac_type < e1000_82571) {
6296	/* Nothing to do */
6297	return E1000_SUCCESS;
6298	}
6299	if (hw->media_type == e1000_media_type_fiber) {
6300	/* always blink LED0 for PCI-E fiber */
6301	ledctl_blink = E1000_LEDCTL_LED0_BLINK \|
6302	(E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
6303	} else {
6304	/* set the blink bit for each LED that's "on" (0x0E) in ledctl_mode2 */
6305	ledctl_blink = hw->ledctl_mode2;
6306	for (i=0; i < 4; i++)
6307	if (((hw->ledctl_mode2 >> (i * 8)) & 0xFF) ==
6308	E1000_LEDCTL_MODE_LED_ON)
6309	ledctl_blink \|= (E1000_LEDCTL_LED0_BLINK << (i * 8));
6310	}
6311
6312	E1000_WRITE_REG(hw, LEDCTL, ledctl_blink);
6313
6314	return E1000_SUCCESS;
6315	}
6316
6317	/******************************************************************************
6318	* Restores the saved state of the SW controlable LED.
6319	*
6320	* hw - Struct containing variables accessed by shared code
6321	*****************************************************************************/
6322	int32_t
6323	e1000_cleanup_led(struct e1000_hw *hw)
6324	{
6325	int32_t ret_val = E1000_SUCCESS;
6326
6327	DEBUGFUNC("e1000_cleanup_led");
6328
6329	switch (hw->mac_type) {
6330	case e1000_82542_rev2_0:
6331	case e1000_82542_rev2_1:
6332	case e1000_82543:
6333	case e1000_82544:
6334	/* No cleanup necessary */
6335	break;
6336	case e1000_82541:
6337	case e1000_82547:
6338	case e1000_82541_rev_2:
6339	case e1000_82547_rev_2:
6340	/* Turn on PHY Smart Power Down (if previously enabled) */
6341	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO,
6342	hw->phy_spd_default);
6343	if (ret_val)
6344	return ret_val;
6345	/* Fall Through */
6346	default:
6347	if (hw->phy_type == e1000_phy_ife) {
6348	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED, 0);
6349	break;
6350	}
6351	/* Restore LEDCTL settings */
6352	E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_default);
6353	break;
6354	}
6355
6356	return E1000_SUCCESS;
6357	}
6358
6359	/******************************************************************************
6360	* Turns on the software controllable LED
6361	*
6362	* hw - Struct containing variables accessed by shared code
6363	*****************************************************************************/
6364	int32_t
6365	e1000_led_on(struct e1000_hw *hw)
6366	{
6367	uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6368
6369	DEBUGFUNC("e1000_led_on");
6370
6371	switch (hw->mac_type) {
6372	case e1000_82542_rev2_0:
6373	case e1000_82542_rev2_1:
6374	case e1000_82543:
6375	/* Set SW Defineable Pin 0 to turn on the LED */
6376	ctrl \|= E1000_CTRL_SWDPIN0;
6377	ctrl \|= E1000_CTRL_SWDPIO0;
6378	break;
6379	case e1000_82544:
6380	if (hw->media_type == e1000_media_type_fiber) {
6381	/* Set SW Defineable Pin 0 to turn on the LED */
6382	ctrl \|= E1000_CTRL_SWDPIN0;
6383	ctrl \|= E1000_CTRL_SWDPIO0;
6384	} else {
6385	/* Clear SW Defineable Pin 0 to turn on the LED */
6386	ctrl &= ~E1000_CTRL_SWDPIN0;
6387	ctrl \|= E1000_CTRL_SWDPIO0;
6388	}
6389	break;
6390	default:
6391	if (hw->media_type == e1000_media_type_fiber) {
6392	/* Clear SW Defineable Pin 0 to turn on the LED */
6393	ctrl &= ~E1000_CTRL_SWDPIN0;
6394	ctrl \|= E1000_CTRL_SWDPIO0;
6395	} else if (hw->phy_type == e1000_phy_ife) {
6396	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6397	(IFE_PSCL_PROBE_MODE \| IFE_PSCL_PROBE_LEDS_ON));
6398	} else if (hw->media_type == e1000_media_type_copper) {
6399	E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode2);
6400	return E1000_SUCCESS;
6401	}
6402	break;
6403	}
6404
6405	E1000_WRITE_REG(hw, CTRL, ctrl);
6406
6407	return E1000_SUCCESS;
6408	}
6409
6410	/******************************************************************************
6411	* Turns off the software controllable LED
6412	*
6413	* hw - Struct containing variables accessed by shared code
6414	*****************************************************************************/
6415	int32_t
6416	e1000_led_off(struct e1000_hw *hw)
6417	{
6418	uint32_t ctrl = E1000_READ_REG(hw, CTRL);
6419
6420	DEBUGFUNC("e1000_led_off");
6421
6422	switch (hw->mac_type) {
6423	case e1000_82542_rev2_0:
6424	case e1000_82542_rev2_1:
6425	case e1000_82543:
6426	/* Clear SW Defineable Pin 0 to turn off the LED */
6427	ctrl &= ~E1000_CTRL_SWDPIN0;
6428	ctrl \|= E1000_CTRL_SWDPIO0;
6429	break;
6430	case e1000_82544:
6431	if (hw->media_type == e1000_media_type_fiber) {
6432	/* Clear SW Defineable Pin 0 to turn off the LED */
6433	ctrl &= ~E1000_CTRL_SWDPIN0;
6434	ctrl \|= E1000_CTRL_SWDPIO0;
6435	} else {
6436	/* Set SW Defineable Pin 0 to turn off the LED */
6437	ctrl \|= E1000_CTRL_SWDPIN0;
6438	ctrl \|= E1000_CTRL_SWDPIO0;
6439	}
6440	break;
6441	default:
6442	if (hw->media_type == e1000_media_type_fiber) {
6443	/* Set SW Defineable Pin 0 to turn off the LED */
6444	ctrl \|= E1000_CTRL_SWDPIN0;
6445	ctrl \|= E1000_CTRL_SWDPIO0;
6446	} else if (hw->phy_type == e1000_phy_ife) {
6447	e1000_write_phy_reg(hw, IFE_PHY_SPECIAL_CONTROL_LED,
6448	(IFE_PSCL_PROBE_MODE \| IFE_PSCL_PROBE_LEDS_OFF));
6449	} else if (hw->media_type == e1000_media_type_copper) {
6450	E1000_WRITE_REG(hw, LEDCTL, hw->ledctl_mode1);
6451	return E1000_SUCCESS;
6452	}
6453	break;
6454	}
6455
6456	E1000_WRITE_REG(hw, CTRL, ctrl);
6457
6458	return E1000_SUCCESS;
6459	}
6460
6461	/******************************************************************************
6462	* Clears all hardware statistics counters.
6463	*
6464	* hw - Struct containing variables accessed by shared code
6465	*****************************************************************************/
6466	static void
6467	e1000_clear_hw_cntrs(struct e1000_hw *hw)
6468	{
6469	volatile uint32_t temp;
6470
6471	temp = E1000_READ_REG(hw, CRCERRS);
6472	temp = E1000_READ_REG(hw, SYMERRS);
6473	temp = E1000_READ_REG(hw, MPC);
6474	temp = E1000_READ_REG(hw, SCC);
6475	temp = E1000_READ_REG(hw, ECOL);
6476	temp = E1000_READ_REG(hw, MCC);
6477	temp = E1000_READ_REG(hw, LATECOL);
6478	temp = E1000_READ_REG(hw, COLC);
6479	temp = E1000_READ_REG(hw, DC);
6480	temp = E1000_READ_REG(hw, SEC);
6481	temp = E1000_READ_REG(hw, RLEC);
6482	temp = E1000_READ_REG(hw, XONRXC);
6483	temp = E1000_READ_REG(hw, XONTXC);
6484	temp = E1000_READ_REG(hw, XOFFRXC);
6485	temp = E1000_READ_REG(hw, XOFFTXC);
6486	temp = E1000_READ_REG(hw, FCRUC);
6487
6488	if (hw->mac_type != e1000_ich8lan) {
6489	temp = E1000_READ_REG(hw, PRC64);
6490	temp = E1000_READ_REG(hw, PRC127);
6491	temp = E1000_READ_REG(hw, PRC255);
6492	temp = E1000_READ_REG(hw, PRC511);
6493	temp = E1000_READ_REG(hw, PRC1023);
6494	temp = E1000_READ_REG(hw, PRC1522);
6495	}
6496
6497	temp = E1000_READ_REG(hw, GPRC);
6498	temp = E1000_READ_REG(hw, BPRC);
6499	temp = E1000_READ_REG(hw, MPRC);
6500	temp = E1000_READ_REG(hw, GPTC);
6501	temp = E1000_READ_REG(hw, GORCL);
6502	temp = E1000_READ_REG(hw, GORCH);
6503	temp = E1000_READ_REG(hw, GOTCL);
6504	temp = E1000_READ_REG(hw, GOTCH);
6505	temp = E1000_READ_REG(hw, RNBC);
6506	temp = E1000_READ_REG(hw, RUC);
6507	temp = E1000_READ_REG(hw, RFC);
6508	temp = E1000_READ_REG(hw, ROC);
6509	temp = E1000_READ_REG(hw, RJC);
6510	temp = E1000_READ_REG(hw, TORL);
6511	temp = E1000_READ_REG(hw, TORH);
6512	temp = E1000_READ_REG(hw, TOTL);
6513	temp = E1000_READ_REG(hw, TOTH);
6514	temp = E1000_READ_REG(hw, TPR);
6515	temp = E1000_READ_REG(hw, TPT);
6516
6517	if (hw->mac_type != e1000_ich8lan) {
6518	temp = E1000_READ_REG(hw, PTC64);
6519	temp = E1000_READ_REG(hw, PTC127);
6520	temp = E1000_READ_REG(hw, PTC255);
6521	temp = E1000_READ_REG(hw, PTC511);
6522	temp = E1000_READ_REG(hw, PTC1023);
6523	temp = E1000_READ_REG(hw, PTC1522);
6524	}
6525
6526	temp = E1000_READ_REG(hw, MPTC);
6527	temp = E1000_READ_REG(hw, BPTC);
6528
6529	if (hw->mac_type < e1000_82543) return;
6530
6531	temp = E1000_READ_REG(hw, ALGNERRC);
6532	temp = E1000_READ_REG(hw, RXERRC);
6533	temp = E1000_READ_REG(hw, TNCRS);
6534	temp = E1000_READ_REG(hw, CEXTERR);
6535	temp = E1000_READ_REG(hw, TSCTC);
6536	temp = E1000_READ_REG(hw, TSCTFC);
6537
6538	if (hw->mac_type <= e1000_82544) return;
6539
6540	temp = E1000_READ_REG(hw, MGTPRC);
6541	temp = E1000_READ_REG(hw, MGTPDC);
6542	temp = E1000_READ_REG(hw, MGTPTC);
6543
6544	if (hw->mac_type <= e1000_82547_rev_2) return;
6545
6546	temp = E1000_READ_REG(hw, IAC);
6547	temp = E1000_READ_REG(hw, ICRXOC);
6548
6549	if (hw->mac_type == e1000_ich8lan) return;
6550
6551	temp = E1000_READ_REG(hw, ICRXPTC);
6552	temp = E1000_READ_REG(hw, ICRXATC);
6553	temp = E1000_READ_REG(hw, ICTXPTC);
6554	temp = E1000_READ_REG(hw, ICTXATC);
6555	temp = E1000_READ_REG(hw, ICTXQEC);
6556	temp = E1000_READ_REG(hw, ICTXQMTC);
6557	temp = E1000_READ_REG(hw, ICRXDMTC);
6558	}
6559
6560	/******************************************************************************
6561	* Resets Adaptive IFS to its default state.
6562	*
6563	* hw - Struct containing variables accessed by shared code
6564	*
6565	* Call this after e1000_init_hw. You may override the IFS defaults by setting
6566	* hw->ifs_params_forced to TRUE. However, you must initialize hw->
6567	* current_ifs_val, ifs_min_val, ifs_max_val, ifs_step_size, and ifs_ratio
6568	* before calling this function.
6569	*****************************************************************************/
6570	void
6571	e1000_reset_adaptive(struct e1000_hw *hw)
6572	{
6573	DEBUGFUNC("e1000_reset_adaptive");
6574
6575	if (hw->adaptive_ifs) {
6576	if (!hw->ifs_params_forced) {
6577	hw->current_ifs_val = 0;
6578	hw->ifs_min_val = IFS_MIN;
6579	hw->ifs_max_val = IFS_MAX;
6580	hw->ifs_step_size = IFS_STEP;
6581	hw->ifs_ratio = IFS_RATIO;
6582	}
6583	hw->in_ifs_mode = FALSE;
6584	E1000_WRITE_REG(hw, AIT, 0);
6585	} else {
6586	DEBUGOUT("Not in Adaptive IFS mode!\n");
6587	}
6588	}
6589
6590	/******************************************************************************
6591	* Called during the callback/watchdog routine to update IFS value based on
6592	* the ratio of transmits to collisions.
6593	*
6594	* hw - Struct containing variables accessed by shared code
6595	* tx_packets - Number of transmits since last callback
6596	* total_collisions - Number of collisions since last callback
6597	*****************************************************************************/
6598	void
6599	e1000_update_adaptive(struct e1000_hw *hw)
6600	{
6601	DEBUGFUNC("e1000_update_adaptive");
6602
6603	if (hw->adaptive_ifs) {
6604	if ((hw->collision_delta * hw->ifs_ratio) > hw->tx_packet_delta) {
6605	if (hw->tx_packet_delta > MIN_NUM_XMITS) {
6606	hw->in_ifs_mode = TRUE;
6607	if (hw->current_ifs_val < hw->ifs_max_val) {
6608	if (hw->current_ifs_val == 0)
6609	hw->current_ifs_val = hw->ifs_min_val;
6610	else
6611	hw->current_ifs_val += hw->ifs_step_size;
6612	E1000_WRITE_REG(hw, AIT, hw->current_ifs_val);
6613	}
6614	}
6615	} else {
6616	if (hw->in_ifs_mode && (hw->tx_packet_delta <= MIN_NUM_XMITS)) {
6617	hw->current_ifs_val = 0;
6618	hw->in_ifs_mode = FALSE;
6619	E1000_WRITE_REG(hw, AIT, 0);
6620	}
6621	}
6622	} else {
6623	DEBUGOUT("Not in Adaptive IFS mode!\n");
6624	}
6625	}
6626
6627	/******************************************************************************
6628	* Adjusts the statistic counters when a frame is accepted by TBI_ACCEPT
6629	*
6630	* hw - Struct containing variables accessed by shared code
6631	* frame_len - The length of the frame in question
6632	* mac_addr - The Ethernet destination address of the frame in question
6633	*****************************************************************************/
6634	void
6635	e1000_tbi_adjust_stats(struct e1000_hw *hw,
6636	struct e1000_hw_stats *stats,
6637	uint32_t frame_len,
6638	uint8_t *mac_addr)
6639	{
6640	uint64_t carry_bit;
6641
6642	/* First adjust the frame length. */
6643	frame_len--;
6644	/* We need to adjust the statistics counters, since the hardware
6645	* counters overcount this packet as a CRC error and undercount
6646	* the packet as a good packet
6647	*/
6648	/* This packet should not be counted as a CRC error. */
6649	stats->crcerrs--;
6650	/* This packet does count as a Good Packet Received. */
6651	stats->gprc++;
6652
6653	/* Adjust the Good Octets received counters */
6654	carry_bit = 0x80000000 & stats->gorcl;
6655	stats->gorcl += frame_len;
6656	/* If the high bit of Gorcl (the low 32 bits of the Good Octets
6657	* Received Count) was one before the addition,
6658	* AND it is zero after, then we lost the carry out,
6659	* need to add one to Gorch (Good Octets Received Count High).
6660	* This could be simplified if all environments supported
6661	* 64-bit integers.
6662	*/
6663	if (carry_bit && ((stats->gorcl & 0x80000000) == 0))
6664	stats->gorch++;
6665	/* Is this a broadcast or multicast? Check broadcast first,
6666	* since the test for a multicast frame will test positive on
6667	* a broadcast frame.
6668	*/
6669	if ((mac_addr[0] == (uint8_t) 0xff) && (mac_addr[1] == (uint8_t) 0xff))
6670	/* Broadcast packet */
6671	stats->bprc++;
6672	else if (*mac_addr & 0x01)
6673	/* Multicast packet */
6674	stats->mprc++;
6675
6676	if (frame_len == hw->max_frame_size) {
6677	/* In this case, the hardware has overcounted the number of
6678	* oversize frames.
6679	*/
6680	if (stats->roc > 0)
6681	stats->roc--;
6682	}
6683
6684	/* Adjust the bin counters when the extra byte put the frame in the
6685	* wrong bin. Remember that the frame_len was adjusted above.
6686	*/
6687	if (frame_len == 64) {
6688	stats->prc64++;
6689	stats->prc127--;
6690	} else if (frame_len == 127) {
6691	stats->prc127++;
6692	stats->prc255--;
6693	} else if (frame_len == 255) {
6694	stats->prc255++;
6695	stats->prc511--;
6696	} else if (frame_len == 511) {
6697	stats->prc511++;
6698	stats->prc1023--;
6699	} else if (frame_len == 1023) {
6700	stats->prc1023++;
6701	stats->prc1522--;
6702	} else if (frame_len == 1522) {
6703	stats->prc1522++;
6704	}
6705	}
6706
6707	/******************************************************************************
6708	* Gets the current PCI bus type, speed, and width of the hardware
6709	*
6710	* hw - Struct containing variables accessed by shared code
6711	*****************************************************************************/
6712	void
6713	e1000_get_bus_info(struct e1000_hw *hw)
6714	{
6715	int32_t ret_val;
6716	uint16_t pci_ex_link_status;
6717	uint32_t status;
6718
6719	switch (hw->mac_type) {
6720	case e1000_82542_rev2_0:
6721	case e1000_82542_rev2_1:
6722	hw->bus_type = e1000_bus_type_pci;
6723	hw->bus_speed = e1000_bus_speed_unknown;
6724	hw->bus_width = e1000_bus_width_unknown;
6725	break;
6726	case e1000_82571:
6727	case e1000_82572:
6728	case e1000_82573:
6729	case e1000_80003es2lan:
6730	case e1000_82576:
6731	hw->bus_type = e1000_bus_type_pci_express;
6732	hw->bus_speed = e1000_bus_speed_2500;
6733	ret_val = e1000_read_pcie_cap_reg(hw,
6734	PCI_EX_LINK_STATUS,
6735	&pci_ex_link_status);
6736	if (ret_val)
6737	hw->bus_width = e1000_bus_width_unknown;
6738	else
6739	hw->bus_width = (pci_ex_link_status & PCI_EX_LINK_WIDTH_MASK) >>
6740	PCI_EX_LINK_WIDTH_SHIFT;
6741	break;
6742	case e1000_ich8lan:
6743	hw->bus_type = e1000_bus_type_pci_express;
6744	hw->bus_speed = e1000_bus_speed_2500;
6745	hw->bus_width = e1000_bus_width_pciex_1;
6746	break;
6747	default:
6748	status = E1000_READ_REG(hw, STATUS);
6749	hw->bus_type = (status & E1000_STATUS_PCIX_MODE) ?
6750	e1000_bus_type_pcix : e1000_bus_type_pci;
6751
6752	if (hw->device_id == E1000_DEV_ID_82546EB_QUAD_COPPER) {
6753	hw->bus_speed = (hw->bus_type == e1000_bus_type_pci) ?
6754	e1000_bus_speed_66 : e1000_bus_speed_120;
6755	} else if (hw->bus_type == e1000_bus_type_pci) {
6756	hw->bus_speed = (status & E1000_STATUS_PCI66) ?
6757	e1000_bus_speed_66 : e1000_bus_speed_33;
6758	} else {
6759	switch (status & E1000_STATUS_PCIX_SPEED) {
6760	case E1000_STATUS_PCIX_SPEED_66:
6761	hw->bus_speed = e1000_bus_speed_66;
6762	break;
6763	case E1000_STATUS_PCIX_SPEED_100:
6764	hw->bus_speed = e1000_bus_speed_100;
6765	break;
6766	case E1000_STATUS_PCIX_SPEED_133:
6767	hw->bus_speed = e1000_bus_speed_133;
6768	break;
6769	default:
6770	hw->bus_speed = e1000_bus_speed_reserved;
6771	break;
6772	}
6773	}
6774	hw->bus_width = (status & E1000_STATUS_BUS64) ?
6775	e1000_bus_width_64 : e1000_bus_width_32;
6776	break;
6777	}
6778	}
6779
6780	/******************************************************************************
6781	* Writes a value to one of the devices registers using port I/O (as opposed to
6782	* memory mapped I/O). Only 82544 and newer devices support port I/O.
6783	*
6784	* hw - Struct containing variables accessed by shared code
6785	* offset - offset to write to
6786	* value - value to write
6787	*****************************************************************************/
6788	static void
6789	e1000_write_reg_io(struct e1000_hw *hw,
6790	uint32_t offset,
6791	uint32_t value)
6792	{
6793	unsigned long io_addr = hw->io_base;
6794	unsigned long io_data = hw->io_base + 4;
6795
6796	e1000_io_write(hw, io_addr, offset);
6797	e1000_io_write(hw, io_data, value);
6798	}
6799
6800	/******************************************************************************
6801	* Estimates the cable length.
6802	*
6803	* hw - Struct containing variables accessed by shared code
6804	* min_length - The estimated minimum length
6805	* max_length - The estimated maximum length
6806	*
6807	* returns: - E1000_ERR_XXX
6808	* E1000_SUCCESS
6809	*
6810	* This function always returns a ranged length (minimum & maximum).
6811	* So for M88 phy's, this function interprets the one value returned from the
6812	* register to the minimum and maximum range.
6813	* For IGP phy's, the function calculates the range by the AGC registers.
6814	*****************************************************************************/
6815	static int32_t
6816	e1000_get_cable_length(struct e1000_hw *hw,
6817	uint16_t *min_length,
6818	uint16_t *max_length)
6819	{
6820	int32_t ret_val;
6821	uint16_t agc_value = 0;
6822	uint16_t i, phy_data;
6823	uint16_t cable_length;
6824
6825	DEBUGFUNC("e1000_get_cable_length");
6826
6827	min_length = max_length = 0;
6828
6829	/* Use old method for Phy older than IGP */
6830	if (hw->phy_type == e1000_phy_m88) {
6831
6832	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
6833	&phy_data);
6834	if (ret_val)
6835	return ret_val;
6836	cable_length = (phy_data & M88E1000_PSSR_CABLE_LENGTH) >>
6837	M88E1000_PSSR_CABLE_LENGTH_SHIFT;
6838
6839	/* Convert the enum value to ranged values */
6840	switch (cable_length) {
6841	case e1000_cable_length_50:
6842	*min_length = 0;
6843	*max_length = e1000_igp_cable_length_50;
6844	break;
6845	case e1000_cable_length_50_80:
6846	*min_length = e1000_igp_cable_length_50;
6847	*max_length = e1000_igp_cable_length_80;
6848	break;
6849	case e1000_cable_length_80_110:
6850	*min_length = e1000_igp_cable_length_80;
6851	*max_length = e1000_igp_cable_length_110;
6852	break;
6853	case e1000_cable_length_110_140:
6854	*min_length = e1000_igp_cable_length_110;
6855	*max_length = e1000_igp_cable_length_140;
6856	break;
6857	case e1000_cable_length_140:
6858	*min_length = e1000_igp_cable_length_140;
6859	*max_length = e1000_igp_cable_length_170;
6860	break;
6861	default:
6862	return -E1000_ERR_PHY;
6863	break;
6864	}
6865	} else if (hw->phy_type == e1000_phy_gg82563) {
6866	ret_val = e1000_read_phy_reg(hw, GG82563_PHY_DSP_DISTANCE,
6867	&phy_data);
6868	if (ret_val)
6869	return ret_val;
6870	cable_length = phy_data & GG82563_DSPD_CABLE_LENGTH;
6871
6872	switch (cable_length) {
6873	case e1000_gg_cable_length_60:
6874	*min_length = 0;
6875	*max_length = e1000_igp_cable_length_60;
6876	break;
6877	case e1000_gg_cable_length_60_115:
6878	*min_length = e1000_igp_cable_length_60;
6879	*max_length = e1000_igp_cable_length_115;
6880	break;
6881	case e1000_gg_cable_length_115_150:
6882	*min_length = e1000_igp_cable_length_115;
6883	*max_length = e1000_igp_cable_length_150;
6884	break;
6885	case e1000_gg_cable_length_150:
6886	*min_length = e1000_igp_cable_length_150;
6887	*max_length = e1000_igp_cable_length_180;
6888	break;
6889	default:
6890	return -E1000_ERR_PHY;
6891	break;
6892	}
6893	} else if (hw->phy_type == e1000_phy_igp) { /* For IGP PHY */
6894	uint16_t cur_agc_value;
6895	uint16_t min_agc_value = IGP01E1000_AGC_LENGTH_TABLE_SIZE;
6896	uint16_t agc_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
6897	{IGP01E1000_PHY_AGC_A,
6898	IGP01E1000_PHY_AGC_B,
6899	IGP01E1000_PHY_AGC_C,
6900	IGP01E1000_PHY_AGC_D};
6901	/* Read the AGC registers for all channels */
6902	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
6903
6904	ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6905	if (ret_val)
6906	return ret_val;
6907
6908	cur_agc_value = phy_data >> IGP01E1000_AGC_LENGTH_SHIFT;
6909
6910	/* Value bound check. */
6911	if ((cur_agc_value >= IGP01E1000_AGC_LENGTH_TABLE_SIZE - 1) \|\|
6912	(cur_agc_value == 0))
6913	return -E1000_ERR_PHY;
6914
6915	agc_value += cur_agc_value;
6916
6917	/* Update minimal AGC value. */
6918	if (min_agc_value > cur_agc_value)
6919	min_agc_value = cur_agc_value;
6920	}
6921
6922	/* Remove the minimal AGC result for length < 50m */
6923	if (agc_value < IGP01E1000_PHY_CHANNEL_NUM * e1000_igp_cable_length_50) {
6924	agc_value -= min_agc_value;
6925
6926	/* Get the average length of the remaining 3 channels */
6927	agc_value /= (IGP01E1000_PHY_CHANNEL_NUM - 1);
6928	} else {
6929	/* Get the average length of all the 4 channels. */
6930	agc_value /= IGP01E1000_PHY_CHANNEL_NUM;
6931	}
6932
6933	/* Set the range of the calculated length. */
6934	*min_length = ((e1000_igp_cable_length_table[agc_value] -
6935	IGP01E1000_AGC_RANGE) > 0) ?
6936	(e1000_igp_cable_length_table[agc_value] -
6937	IGP01E1000_AGC_RANGE) : 0;
6938	*max_length = e1000_igp_cable_length_table[agc_value] +
6939	IGP01E1000_AGC_RANGE;
6940	} else if (hw->phy_type == e1000_phy_igp_2 \|\|
6941	hw->phy_type == e1000_phy_igp_3) {
6942	uint16_t cur_agc_index, max_agc_index = 0;
6943	uint16_t min_agc_index = IGP02E1000_AGC_LENGTH_TABLE_SIZE - 1;
6944	uint16_t agc_reg_array[IGP02E1000_PHY_CHANNEL_NUM] =
6945	{IGP02E1000_PHY_AGC_A,
6946	IGP02E1000_PHY_AGC_B,
6947	IGP02E1000_PHY_AGC_C,
6948	IGP02E1000_PHY_AGC_D};
6949	/* Read the AGC registers for all channels */
6950	for (i = 0; i < IGP02E1000_PHY_CHANNEL_NUM; i++) {
6951	ret_val = e1000_read_phy_reg(hw, agc_reg_array[i], &phy_data);
6952	if (ret_val)
6953	return ret_val;
6954
6955	/* Getting bits 15:9, which represent the combination of course and
6956	* fine gain values. The result is a number that can be put into
6957	* the lookup table to obtain the approximate cable length. */
6958	cur_agc_index = (phy_data >> IGP02E1000_AGC_LENGTH_SHIFT) &
6959	IGP02E1000_AGC_LENGTH_MASK;
6960
6961	/* Array index bound check. */
6962	if ((cur_agc_index >= IGP02E1000_AGC_LENGTH_TABLE_SIZE) \|\|
6963	(cur_agc_index == 0))
6964	return -E1000_ERR_PHY;
6965
6966	/* Remove min & max AGC values from calculation. */
6967	if (e1000_igp_2_cable_length_table[min_agc_index] >
6968	e1000_igp_2_cable_length_table[cur_agc_index])
6969	min_agc_index = cur_agc_index;
6970	if (e1000_igp_2_cable_length_table[max_agc_index] <
6971	e1000_igp_2_cable_length_table[cur_agc_index])
6972	max_agc_index = cur_agc_index;
6973
6974	agc_value += e1000_igp_2_cable_length_table[cur_agc_index];
6975	}
6976
6977	agc_value -= (e1000_igp_2_cable_length_table[min_agc_index] +
6978	e1000_igp_2_cable_length_table[max_agc_index]);
6979	agc_value /= (IGP02E1000_PHY_CHANNEL_NUM - 2);
6980
6981	/* Calculate cable length with the error range of +/- 10 meters. */
6982	*min_length = ((agc_value - IGP02E1000_AGC_RANGE) > 0) ?
6983	(agc_value - IGP02E1000_AGC_RANGE) : 0;
6984	*max_length = agc_value + IGP02E1000_AGC_RANGE;
6985	}
6986
6987	return E1000_SUCCESS;
6988	}
6989
6990	/******************************************************************************
6991	* Check the cable polarity
6992	*
6993	* hw - Struct containing variables accessed by shared code
6994	* polarity - output parameter : 0 - Polarity is not reversed
6995	* 1 - Polarity is reversed.
6996	*
6997	* returns: - E1000_ERR_XXX
6998	* E1000_SUCCESS
6999	*
7000	* For phy's older then IGP, this function simply reads the polarity bit in the
7001	* Phy Status register. For IGP phy's, this bit is valid only if link speed is
7002	* 10 Mbps. If the link speed is 100 Mbps there is no polarity so this bit will
7003	* return 0. If the link speed is 1000 Mbps the polarity status is in the
7004	* IGP01E1000_PHY_PCS_INIT_REG.
7005	*****************************************************************************/
7006	static int32_t
7007	e1000_check_polarity(struct e1000_hw *hw,
7008	e1000_rev_polarity *polarity)
7009	{
7010	int32_t ret_val;
7011	uint16_t phy_data;
7012
7013	DEBUGFUNC("e1000_check_polarity");
7014
7015	if ((hw->phy_type == e1000_phy_m88) \|\|
7016	(hw->phy_type == e1000_phy_gg82563)) {
7017	/* return the Polarity bit in the Status register. */
7018	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7019	&phy_data);
7020	if (ret_val)
7021	return ret_val;
7022	*polarity = ((phy_data & M88E1000_PSSR_REV_POLARITY) >>
7023	M88E1000_PSSR_REV_POLARITY_SHIFT) ?
7024	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7025
7026	} else if (hw->phy_type == e1000_phy_igp \|\|
7027	hw->phy_type == e1000_phy_igp_3 \|\|
7028	hw->phy_type == e1000_phy_igp_2) {
7029	/* Read the Status register to check the speed */
7030	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_STATUS,
7031	&phy_data);
7032	if (ret_val)
7033	return ret_val;
7034
7035	/* If speed is 1000 Mbps, must read the IGP01E1000_PHY_PCS_INIT_REG to
7036	* find the polarity status */
7037	if ((phy_data & IGP01E1000_PSSR_SPEED_MASK) ==
7038	IGP01E1000_PSSR_SPEED_1000MBPS) {
7039
7040	/* Read the GIG initialization PCS register (0x00B4) */
7041	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PCS_INIT_REG,
7042	&phy_data);
7043	if (ret_val)
7044	return ret_val;
7045
7046	/* Check the polarity bits */
7047	*polarity = (phy_data & IGP01E1000_PHY_POLARITY_MASK) ?
7048	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7049	} else {
7050	/* For 10 Mbps, read the polarity bit in the status register. (for
7051	* 100 Mbps this bit is always 0) */
7052	*polarity = (phy_data & IGP01E1000_PSSR_POLARITY_REVERSED) ?
7053	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7054	}
7055	} else if (hw->phy_type == e1000_phy_ife) {
7056	ret_val = e1000_read_phy_reg(hw, IFE_PHY_EXTENDED_STATUS_CONTROL,
7057	&phy_data);
7058	if (ret_val)
7059	return ret_val;
7060	*polarity = ((phy_data & IFE_PESC_POLARITY_REVERSED) >>
7061	IFE_PESC_POLARITY_REVERSED_SHIFT) ?
7062	e1000_rev_polarity_reversed : e1000_rev_polarity_normal;
7063	}
7064	return E1000_SUCCESS;
7065	}
7066
7067	/******************************************************************************
7068	* Check if Downshift occured
7069	*
7070	* hw - Struct containing variables accessed by shared code
7071	* downshift - output parameter : 0 - No Downshift ocured.
7072	* 1 - Downshift ocured.
7073	*
7074	* returns: - E1000_ERR_XXX
7075	* E1000_SUCCESS
7076	*
7077	* For phy's older then IGP, this function reads the Downshift bit in the Phy
7078	* Specific Status register. For IGP phy's, it reads the Downgrade bit in the
7079	* Link Health register. In IGP this bit is latched high, so the driver must
7080	* read it immediately after link is established.
7081	*****************************************************************************/
7082	static int32_t
7083	e1000_check_downshift(struct e1000_hw *hw)
7084	{
7085	int32_t ret_val;
7086	uint16_t phy_data;
7087
7088	DEBUGFUNC("e1000_check_downshift");
7089
7090	if (hw->phy_type == e1000_phy_igp \|\|
7091	hw->phy_type == e1000_phy_igp_3 \|\|
7092	hw->phy_type == e1000_phy_igp_2) {
7093	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_LINK_HEALTH,
7094	&phy_data);
7095	if (ret_val)
7096	return ret_val;
7097
7098	hw->speed_downgraded = (phy_data & IGP01E1000_PLHR_SS_DOWNGRADE) ? 1 : 0;
7099	} else if ((hw->phy_type == e1000_phy_m88) \|\|
7100	(hw->phy_type == e1000_phy_gg82563)) {
7101	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_STATUS,
7102	&phy_data);
7103	if (ret_val)
7104	return ret_val;
7105
7106	hw->speed_downgraded = (phy_data & M88E1000_PSSR_DOWNSHIFT) >>
7107	M88E1000_PSSR_DOWNSHIFT_SHIFT;
7108	} else if (hw->phy_type == e1000_phy_ife) {
7109	/* e1000_phy_ife supports 10/100 speed only */
7110	hw->speed_downgraded = FALSE;
7111	}
7112
7113	return E1000_SUCCESS;
7114	}
7115
7116	/*****************************************************************************
7117	*
7118	* 82541_rev_2 & 82547_rev_2 have the capability to configure the DSP when a
7119	* gigabit link is achieved to improve link quality.
7120	*
7121	* hw: Struct containing variables accessed by shared code
7122	*
7123	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7124	* E1000_SUCCESS at any other case.
7125	*
7126	****************************************************************************/
7127
7128	static int32_t
7129	e1000_config_dsp_after_link_change(struct e1000_hw *hw,
7130	boolean_t link_up)
7131	{
7132	int32_t ret_val;
7133	uint16_t phy_data, phy_saved_data, speed, duplex, i;
7134	uint16_t dsp_reg_array[IGP01E1000_PHY_CHANNEL_NUM] =
7135	{IGP01E1000_PHY_AGC_PARAM_A,
7136	IGP01E1000_PHY_AGC_PARAM_B,
7137	IGP01E1000_PHY_AGC_PARAM_C,
7138	IGP01E1000_PHY_AGC_PARAM_D};
7139	uint16_t min_length, max_length;
7140
7141	DEBUGFUNC("e1000_config_dsp_after_link_change");
7142
7143	if (hw->phy_type != e1000_phy_igp)
7144	return E1000_SUCCESS;
7145
7146	if (link_up) {
7147	ret_val = e1000_get_speed_and_duplex(hw, &speed, &duplex);
7148	if (ret_val) {
7149	DEBUGOUT("Error getting link speed and duplex\n");
7150	return ret_val;
7151	}
7152
7153	if (speed == SPEED_1000) {
7154
7155	ret_val = e1000_get_cable_length(hw, &min_length, &max_length);
7156	if (ret_val)
7157	return ret_val;
7158
7159	if ((hw->dsp_config_state == e1000_dsp_config_enabled) &&
7160	min_length >= e1000_igp_cable_length_50) {
7161
7162	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7163	ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i],
7164	&phy_data);
7165	if (ret_val)
7166	return ret_val;
7167
7168	phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7169
7170	ret_val = e1000_write_phy_reg(hw, dsp_reg_array[i],
7171	phy_data);
7172	if (ret_val)
7173	return ret_val;
7174	}
7175	hw->dsp_config_state = e1000_dsp_config_activated;
7176	}
7177
7178	if ((hw->ffe_config_state == e1000_ffe_config_enabled) &&
7179	(min_length < e1000_igp_cable_length_50)) {
7180
7181	uint16_t ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_20;
7182	uint32_t idle_errs = 0;
7183
7184	/* clear previous idle error counts */
7185	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7186	&phy_data);
7187	if (ret_val)
7188	return ret_val;
7189
7190	for (i = 0; i < ffe_idle_err_timeout; i++) {
7191	udelay(1000);
7192	ret_val = e1000_read_phy_reg(hw, PHY_1000T_STATUS,
7193	&phy_data);
7194	if (ret_val)
7195	return ret_val;
7196
7197	idle_errs += (phy_data & SR_1000T_IDLE_ERROR_CNT);
7198	if (idle_errs > SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT) {
7199	hw->ffe_config_state = e1000_ffe_config_active;
7200
7201	ret_val = e1000_write_phy_reg(hw,
7202	IGP01E1000_PHY_DSP_FFE,
7203	IGP01E1000_PHY_DSP_FFE_CM_CP);
7204	if (ret_val)
7205	return ret_val;
7206	break;
7207	}
7208
7209	if (idle_errs)
7210	ffe_idle_err_timeout = FFE_IDLE_ERR_COUNT_TIMEOUT_100;
7211	}
7212	}
7213	}
7214	} else {
7215	if (hw->dsp_config_state == e1000_dsp_config_activated) {
7216	/* Save off the current value of register 0x2F5B to be restored at
7217	* the end of the routines. */
7218	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7219
7220	if (ret_val)
7221	return ret_val;
7222
7223	/* Disable the PHY transmitter */
7224	ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7225
7226	if (ret_val)
7227	return ret_val;
7228
7229	mdelay(20);
7230
7231	ret_val = e1000_write_phy_reg(hw, 0x0000,
7232	IGP01E1000_IEEE_FORCE_GIGA);
7233	if (ret_val)
7234	return ret_val;
7235	for (i = 0; i < IGP01E1000_PHY_CHANNEL_NUM; i++) {
7236	ret_val = e1000_read_phy_reg(hw, dsp_reg_array[i], &phy_data);
7237	if (ret_val)
7238	return ret_val;
7239
7240	phy_data &= ~IGP01E1000_PHY_EDAC_MU_INDEX;
7241	phy_data \|= IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS;
7242
7243	ret_val = e1000_write_phy_reg(hw,dsp_reg_array[i], phy_data);
7244	if (ret_val)
7245	return ret_val;
7246	}
7247
7248	ret_val = e1000_write_phy_reg(hw, 0x0000,
7249	IGP01E1000_IEEE_RESTART_AUTONEG);
7250	if (ret_val)
7251	return ret_val;
7252
7253	mdelay(20);
7254
7255	/* Now enable the transmitter */
7256	ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7257
7258	if (ret_val)
7259	return ret_val;
7260
7261	hw->dsp_config_state = e1000_dsp_config_enabled;
7262	}
7263
7264	if (hw->ffe_config_state == e1000_ffe_config_active) {
7265	/* Save off the current value of register 0x2F5B to be restored at
7266	* the end of the routines. */
7267	ret_val = e1000_read_phy_reg(hw, 0x2F5B, &phy_saved_data);
7268
7269	if (ret_val)
7270	return ret_val;
7271
7272	/* Disable the PHY transmitter */
7273	ret_val = e1000_write_phy_reg(hw, 0x2F5B, 0x0003);
7274
7275	if (ret_val)
7276	return ret_val;
7277
7278	mdelay(20);
7279
7280	ret_val = e1000_write_phy_reg(hw, 0x0000,
7281	IGP01E1000_IEEE_FORCE_GIGA);
7282	if (ret_val)
7283	return ret_val;
7284	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_DSP_FFE,
7285	IGP01E1000_PHY_DSP_FFE_DEFAULT);
7286	if (ret_val)
7287	return ret_val;
7288
7289	ret_val = e1000_write_phy_reg(hw, 0x0000,
7290	IGP01E1000_IEEE_RESTART_AUTONEG);
7291	if (ret_val)
7292	return ret_val;
7293
7294	mdelay(20);
7295
7296	/* Now enable the transmitter */
7297	ret_val = e1000_write_phy_reg(hw, 0x2F5B, phy_saved_data);
7298
7299	if (ret_val)
7300	return ret_val;
7301
7302	hw->ffe_config_state = e1000_ffe_config_enabled;
7303	}
7304	}
7305	return E1000_SUCCESS;
7306	}
7307
7308	/*****************************************************************************
7309	* Set PHY to class A mode
7310	* Assumes the following operations will follow to enable the new class mode.
7311	* 1. Do a PHY soft reset
7312	* 2. Restart auto-negotiation or force link.
7313	*
7314	* hw - Struct containing variables accessed by shared code
7315	****************************************************************************/
7316	static int32_t
7317	e1000_set_phy_mode(struct e1000_hw *hw)
7318	{
7319	int32_t ret_val;
7320	uint16_t eeprom_data;
7321
7322	DEBUGFUNC("e1000_set_phy_mode");
7323
7324	if ((hw->mac_type == e1000_82545_rev_3) &&
7325	(hw->media_type == e1000_media_type_copper)) {
7326	ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD, 1, &eeprom_data);
7327	if (ret_val) {
7328	return ret_val;
7329	}
7330
7331	if ((eeprom_data != EEPROM_RESERVED_WORD) &&
7332	(eeprom_data & EEPROM_PHY_CLASS_A)) {
7333	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x000B);
7334	if (ret_val)
7335	return ret_val;
7336	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x8104);
7337	if (ret_val)
7338	return ret_val;
7339
7340	hw->phy_reset_disable = FALSE;
7341	}
7342	}
7343
7344	return E1000_SUCCESS;
7345	}
7346
7347	/*****************************************************************************
7348	*
7349	* This function sets the lplu state according to the active flag. When
7350	* activating lplu this function also disables smart speed and vise versa.
7351	* lplu will not be activated unless the device autonegotiation advertisment
7352	* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7353	* hw: Struct containing variables accessed by shared code
7354	* active - true to enable lplu false to disable lplu.
7355	*
7356	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7357	* E1000_SUCCESS at any other case.
7358	*
7359	****************************************************************************/
7360
7361	static int32_t
7362	e1000_set_d3_lplu_state(struct e1000_hw *hw,
7363	boolean_t active)
7364	{
7365	uint32_t phy_ctrl = 0;
7366	int32_t ret_val;
7367	uint16_t phy_data;
7368	DEBUGFUNC("e1000_set_d3_lplu_state");
7369
7370	if (hw->phy_type != e1000_phy_igp && hw->phy_type != e1000_phy_igp_2
7371	&& hw->phy_type != e1000_phy_igp_3)
7372	return E1000_SUCCESS;
7373
7374	/* During driver activity LPLU should not be used or it will attain link
7375	* from the lowest speeds starting from 10Mbps. The capability is used for
7376	* Dx transitions and states */
7377	if (hw->mac_type == e1000_82541_rev_2 \|\| hw->mac_type == e1000_82547_rev_2) {
7378	ret_val = e1000_read_phy_reg(hw, IGP01E1000_GMII_FIFO, &phy_data);
7379	if (ret_val)
7380	return ret_val;
7381	} else if (hw->mac_type == e1000_ich8lan) {
7382	/* MAC writes into PHY register based on the state transition
7383	* and start auto-negotiation. SW driver can overwrite the settings
7384	* in CSR PHY power control E1000_PHY_CTRL register. */
7385	phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7386	} else {
7387	ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7388	if (ret_val)
7389	return ret_val;
7390	}
7391
7392	if (!active) {
7393	if (hw->mac_type == e1000_82541_rev_2 \|\|
7394	hw->mac_type == e1000_82547_rev_2) {
7395	phy_data &= ~IGP01E1000_GMII_FLEX_SPD;
7396	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7397	if (ret_val)
7398	return ret_val;
7399	} else {
7400	if (hw->mac_type == e1000_ich8lan) {
7401	phy_ctrl &= ~E1000_PHY_CTRL_NOND0A_LPLU;
7402	E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7403	} else {
7404	phy_data &= ~IGP02E1000_PM_D3_LPLU;
7405	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7406	phy_data);
7407	if (ret_val)
7408	return ret_val;
7409	}
7410	}
7411
7412	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7413	* Dx states where the power conservation is most important. During
7414	* driver activity we should enable SmartSpeed, so performance is
7415	* maintained. */
7416	if (hw->smart_speed == e1000_smart_speed_on) {
7417	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7418	&phy_data);
7419	if (ret_val)
7420	return ret_val;
7421
7422	phy_data \|= IGP01E1000_PSCFR_SMART_SPEED;
7423	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7424	phy_data);
7425	if (ret_val)
7426	return ret_val;
7427	} else if (hw->smart_speed == e1000_smart_speed_off) {
7428	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7429	&phy_data);
7430	if (ret_val)
7431	return ret_val;
7432
7433	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7434	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7435	phy_data);
7436	if (ret_val)
7437	return ret_val;
7438	}
7439
7440	} else if ((hw->autoneg_advertised == AUTONEG_ADVERTISE_SPEED_DEFAULT) \|\|
7441	(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_ALL ) \|\|
7442	(hw->autoneg_advertised == AUTONEG_ADVERTISE_10_100_ALL)) {
7443
7444	if (hw->mac_type == e1000_82541_rev_2 \|\|
7445	hw->mac_type == e1000_82547_rev_2) {
7446	phy_data \|= IGP01E1000_GMII_FLEX_SPD;
7447	ret_val = e1000_write_phy_reg(hw, IGP01E1000_GMII_FIFO, phy_data);
7448	if (ret_val)
7449	return ret_val;
7450	} else {
7451	if (hw->mac_type == e1000_ich8lan) {
7452	phy_ctrl \|= E1000_PHY_CTRL_NOND0A_LPLU;
7453	E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7454	} else {
7455	phy_data \|= IGP02E1000_PM_D3_LPLU;
7456	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT,
7457	phy_data);
7458	if (ret_val)
7459	return ret_val;
7460	}
7461	}
7462
7463	/* When LPLU is enabled we should disable SmartSpeed */
7464	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7465	if (ret_val)
7466	return ret_val;
7467
7468	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7469	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7470	if (ret_val)
7471	return ret_val;
7472
7473	}
7474	return E1000_SUCCESS;
7475	}
7476
7477	/*****************************************************************************
7478	*
7479	* This function sets the lplu d0 state according to the active flag. When
7480	* activating lplu this function also disables smart speed and vise versa.
7481	* lplu will not be activated unless the device autonegotiation advertisment
7482	* meets standards of either 10 or 10/100 or 10/100/1000 at all duplexes.
7483	* hw: Struct containing variables accessed by shared code
7484	* active - true to enable lplu false to disable lplu.
7485	*
7486	* returns: - E1000_ERR_PHY if fail to read/write the PHY
7487	* E1000_SUCCESS at any other case.
7488	*
7489	****************************************************************************/
7490
7491	static int32_t
7492	e1000_set_d0_lplu_state(struct e1000_hw *hw,
7493	boolean_t active)
7494	{
7495	uint32_t phy_ctrl = 0;
7496	int32_t ret_val;
7497	uint16_t phy_data;
7498	DEBUGFUNC("e1000_set_d0_lplu_state");
7499
7500	if (hw->mac_type <= e1000_82547_rev_2)
7501	return E1000_SUCCESS;
7502
7503	if (hw->mac_type == e1000_ich8lan) {
7504	phy_ctrl = E1000_READ_REG(hw, PHY_CTRL);
7505	} else {
7506	ret_val = e1000_read_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, &phy_data);
7507	if (ret_val)
7508	return ret_val;
7509	}
7510
7511	if (!active) {
7512	if (hw->mac_type == e1000_ich8lan) {
7513	phy_ctrl &= ~E1000_PHY_CTRL_D0A_LPLU;
7514	E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7515	} else {
7516	phy_data &= ~IGP02E1000_PM_D0_LPLU;
7517	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7518	if (ret_val)
7519	return ret_val;
7520	}
7521
7522	/* LPLU and SmartSpeed are mutually exclusive. LPLU is used during
7523	* Dx states where the power conservation is most important. During
7524	* driver activity we should enable SmartSpeed, so performance is
7525	* maintained. */
7526	if (hw->smart_speed == e1000_smart_speed_on) {
7527	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7528	&phy_data);
7529	if (ret_val)
7530	return ret_val;
7531
7532	phy_data \|= IGP01E1000_PSCFR_SMART_SPEED;
7533	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7534	phy_data);
7535	if (ret_val)
7536	return ret_val;
7537	} else if (hw->smart_speed == e1000_smart_speed_off) {
7538	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7539	&phy_data);
7540	if (ret_val)
7541	return ret_val;
7542
7543	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7544	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
7545	phy_data);
7546	if (ret_val)
7547	return ret_val;
7548	}
7549
7550
7551	} else {
7552
7553	if (hw->mac_type == e1000_ich8lan) {
7554	phy_ctrl \|= E1000_PHY_CTRL_D0A_LPLU;
7555	E1000_WRITE_REG(hw, PHY_CTRL, phy_ctrl);
7556	} else {
7557	phy_data \|= IGP02E1000_PM_D0_LPLU;
7558	ret_val = e1000_write_phy_reg(hw, IGP02E1000_PHY_POWER_MGMT, phy_data);
7559	if (ret_val)
7560	return ret_val;
7561	}
7562
7563	/* When LPLU is enabled we should disable SmartSpeed */
7564	ret_val = e1000_read_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, &phy_data);
7565	if (ret_val)
7566	return ret_val;
7567
7568	phy_data &= ~IGP01E1000_PSCFR_SMART_SPEED;
7569	ret_val = e1000_write_phy_reg(hw, IGP01E1000_PHY_PORT_CONFIG, phy_data);
7570	if (ret_val)
7571	return ret_val;
7572
7573	}
7574	return E1000_SUCCESS;
7575	}
7576
7577	/******************************************************************************
7578	* Change VCO speed register to improve Bit Error Rate performance of SERDES.
7579	*
7580	* hw - Struct containing variables accessed by shared code
7581	*****************************************************************************/
7582	static int32_t
7583	e1000_set_vco_speed(struct e1000_hw *hw)
7584	{
7585	int32_t ret_val;
7586	uint16_t default_page = 0;
7587	uint16_t phy_data;
7588
7589	DEBUGFUNC("e1000_set_vco_speed");
7590
7591	switch (hw->mac_type) {
7592	case e1000_82545_rev_3:
7593	case e1000_82546_rev_3:
7594	break;
7595	default:
7596	return E1000_SUCCESS;
7597	}
7598
7599	/* Set PHY register 30, page 5, bit 8 to 0 */
7600
7601	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, &default_page);
7602	if (ret_val)
7603	return ret_val;
7604
7605	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0005);
7606	if (ret_val)
7607	return ret_val;
7608
7609	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7610	if (ret_val)
7611	return ret_val;
7612
7613	phy_data &= ~M88E1000_PHY_VCO_REG_BIT8;
7614	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7615	if (ret_val)
7616	return ret_val;
7617
7618	/* Set PHY register 30, page 4, bit 11 to 1 */
7619
7620	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0004);
7621	if (ret_val)
7622	return ret_val;
7623
7624	ret_val = e1000_read_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, &phy_data);
7625	if (ret_val)
7626	return ret_val;
7627
7628	phy_data \|= M88E1000_PHY_VCO_REG_BIT11;
7629	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, phy_data);
7630	if (ret_val)
7631	return ret_val;
7632
7633	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, default_page);
7634	if (ret_val)
7635	return ret_val;
7636
7637	return E1000_SUCCESS;
7638	}
7639
7640
7641	/*****************************************************************************
7642	* This function reads the cookie from ARC ram.
7643	*
7644	* returns: - E1000_SUCCESS .
7645	****************************************************************************/
7646	static int32_t
7647	e1000_host_if_read_cookie(struct e1000_hw * hw, uint8_t *buffer)
7648	{
7649	uint8_t i;
7650	uint32_t offset = E1000_MNG_DHCP_COOKIE_OFFSET;
7651	uint8_t length = E1000_MNG_DHCP_COOKIE_LENGTH;
7652
7653	length = (length >> 2);
7654	offset = (offset >> 2);
7655
7656	for (i = 0; i < length; i++) {
7657	((uint32_t ) buffer + i) =
7658	E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset + i);
7659	}
7660	return E1000_SUCCESS;
7661	}
7662
7663
7664	/*****************************************************************************
7665	* This function checks whether the HOST IF is enabled for command operaton
7666	* and also checks whether the previous command is completed.
7667	* It busy waits in case of previous command is not completed.
7668	*
7669	* returns: - E1000_ERR_HOST_INTERFACE_COMMAND in case if is not ready or
7670	* timeout
7671	* - E1000_SUCCESS for success.
7672	****************************************************************************/
7673	static int32_t
7674	e1000_mng_enable_host_if(struct e1000_hw * hw)
7675	{
7676	uint32_t hicr;
7677	uint8_t i;
7678
7679	/* Check that the host interface is enabled. */
7680	hicr = E1000_READ_REG(hw, HICR);
7681	if ((hicr & E1000_HICR_EN) == 0) {
7682	DEBUGOUT("E1000_HOST_EN bit disabled.\n");
7683	return -E1000_ERR_HOST_INTERFACE_COMMAND;
7684	}
7685	/* check the previous command is completed */
7686	for (i = 0; i < E1000_MNG_DHCP_COMMAND_TIMEOUT; i++) {
7687	hicr = E1000_READ_REG(hw, HICR);
7688	if (!(hicr & E1000_HICR_C))
7689	break;
7690	mdelay(1);
7691	}
7692
7693	if (i == E1000_MNG_DHCP_COMMAND_TIMEOUT) {
7694	DEBUGOUT("Previous command timeout failed .\n");
7695	return -E1000_ERR_HOST_INTERFACE_COMMAND;
7696	}
7697	return E1000_SUCCESS;
7698	}
7699
7700	/*****************************************************************************
7701	* This function writes the buffer content at the offset given on the host if.
7702	* It also does alignment considerations to do the writes in most efficient way.
7703	* Also fills up the sum of the buffer in *buffer parameter.
7704	*
7705	* returns - E1000_SUCCESS for success.
7706	****************************************************************************/
7707	static int32_t
7708	e1000_mng_host_if_write(struct e1000_hw * hw, uint8_t *buffer,
7709	uint16_t length, uint16_t offset, uint8_t *sum)
7710	{
7711	uint8_t *tmp;
7712	uint8_t *bufptr = buffer;
7713	uint32_t data = 0;
7714	uint16_t remaining, i, j, prev_bytes;
7715
7716	/* sum = only sum of the data and it is not checksum */
7717
7718	if (length == 0 \|\| offset + length > E1000_HI_MAX_MNG_DATA_LENGTH) {
7719	return -E1000_ERR_PARAM;
7720	}
7721
7722	tmp = (uint8_t *)&data;
7723	prev_bytes = offset & 0x3;
7724	offset &= 0xFFFC;
7725	offset >>= 2;
7726
7727	if (prev_bytes) {
7728	data = E1000_READ_REG_ARRAY_DWORD(hw, HOST_IF, offset);
7729	for (j = prev_bytes; j < sizeof(uint32_t); j++) {
7730	(tmp + j) = bufptr++;
7731	sum += (tmp + j);
7732	}
7733	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset, data);
7734	length -= j - prev_bytes;
7735	offset++;
7736	}
7737
7738	remaining = length & 0x3;
7739	length -= remaining;
7740
7741	/* Calculate length in DWORDs */
7742	length >>= 2;
7743
7744	/* The device driver writes the relevant command block into the
7745	* ram area. */
7746	for (i = 0; i < length; i++) {
7747	for (j = 0; j < sizeof(uint32_t); j++) {
7748	(tmp + j) = bufptr++;
7749	sum += (tmp + j);
7750	}
7751
7752	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7753	}
7754	if (remaining) {
7755	for (j = 0; j < sizeof(uint32_t); j++) {
7756	if (j < remaining)
7757	(tmp + j) = bufptr++;
7758	else
7759	*(tmp + j) = 0;
7760
7761	sum += (tmp + j);
7762	}
7763	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, offset + i, data);
7764	}
7765
7766	return E1000_SUCCESS;
7767	}
7768
7769
7770	/*****************************************************************************
7771	* This function writes the command header after does the checksum calculation.
7772	*
7773	* returns - E1000_SUCCESS for success.
7774	****************************************************************************/
7775	static int32_t
7776	e1000_mng_write_cmd_header(struct e1000_hw * hw,
7777	struct e1000_host_mng_command_header * hdr)
7778	{
7779	uint16_t i;
7780	uint8_t sum;
7781	uint8_t *buffer;
7782
7783	/* Write the whole command header structure which includes sum of
7784	* the buffer */
7785
7786	uint16_t length = sizeof(struct e1000_host_mng_command_header);
7787
7788	sum = hdr->checksum;
7789	hdr->checksum = 0;
7790
7791	buffer = (uint8_t *) hdr;
7792	i = length;
7793	while (i--)
7794	sum += buffer[i];
7795
7796	hdr->checksum = 0 - sum;
7797
7798	length >>= 2;
7799	/* The device driver writes the relevant command block into the ram area. */
7800	for (i = 0; i < length; i++) {
7801	E1000_WRITE_REG_ARRAY_DWORD(hw, HOST_IF, i, ((uint32_t ) hdr + i));
7802	E1000_WRITE_FLUSH(hw);
7803	}
7804
7805	return E1000_SUCCESS;
7806	}
7807
7808
7809	/*****************************************************************************
7810	* This function indicates to ARC that a new command is pending which completes
7811	* one write operation by the driver.
7812	*
7813	* returns - E1000_SUCCESS for success.
7814	****************************************************************************/
7815	static int32_t
7816	e1000_mng_write_commit(struct e1000_hw * hw)
7817	{
7818	uint32_t hicr;
7819
7820	hicr = E1000_READ_REG(hw, HICR);
7821	/* Setting this bit tells the ARC that a new command is pending. */
7822	E1000_WRITE_REG(hw, HICR, hicr \| E1000_HICR_C);
7823
7824	return E1000_SUCCESS;
7825	}
7826
7827
7828	/*****************************************************************************
7829	* This function checks the mode of the firmware.
7830	*
7831	* returns - TRUE when the mode is IAMT or FALSE.
7832	****************************************************************************/
7833	boolean_t
7834	e1000_check_mng_mode(struct e1000_hw *hw)
7835	{
7836	uint32_t fwsm;
7837
7838	fwsm = E1000_READ_REG(hw, FWSM);
7839
7840	if (hw->mac_type == e1000_ich8lan) {
7841	if ((fwsm & E1000_FWSM_MODE_MASK) ==
7842	(E1000_MNG_ICH_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7843	return TRUE;
7844	} else if ((fwsm & E1000_FWSM_MODE_MASK) ==
7845	(E1000_MNG_IAMT_MODE << E1000_FWSM_MODE_SHIFT))
7846	return TRUE;
7847
7848	return FALSE;
7849	}
7850
7851
7852	/*****************************************************************************
7853	* This function writes the dhcp info .
7854	****************************************************************************/
7855	int32_t
7856	e1000_mng_write_dhcp_info(struct e1000_hw * hw, uint8_t *buffer,
7857	uint16_t length)
7858	{
7859	int32_t ret_val;
7860	struct e1000_host_mng_command_header hdr;
7861
7862	hdr.command_id = E1000_MNG_DHCP_TX_PAYLOAD_CMD;
7863	hdr.command_length = length;
7864	hdr.reserved1 = 0;
7865	hdr.reserved2 = 0;
7866	hdr.checksum = 0;
7867
7868	ret_val = e1000_mng_enable_host_if(hw);
7869	if (ret_val == E1000_SUCCESS) {
7870	ret_val = e1000_mng_host_if_write(hw, buffer, length, sizeof(hdr),
7871	&(hdr.checksum));
7872	if (ret_val == E1000_SUCCESS) {
7873	ret_val = e1000_mng_write_cmd_header(hw, &hdr);
7874	if (ret_val == E1000_SUCCESS)
7875	ret_val = e1000_mng_write_commit(hw);
7876	}
7877	}
7878	return ret_val;
7879	}
7880
7881
7882	/*****************************************************************************
7883	* This function calculates the checksum.
7884	*
7885	* returns - checksum of buffer contents.
7886	****************************************************************************/
7887	static uint8_t
7888	e1000_calculate_mng_checksum(char *buffer, uint32_t length)
7889	{
7890	uint8_t sum = 0;
7891	uint32_t i;
7892
7893	if (!buffer)
7894	return 0;
7895
7896	for (i=0; i < length; i++)
7897	sum += buffer[i];
7898
7899	return (uint8_t) (0 - sum);
7900	}
7901
7902	/*****************************************************************************
7903	* This function checks whether tx pkt filtering needs to be enabled or not.
7904	*
7905	* returns - TRUE for packet filtering or FALSE.
7906	****************************************************************************/
7907	boolean_t
7908	e1000_enable_tx_pkt_filtering(struct e1000_hw *hw)
7909	{
7910	/* called in init as well as watchdog timer functions */
7911
7912	int32_t ret_val, checksum;
7913	boolean_t tx_filter = FALSE;
7914	struct e1000_host_mng_dhcp_cookie *hdr = &(hw->mng_cookie);
7915	uint8_t buffer = (uint8_t ) &(hw->mng_cookie);
7916
7917	if (e1000_check_mng_mode(hw)) {
7918	ret_val = e1000_mng_enable_host_if(hw);
7919	if (ret_val == E1000_SUCCESS) {
7920	ret_val = e1000_host_if_read_cookie(hw, buffer);
7921	if (ret_val == E1000_SUCCESS) {
7922	checksum = hdr->checksum;
7923	hdr->checksum = 0;
7924	if ((hdr->signature == E1000_IAMT_SIGNATURE) &&
7925	checksum == e1000_calculate_mng_checksum((char *)buffer,
7926	E1000_MNG_DHCP_COOKIE_LENGTH)) {
7927	if (hdr->status &
7928	E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT)
7929	tx_filter = TRUE;
7930	} else
7931	tx_filter = TRUE;
7932	} else
7933	tx_filter = TRUE;
7934	}
7935	}
7936
7937	hw->tx_pkt_filtering = tx_filter;
7938	return tx_filter;
7939	}
7940
7941	/******************************************************************************
7942	* Verifies the hardware needs to allow ARPs to be processed by the host
7943	*
7944	* hw - Struct containing variables accessed by shared code
7945	*
7946	* returns: - TRUE/FALSE
7947	*
7948	*****************************************************************************/
7949	uint32_t
7950	e1000_enable_mng_pass_thru(struct e1000_hw *hw)
7951	{
7952	uint32_t manc;
7953	uint32_t fwsm, factps;
7954
7955	if (hw->asf_firmware_present) {
7956	manc = E1000_READ_REG(hw, MANC);
7957
7958	if (!(manc & E1000_MANC_RCV_TCO_EN) \|\|
7959	!(manc & E1000_MANC_EN_MAC_ADDR_FILTER))
7960	return FALSE;
7961	if (e1000_arc_subsystem_valid(hw) == TRUE) {
7962	fwsm = E1000_READ_REG(hw, FWSM);
7963	factps = E1000_READ_REG(hw, FACTPS);
7964
7965	if ((((fwsm & E1000_FWSM_MODE_MASK) >> E1000_FWSM_MODE_SHIFT) ==
7966	e1000_mng_mode_pt) && !(factps & E1000_FACTPS_MNGCG))
7967	return TRUE;
7968	} else
7969	if ((manc & E1000_MANC_SMBUS_EN) && !(manc & E1000_MANC_ASF_EN))
7970	return TRUE;
7971	}
7972	return FALSE;
7973	}
7974
7975	static int32_t
7976	e1000_polarity_reversal_workaround(struct e1000_hw *hw)
7977	{
7978	int32_t ret_val;
7979	uint16_t mii_status_reg;
7980	uint16_t i;
7981
7982	/* Polarity reversal workaround for forced 10F/10H links. */
7983
7984	/* Disable the transmitter on the PHY */
7985
7986	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
7987	if (ret_val)
7988	return ret_val;
7989	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFFF);
7990	if (ret_val)
7991	return ret_val;
7992
7993	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
7994	if (ret_val)
7995	return ret_val;
7996
7997	/* This loop will early-out if the NO link condition has been met. */
7998	for (i = PHY_FORCE_TIME; i > 0; i--) {
7999	/* Read the MII Status Register and wait for Link Status bit
8000	* to be clear.
8001	*/
8002
8003	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8004	if (ret_val)
8005	return ret_val;
8006
8007	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8008	if (ret_val)
8009	return ret_val;
8010
8011	if ((mii_status_reg & ~MII_SR_LINK_STATUS) == 0) break;
8012	mdelay(100);
8013	}
8014
8015	/* Recommended delay time after link has been lost */
8016	mdelay(1000);
8017
8018	/* Now we will re-enable th transmitter on the PHY */
8019
8020	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0019);
8021	if (ret_val)
8022	return ret_val;
8023	mdelay(50);
8024	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFFF0);
8025	if (ret_val)
8026	return ret_val;
8027	mdelay(50);
8028	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0xFF00);
8029	if (ret_val)
8030	return ret_val;
8031	mdelay(50);
8032	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_GEN_CONTROL, 0x0000);
8033	if (ret_val)
8034	return ret_val;
8035
8036	ret_val = e1000_write_phy_reg(hw, M88E1000_PHY_PAGE_SELECT, 0x0000);
8037	if (ret_val)
8038	return ret_val;
8039
8040	/* This loop will early-out if the link condition has been met. */
8041	for (i = PHY_FORCE_TIME; i > 0; i--) {
8042	/* Read the MII Status Register and wait for Link Status bit
8043	* to be set.
8044	*/
8045
8046	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8047	if (ret_val)
8048	return ret_val;
8049
8050	ret_val = e1000_read_phy_reg(hw, PHY_STATUS, &mii_status_reg);
8051	if (ret_val)
8052	return ret_val;
8053
8054	if (mii_status_reg & MII_SR_LINK_STATUS) break;
8055	mdelay(100);
8056	}
8057	return E1000_SUCCESS;
8058	}
8059
8060	/***************************************************************************
8061	*
8062	* Disables PCI-Express master access.
8063	*
8064	* hw: Struct containing variables accessed by shared code
8065	*
8066	* returns: - none.
8067	*
8068	***************************************************************************/
8069	static void
8070	e1000_set_pci_express_master_disable(struct e1000_hw *hw)
8071	{
8072	uint32_t ctrl;
8073
8074	DEBUGFUNC("e1000_set_pci_express_master_disable");
8075
8076	if (hw->bus_type != e1000_bus_type_pci_express)
8077	return;
8078
8079	ctrl = E1000_READ_REG(hw, CTRL);
8080	ctrl \|= E1000_CTRL_GIO_MASTER_DISABLE;
8081	E1000_WRITE_REG(hw, CTRL, ctrl);
8082	}
8083
8084	/*******************************************************************************
8085	*
8086	* Disables PCI-Express master access and verifies there are no pending requests
8087	*
8088	* hw: Struct containing variables accessed by shared code
8089	*
8090	* returns: - E1000_ERR_MASTER_REQUESTS_PENDING if master disable bit hasn't
8091	* caused the master requests to be disabled.
8092	* E1000_SUCCESS master requests disabled.
8093	*
8094	******************************************************************************/
8095	int32_t
8096	e1000_disable_pciex_master(struct e1000_hw *hw)
8097	{
8098	int32_t timeout = MASTER_DISABLE_TIMEOUT; /* 80ms */
8099
8100	DEBUGFUNC("e1000_disable_pciex_master");
8101
8102	if (hw->bus_type != e1000_bus_type_pci_express)
8103	return E1000_SUCCESS;
8104
8105	e1000_set_pci_express_master_disable(hw);
8106
8107	while (timeout) {
8108	if (!(E1000_READ_REG(hw, STATUS) & E1000_STATUS_GIO_MASTER_ENABLE))
8109	break;
8110	else
8111	udelay(100);
8112	timeout--;
8113	}
8114
8115	if (!timeout) {
8116	DEBUGOUT("Master requests are pending.\n");
8117	return -E1000_ERR_MASTER_REQUESTS_PENDING;
8118	}
8119
8120	return E1000_SUCCESS;
8121	}
8122
8123	/*******************************************************************************
8124	*
8125	* Check for EEPROM Auto Read bit done.
8126	*
8127	* hw: Struct containing variables accessed by shared code
8128	*
8129	* returns: - E1000_ERR_RESET if fail to reset MAC
8130	* E1000_SUCCESS at any other case.
8131	*
8132	******************************************************************************/
8133	static int32_t
8134	e1000_get_auto_rd_done(struct e1000_hw *hw)
8135	{
8136	int32_t timeout = AUTO_READ_DONE_TIMEOUT;
8137
8138	DEBUGFUNC("e1000_get_auto_rd_done");
8139
8140	switch (hw->mac_type) {
8141	default:
8142	msleep(5);
8143	break;
8144	case e1000_82571:
8145	case e1000_82572:
8146	case e1000_82573:
8147	case e1000_80003es2lan:
8148	case e1000_ich8lan:
8149	case e1000_82576:
8150	while (timeout) {
8151	if (E1000_READ_REG(hw, EECD) & E1000_EECD_AUTO_RD)
8152	break;
8153	else msleep(1);
8154	timeout--;
8155	}
8156
8157	if (!timeout) {
8158	DEBUGOUT("Auto read by HW from EEPROM has not completed.\n");
8159	return -E1000_ERR_RESET;
8160	}
8161	break;
8162	}
8163
8164	/* PHY configuration from NVM just starts after EECD_AUTO_RD sets to high.
8165	* Need to wait for PHY configuration completion before accessing NVM
8166	* and PHY. */
8167	if (hw->mac_type == e1000_82573)
8168	msleep(25);
8169
8170	return E1000_SUCCESS;
8171	}
8172
8173	/***************************************************************************
8174	* Checks if the PHY configuration is done
8175	*
8176	* hw: Struct containing variables accessed by shared code
8177	*
8178	* returns: - E1000_ERR_RESET if fail to reset MAC
8179	* E1000_SUCCESS at any other case.
8180	*
8181	***************************************************************************/
8182	static int32_t
8183	e1000_get_phy_cfg_done(struct e1000_hw *hw)
8184	{
8185	int32_t timeout = PHY_CFG_TIMEOUT;
8186	uint32_t cfg_mask = E1000_EEPROM_CFG_DONE;
8187
8188	DEBUGFUNC("e1000_get_phy_cfg_done");
8189
8190	switch (hw->mac_type) {
8191	default:
8192	mdelay(10);
8193	break;
8194	case e1000_80003es2lan:
8195	case e1000_82576:
8196	/* Separate _CFG_DONE_ bit for each port */
8197	if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
8198	cfg_mask = E1000_EEPROM_CFG_DONE_PORT_1;
8199	/* Fall Through */
8200	case e1000_82571:
8201	case e1000_82572:
8202	while (timeout) {
8203	if (E1000_READ_REG(hw, EEMNGCTL) & cfg_mask)
8204	break;
8205	else
8206	msleep(1);
8207	timeout--;
8208	}
8209	if (!timeout) {
8210	DEBUGOUT("MNG configuration cycle has not completed.\n");
8211	return -E1000_ERR_RESET;
8212	}
8213	break;
8214	}
8215
8216	return E1000_SUCCESS;
8217	}
8218
8219	/***************************************************************************
8220	*
8221	* Using the combination of SMBI and SWESMBI semaphore bits when resetting
8222	* adapter or Eeprom access.
8223	*
8224	* hw: Struct containing variables accessed by shared code
8225	*
8226	* returns: - E1000_ERR_EEPROM if fail to access EEPROM.
8227	* E1000_SUCCESS at any other case.
8228	*
8229	***************************************************************************/
8230	static int32_t
8231	e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
8232	{
8233	int32_t timeout;
8234	uint32_t swsm;
8235
8236	DEBUGFUNC("e1000_get_hw_eeprom_semaphore");
8237
8238	if (!hw->eeprom_semaphore_present)
8239	return E1000_SUCCESS;
8240
8241	if (hw->mac_type == e1000_80003es2lan) {
8242	/* Get the SW semaphore. */
8243	if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
8244	return -E1000_ERR_EEPROM;
8245	}
8246
8247	/* Get the FW semaphore. */
8248	timeout = hw->eeprom.word_size + 1;
8249	while (timeout) {
8250	swsm = E1000_READ_REG(hw, SWSM);
8251	swsm \|= E1000_SWSM_SWESMBI;
8252	E1000_WRITE_REG(hw, SWSM, swsm);
8253	/* if we managed to set the bit we got the semaphore. */
8254	swsm = E1000_READ_REG(hw, SWSM);
8255	if (swsm & E1000_SWSM_SWESMBI)
8256	break;
8257
8258	udelay(50);
8259	timeout--;
8260	}
8261
8262	if (!timeout) {
8263	/* Release semaphores */
8264	e1000_put_hw_eeprom_semaphore(hw);
8265	DEBUGOUT("Driver can't access the Eeprom - SWESMBI bit is set.\n");
8266	return -E1000_ERR_EEPROM;
8267	}
8268
8269	return E1000_SUCCESS;
8270	}
8271
8272	/***************************************************************************
8273	* This function clears HW semaphore bits.
8274	*
8275	* hw: Struct containing variables accessed by shared code
8276	*
8277	* returns: - None.
8278	*
8279	***************************************************************************/
8280	static void
8281	e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
8282	{
8283	uint32_t swsm;
8284
8285	DEBUGFUNC("e1000_put_hw_eeprom_semaphore");
8286
8287	if (!hw->eeprom_semaphore_present)
8288	return;
8289
8290	swsm = E1000_READ_REG(hw, SWSM);
8291	if (hw->mac_type == e1000_80003es2lan) {
8292	/* Release both semaphores. */
8293	swsm &= ~(E1000_SWSM_SMBI \| E1000_SWSM_SWESMBI);
8294	} else
8295	swsm &= ~(E1000_SWSM_SWESMBI);
8296	E1000_WRITE_REG(hw, SWSM, swsm);
8297	}
8298
8299	/***************************************************************************
8300	*
8301	* Obtaining software semaphore bit (SMBI) before resetting PHY.
8302	*
8303	* hw: Struct containing variables accessed by shared code
8304	*
8305	* returns: - E1000_ERR_RESET if fail to obtain semaphore.
8306	* E1000_SUCCESS at any other case.
8307	*
8308	***************************************************************************/
8309	static int32_t
8310	e1000_get_software_semaphore(struct e1000_hw *hw)
8311	{
8312	int32_t timeout = hw->eeprom.word_size + 1;
8313	uint32_t swsm;
8314
8315	DEBUGFUNC("e1000_get_software_semaphore");
8316
8317	if (hw->mac_type != e1000_80003es2lan) {
8318	return E1000_SUCCESS;
8319	}
8320
8321	while (timeout) {
8322	swsm = E1000_READ_REG(hw, SWSM);
8323	/* If SMBI bit cleared, it is now set and we hold the semaphore */
8324	if (!(swsm & E1000_SWSM_SMBI))
8325	break;
8326	mdelay(1);
8327	timeout--;
8328	}
8329
8330	if (!timeout) {
8331	DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
8332	return -E1000_ERR_RESET;
8333	}
8334
8335	return E1000_SUCCESS;
8336	}
8337
8338	/***************************************************************************
8339	*
8340	* Release semaphore bit (SMBI).
8341	*
8342	* hw: Struct containing variables accessed by shared code
8343	*
8344	***************************************************************************/
8345	static void
8346	e1000_release_software_semaphore(struct e1000_hw *hw)
8347	{
8348	uint32_t swsm;
8349
8350	DEBUGFUNC("e1000_release_software_semaphore");
8351
8352	if (hw->mac_type != e1000_80003es2lan) {
8353	return;
8354	}
8355
8356	swsm = E1000_READ_REG(hw, SWSM);
8357	/* Release the SW semaphores.*/
8358	swsm &= ~E1000_SWSM_SMBI;
8359	E1000_WRITE_REG(hw, SWSM, swsm);
8360	}
8361
8362	/******************************************************************************
8363	* Checks if PHY reset is blocked due to SOL/IDER session, for example.
8364	* Returning E1000_BLK_PHY_RESET isn't necessarily an error. But it's up to
8365	* the caller to figure out how to deal with it.
8366	*
8367	* hw - Struct containing variables accessed by shared code
8368	*
8369	* returns: - E1000_BLK_PHY_RESET
8370	* E1000_SUCCESS
8371	*
8372	*****************************************************************************/
8373	int32_t
8374	e1000_check_phy_reset_block(struct e1000_hw *hw)
8375	{
8376	uint32_t manc = 0;
8377	uint32_t fwsm = 0;
8378
8379	if (hw->mac_type == e1000_ich8lan) {
8380	fwsm = E1000_READ_REG(hw, FWSM);
8381	return (fwsm & E1000_FWSM_RSPCIPHY) ? E1000_SUCCESS
8382	: E1000_BLK_PHY_RESET;
8383	}
8384
8385	if (hw->mac_type > e1000_82547_rev_2)
8386	manc = E1000_READ_REG(hw, MANC);
8387	return (manc & E1000_MANC_BLK_PHY_RST_ON_IDE) ?
8388	E1000_BLK_PHY_RESET : E1000_SUCCESS;
8389	}
8390
8391	static uint8_t
8392	e1000_arc_subsystem_valid(struct e1000_hw *hw)
8393	{
8394	uint32_t fwsm;
8395
8396	/* On 8257x silicon, registers in the range of 0x8800 - 0x8FFC
8397	* may not be provided a DMA clock when no manageability features are
8398	* enabled. We do not want to perform any reads/writes to these registers
8399	* if this is the case. We read FWSM to determine the manageability mode.
8400	*/
8401	switch (hw->mac_type) {
8402	case e1000_82571:
8403	case e1000_82572:
8404	case e1000_82573:
8405	case e1000_80003es2lan:
8406	case e1000_82576:
8407	fwsm = E1000_READ_REG(hw, FWSM);
8408	if ((fwsm & E1000_FWSM_MODE_MASK) != 0)
8409	return TRUE;
8410	break;
8411	case e1000_ich8lan:
8412	return TRUE;
8413	default:
8414	break;
8415	}
8416	return FALSE;
8417	}
8418
8419
8420	/******************************************************************************
8421	* Configure PCI-Ex no-snoop
8422	*
8423	* hw - Struct containing variables accessed by shared code.
8424	* no_snoop - Bitmap of no-snoop events.
8425	*
8426	* returns: E1000_SUCCESS
8427	*
8428	*****************************************************************************/
8429	static int32_t
8430	e1000_set_pci_ex_no_snoop(struct e1000_hw *hw, uint32_t no_snoop)
8431	{
8432	uint32_t gcr_reg = 0;
8433
8434	DEBUGFUNC("e1000_set_pci_ex_no_snoop");
8435
8436	if (hw->bus_type == e1000_bus_type_unknown)
8437	e1000_get_bus_info(hw);
8438
8439	if (hw->bus_type != e1000_bus_type_pci_express)
8440	return E1000_SUCCESS;
8441
8442	if (no_snoop) {
8443	gcr_reg = E1000_READ_REG(hw, GCR);
8444	gcr_reg &= ~(PCI_EX_NO_SNOOP_ALL);
8445	gcr_reg \|= no_snoop;
8446	E1000_WRITE_REG(hw, GCR, gcr_reg);
8447	}
8448	if (hw->mac_type == e1000_ich8lan) {
8449	uint32_t ctrl_ext;
8450
8451	E1000_WRITE_REG(hw, GCR, PCI_EX_82566_SNOOP_ALL);
8452
8453	ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
8454	ctrl_ext \|= E1000_CTRL_EXT_RO_DIS;
8455	E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
8456	}
8457
8458	return E1000_SUCCESS;
8459	}
8460
8461	/***************************************************************************
8462	*
8463	* Get software semaphore FLAG bit (SWFLAG).
8464	* SWFLAG is used to synchronize the access to all shared resource between
8465	* SW, FW and HW.
8466	*
8467	* hw: Struct containing variables accessed by shared code
8468	*
8469	***************************************************************************/
8470	static int32_t
8471	e1000_get_software_flag(struct e1000_hw *hw)
8472	{
8473	int32_t timeout = PHY_CFG_TIMEOUT;
8474	uint32_t extcnf_ctrl;
8475
8476	DEBUGFUNC("e1000_get_software_flag");
8477
8478	if (hw->mac_type == e1000_ich8lan) {
8479	while (timeout) {
8480	extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8481	extcnf_ctrl \|= E1000_EXTCNF_CTRL_SWFLAG;
8482	E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8483
8484	extcnf_ctrl = E1000_READ_REG(hw, EXTCNF_CTRL);
8485	if (extcnf_ctrl & E1000_EXTCNF_CTRL_SWFLAG)
8486	break;
8487	mdelay(1);
8488	timeout--;
8489	}
8490
8491	if (!timeout) {
8492	DEBUGOUT("FW or HW locks the resource too long.\n");
8493	return -E1000_ERR_CONFIG;
8494	}
8495	}
8496
8497	return E1000_SUCCESS;
8498	}
8499
8500	/***************************************************************************
8501	*
8502	* Release software semaphore FLAG bit (SWFLAG).
8503	* SWFLAG is used to synchronize the access to all shared resource between
8504	* SW, FW and HW.
8505	*
8506	* hw: Struct containing variables accessed by shared code
8507	*
8508	***************************************************************************/
8509	static void
8510	e1000_release_software_flag(struct e1000_hw *hw)
8511	{
8512	uint32_t extcnf_ctrl;
8513
8514	DEBUGFUNC("e1000_release_software_flag");
8515
8516	if (hw->mac_type == e1000_ich8lan) {
8517	extcnf_ctrl= E1000_READ_REG(hw, EXTCNF_CTRL);
8518	extcnf_ctrl &= ~E1000_EXTCNF_CTRL_SWFLAG;
8519	E1000_WRITE_REG(hw, EXTCNF_CTRL, extcnf_ctrl);
8520	}
8521
8522	return;
8523	}
8524
8525	/******************************************************************************
8526	* Reads a 16 bit word or words from the EEPROM using the ICH8's flash access
8527	* register.
8528	*
8529	* hw - Struct containing variables accessed by shared code
8530	* offset - offset of word in the EEPROM to read
8531	* data - word read from the EEPROM
8532	* words - number of words to read
8533	*****************************************************************************/
8534	static int32_t
8535	e1000_read_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8536	uint16_t *data)
8537	{
8538	int32_t error = E1000_SUCCESS;
8539	uint32_t flash_bank = 0;
8540	uint32_t act_offset = 0;
8541	uint32_t bank_offset = 0;
8542	uint16_t word = 0;
8543	uint16_t i = 0;
8544
8545	/* We need to know which is the valid flash bank. In the event
8546	* that we didn't allocate eeprom_shadow_ram, we may not be
8547	* managing flash_bank. So it cannot be trusted and needs
8548	* to be updated with each read.
8549	*/
8550	/* Value of bit 22 corresponds to the flash bank we're on. */
8551	flash_bank = (E1000_READ_REG(hw, EECD) & E1000_EECD_SEC1VAL) ? 1 : 0;
8552
8553	/* Adjust offset appropriately if we're on bank 1 - adjust for word size */
8554	bank_offset = flash_bank * (hw->flash_bank_size * 2);
8555
8556	error = e1000_get_software_flag(hw);
8557	if (error != E1000_SUCCESS)
8558	return error;
8559
8560	for (i = 0; i < words; i++) {
8561	if (hw->eeprom_shadow_ram != NULL &&
8562	hw->eeprom_shadow_ram[offset+i].modified == TRUE) {
8563	data[i] = hw->eeprom_shadow_ram[offset+i].eeprom_word;
8564	} else {
8565	/* The NVM part needs a byte offset, hence * 2 */
8566	act_offset = bank_offset + ((offset + i) * 2);
8567	error = e1000_read_ich8_word(hw, act_offset, &word);
8568	if (error != E1000_SUCCESS)
8569	break;
8570	data[i] = word;
8571	}
8572	}
8573
8574	e1000_release_software_flag(hw);
8575
8576	return error;
8577	}
8578
8579	/******************************************************************************
8580	* Writes a 16 bit word or words to the EEPROM using the ICH8's flash access
8581	* register. Actually, writes are written to the shadow ram cache in the hw
8582	* structure hw->e1000_shadow_ram. e1000_commit_shadow_ram flushes this to
8583	* the NVM, which occurs when the NVM checksum is updated.
8584	*
8585	* hw - Struct containing variables accessed by shared code
8586	* offset - offset of word in the EEPROM to write
8587	* words - number of words to write
8588	* data - words to write to the EEPROM
8589	*****************************************************************************/
8590	static int32_t
8591	e1000_write_eeprom_ich8(struct e1000_hw *hw, uint16_t offset, uint16_t words,
8592	uint16_t *data)
8593	{
8594	uint32_t i = 0;
8595	int32_t error = E1000_SUCCESS;
8596
8597	error = e1000_get_software_flag(hw);
8598	if (error != E1000_SUCCESS)
8599	return error;
8600
8601	/* A driver can write to the NVM only if it has eeprom_shadow_ram
8602	* allocated. Subsequent reads to the modified words are read from
8603	* this cached structure as well. Writes will only go into this
8604	* cached structure unless it's followed by a call to
8605	* e1000_update_eeprom_checksum() where it will commit the changes
8606	* and clear the "modified" field.
8607	*/
8608	if (hw->eeprom_shadow_ram != NULL) {
8609	for (i = 0; i < words; i++) {
8610	if ((offset + i) < E1000_SHADOW_RAM_WORDS) {
8611	hw->eeprom_shadow_ram[offset+i].modified = TRUE;
8612	hw->eeprom_shadow_ram[offset+i].eeprom_word = data[i];
8613	} else {
8614	error = -E1000_ERR_EEPROM;
8615	break;
8616	}
8617	}
8618	} else {
8619	/* Drivers have the option to not allocate eeprom_shadow_ram as long
8620	* as they don't perform any NVM writes. An attempt in doing so
8621	* will result in this error.
8622	*/
8623	error = -E1000_ERR_EEPROM;
8624	}
8625
8626	e1000_release_software_flag(hw);
8627
8628	return error;
8629	}
8630
8631	/******************************************************************************
8632	* This function does initial flash setup so that a new read/write/erase cycle
8633	* can be started.
8634	*
8635	* hw - The pointer to the hw structure
8636	****************************************************************************/
8637	static int32_t
8638	e1000_ich8_cycle_init(struct e1000_hw *hw)
8639	{
8640	union ich8_hws_flash_status hsfsts;
8641	int32_t error = E1000_ERR_EEPROM;
8642	int32_t i = 0;
8643
8644	DEBUGFUNC("e1000_ich8_cycle_init");
8645
8646	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8647
8648	/* May be check the Flash Des Valid bit in Hw status */
8649	if (hsfsts.hsf_status.fldesvalid == 0) {
8650	DEBUGOUT("Flash descriptor invalid. SW Sequencing must be used.");
8651	return error;
8652	}
8653
8654	/* Clear FCERR in Hw status by writing 1 */
8655	/* Clear DAEL in Hw status by writing a 1 */
8656	hsfsts.hsf_status.flcerr = 1;
8657	hsfsts.hsf_status.dael = 1;
8658
8659	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8660
8661	/* Either we should have a hardware SPI cycle in progress bit to check
8662	* against, in order to start a new cycle or FDONE bit should be changed
8663	* in the hardware so that it is 1 after harware reset, which can then be
8664	* used as an indication whether a cycle is in progress or has been
8665	* completed .. we should also have some software semaphore mechanism to
8666	* guard FDONE or the cycle in progress bit so that two threads access to
8667	* those bits can be sequentiallized or a way so that 2 threads dont
8668	* start the cycle at the same time */
8669
8670	if (hsfsts.hsf_status.flcinprog == 0) {
8671	/* There is no cycle running at present, so we can start a cycle */
8672	/* Begin by setting Flash Cycle Done. */
8673	hsfsts.hsf_status.flcdone = 1;
8674	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8675	error = E1000_SUCCESS;
8676	} else {
8677	/* otherwise poll for sometime so the current cycle has a chance
8678	* to end before giving up. */
8679	for (i = 0; i < ICH_FLASH_COMMAND_TIMEOUT; i++) {
8680	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8681	if (hsfsts.hsf_status.flcinprog == 0) {
8682	error = E1000_SUCCESS;
8683	break;
8684	}
8685	udelay(1);
8686	}
8687	if (error == E1000_SUCCESS) {
8688	/* Successful in waiting for previous cycle to timeout,
8689	* now set the Flash Cycle Done. */
8690	hsfsts.hsf_status.flcdone = 1;
8691	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS, hsfsts.regval);
8692	} else {
8693	DEBUGOUT("Flash controller busy, cannot get access");
8694	}
8695	}
8696	return error;
8697	}
8698
8699	/******************************************************************************
8700	* This function starts a flash cycle and waits for its completion
8701	*
8702	* hw - The pointer to the hw structure
8703	****************************************************************************/
8704	static int32_t
8705	e1000_ich8_flash_cycle(struct e1000_hw *hw, uint32_t timeout)
8706	{
8707	union ich8_hws_flash_ctrl hsflctl;
8708	union ich8_hws_flash_status hsfsts;
8709	int32_t error = E1000_ERR_EEPROM;
8710	uint32_t i = 0;
8711
8712	/* Start a cycle by writing 1 in Flash Cycle Go in Hw Flash Control */
8713	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8714	hsflctl.hsf_ctrl.flcgo = 1;
8715	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8716
8717	/* wait till FDONE bit is set to 1 */
8718	do {
8719	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8720	if (hsfsts.hsf_status.flcdone == 1)
8721	break;
8722	udelay(1);
8723	i++;
8724	} while (i < timeout);
8725	if (hsfsts.hsf_status.flcdone == 1 && hsfsts.hsf_status.flcerr == 0) {
8726	error = E1000_SUCCESS;
8727	}
8728	return error;
8729	}
8730
8731	/******************************************************************************
8732	* Reads a byte or word from the NVM using the ICH8 flash access registers.
8733	*
8734	* hw - The pointer to the hw structure
8735	* index - The index of the byte or word to read.
8736	* size - Size of data to read, 1=byte 2=word
8737	* data - Pointer to the word to store the value read.
8738	*****************************************************************************/
8739	static int32_t
8740	e1000_read_ich8_data(struct e1000_hw *hw, uint32_t index,
8741	uint32_t size, uint16_t* data)
8742	{
8743	union ich8_hws_flash_status hsfsts;
8744	union ich8_hws_flash_ctrl hsflctl;
8745	uint32_t flash_linear_address;
8746	uint32_t flash_data = 0;
8747	int32_t error = -E1000_ERR_EEPROM;
8748	int32_t count = 0;
8749
8750	DEBUGFUNC("e1000_read_ich8_data");
8751
8752	if (size < 1 \|\| size > 2 \|\| data == 0x0 \|\|
8753	index > ICH_FLASH_LINEAR_ADDR_MASK)
8754	return error;
8755
8756	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8757	hw->flash_base_addr;
8758
8759	do {
8760	udelay(1);
8761	/* Steps */
8762	error = e1000_ich8_cycle_init(hw);
8763	if (error != E1000_SUCCESS)
8764	break;
8765
8766	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8767	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8768	hsflctl.hsf_ctrl.fldbcount = size - 1;
8769	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_READ;
8770	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8771
8772	/* Write the last 24 bits of index into Flash Linear address field in
8773	* Flash Address */
8774	/* TODO: TBD maybe check the index against the size of flash */
8775
8776	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8777
8778	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8779
8780	/* Check if FCERR is set to 1, if set to 1, clear it and try the whole
8781	* sequence a few more times, else read in (shift in) the Flash Data0,
8782	* the order is least significant byte first msb to lsb */
8783	if (error == E1000_SUCCESS) {
8784	flash_data = E1000_READ_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0);
8785	if (size == 1) {
8786	*data = (uint8_t)(flash_data & 0x000000FF);
8787	} else if (size == 2) {
8788	*data = (uint16_t)(flash_data & 0x0000FFFF);
8789	}
8790	break;
8791	} else {
8792	/* If we've gotten here, then things are probably completely hosed,
8793	* but if the error condition is detected, it won't hurt to give
8794	* it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8795	*/
8796	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8797	if (hsfsts.hsf_status.flcerr == 1) {
8798	/* Repeat for some time before giving up. */
8799	continue;
8800	} else if (hsfsts.hsf_status.flcdone == 0) {
8801	DEBUGOUT("Timeout error - flash cycle did not complete.");
8802	break;
8803	}
8804	}
8805	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8806
8807	return error;
8808	}
8809
8810	/******************************************************************************
8811	* Writes One /two bytes to the NVM using the ICH8 flash access registers.
8812	*
8813	* hw - The pointer to the hw structure
8814	* index - The index of the byte/word to read.
8815	* size - Size of data to read, 1=byte 2=word
8816	* data - The byte(s) to write to the NVM.
8817	*****************************************************************************/
8818	static int32_t
8819	e1000_write_ich8_data(struct e1000_hw *hw, uint32_t index, uint32_t size,
8820	uint16_t data)
8821	{
8822	union ich8_hws_flash_status hsfsts;
8823	union ich8_hws_flash_ctrl hsflctl;
8824	uint32_t flash_linear_address;
8825	uint32_t flash_data = 0;
8826	int32_t error = -E1000_ERR_EEPROM;
8827	int32_t count = 0;
8828
8829	DEBUGFUNC("e1000_write_ich8_data");
8830
8831	if (size < 1 \|\| size > 2 \|\| data > size * 0xff \|\|
8832	index > ICH_FLASH_LINEAR_ADDR_MASK)
8833	return error;
8834
8835	flash_linear_address = (ICH_FLASH_LINEAR_ADDR_MASK & index) +
8836	hw->flash_base_addr;
8837
8838	do {
8839	udelay(1);
8840	/* Steps */
8841	error = e1000_ich8_cycle_init(hw);
8842	if (error != E1000_SUCCESS)
8843	break;
8844
8845	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
8846	/* 0b/1b corresponds to 1 or 2 byte size, respectively. */
8847	hsflctl.hsf_ctrl.fldbcount = size -1;
8848	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_WRITE;
8849	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
8850
8851	/* Write the last 24 bits of index into Flash Linear address field in
8852	* Flash Address */
8853	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
8854
8855	if (size == 1)
8856	flash_data = (uint32_t)data & 0x00FF;
8857	else
8858	flash_data = (uint32_t)data;
8859
8860	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FDATA0, flash_data);
8861
8862	/* check if FCERR is set to 1 , if set to 1, clear it and try the whole
8863	* sequence a few more times else done */
8864	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_COMMAND_TIMEOUT);
8865	if (error == E1000_SUCCESS) {
8866	break;
8867	} else {
8868	/* If we're here, then things are most likely completely hosed,
8869	* but if the error condition is detected, it won't hurt to give
8870	* it another try...ICH_FLASH_CYCLE_REPEAT_COUNT times.
8871	*/
8872	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
8873	if (hsfsts.hsf_status.flcerr == 1) {
8874	/* Repeat for some time before giving up. */
8875	continue;
8876	} else if (hsfsts.hsf_status.flcdone == 0) {
8877	DEBUGOUT("Timeout error - flash cycle did not complete.");
8878	break;
8879	}
8880	}
8881	} while (count++ < ICH_FLASH_CYCLE_REPEAT_COUNT);
8882
8883	return error;
8884	}
8885
8886	/******************************************************************************
8887	* Reads a single byte from the NVM using the ICH8 flash access registers.
8888	*
8889	* hw - pointer to e1000_hw structure
8890	* index - The index of the byte to read.
8891	* data - Pointer to a byte to store the value read.
8892	*****************************************************************************/
8893	static int32_t
8894	e1000_read_ich8_byte(struct e1000_hw hw, uint32_t index, uint8_t data)
8895	{
8896	int32_t status = E1000_SUCCESS;
8897	uint16_t word = 0;
8898
8899	status = e1000_read_ich8_data(hw, index, 1, &word);
8900	if (status == E1000_SUCCESS) {
8901	*data = (uint8_t)word;
8902	}
8903
8904	return status;
8905	}
8906
8907	/******************************************************************************
8908	* Writes a single byte to the NVM using the ICH8 flash access registers.
8909	* Performs verification by reading back the value and then going through
8910	* a retry algorithm before giving up.
8911	*
8912	* hw - pointer to e1000_hw structure
8913	* index - The index of the byte to write.
8914	* byte - The byte to write to the NVM.
8915	*****************************************************************************/
8916	static int32_t
8917	e1000_verify_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t byte)
8918	{
8919	int32_t error = E1000_SUCCESS;
8920	int32_t program_retries = 0;
8921
8922	DEBUGOUT2("Byte := %2.2X Offset := %d\n", byte, index);
8923
8924	error = e1000_write_ich8_byte(hw, index, byte);
8925
8926	if (error != E1000_SUCCESS) {
8927	for (program_retries = 0; program_retries < 100; program_retries++) {
8928	DEBUGOUT2("Retrying \t Byte := %2.2X Offset := %d\n", byte, index);
8929	error = e1000_write_ich8_byte(hw, index, byte);
8930	udelay(100);
8931	if (error == E1000_SUCCESS)
8932	break;
8933	}
8934	}
8935
8936	if (program_retries == 100)
8937	error = E1000_ERR_EEPROM;
8938
8939	return error;
8940	}
8941
8942	/******************************************************************************
8943	* Writes a single byte to the NVM using the ICH8 flash access registers.
8944	*
8945	* hw - pointer to e1000_hw structure
8946	* index - The index of the byte to read.
8947	* data - The byte to write to the NVM.
8948	*****************************************************************************/
8949	static int32_t
8950	e1000_write_ich8_byte(struct e1000_hw *hw, uint32_t index, uint8_t data)
8951	{
8952	int32_t status = E1000_SUCCESS;
8953	uint16_t word = (uint16_t)data;
8954
8955	status = e1000_write_ich8_data(hw, index, 1, word);
8956
8957	return status;
8958	}
8959
8960	/******************************************************************************
8961	* Reads a word from the NVM using the ICH8 flash access registers.
8962	*
8963	* hw - pointer to e1000_hw structure
8964	* index - The starting byte index of the word to read.
8965	* data - Pointer to a word to store the value read.
8966	*****************************************************************************/
8967	static int32_t
8968	e1000_read_ich8_word(struct e1000_hw hw, uint32_t index, uint16_t data)
8969	{
8970	int32_t status = E1000_SUCCESS;
8971	status = e1000_read_ich8_data(hw, index, 2, data);
8972	return status;
8973	}
8974
8975	/******************************************************************************
8976	* Erases the bank specified. Each bank may be a 4, 8 or 64k block. Banks are 0
8977	* based.
8978	*
8979	* hw - pointer to e1000_hw structure
8980	* bank - 0 for first bank, 1 for second bank
8981	*
8982	* Note that this function may actually erase as much as 8 or 64 KBytes. The
8983	* amount of NVM used in each bank is a minimum of 4 KBytes, but in fact the
8984	* bank size may be 4, 8 or 64 KBytes
8985	*****************************************************************************/
8986	int32_t
8987	e1000_erase_ich8_4k_segment(struct e1000_hw *hw, uint32_t bank)
8988	{
8989	union ich8_hws_flash_status hsfsts;
8990	union ich8_hws_flash_ctrl hsflctl;
8991	uint32_t flash_linear_address;
8992	int32_t count = 0;
8993	int32_t error = E1000_ERR_EEPROM;
8994	int32_t iteration;
8995	int32_t sub_sector_size = 0;
8996	int32_t bank_size;
8997	int32_t j = 0;
8998	int32_t error_flag = 0;
8999
9000	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9001
9002	/* Determine HW Sector size: Read BERASE bits of Hw flash Status register */
9003	/* 00: The Hw sector is 256 bytes, hence we need to erase 16
9004	* consecutive sectors. The start index for the nth Hw sector can be
9005	* calculated as bank * 4096 + n * 256
9006	* 01: The Hw sector is 4K bytes, hence we need to erase 1 sector.
9007	* The start index for the nth Hw sector can be calculated
9008	* as bank * 4096
9009	* 10: The HW sector is 8K bytes
9010	* 11: The Hw sector size is 64K bytes */
9011	if (hsfsts.hsf_status.berasesz == 0x0) {
9012	/* Hw sector size 256 */
9013	sub_sector_size = ICH_FLASH_SEG_SIZE_256;
9014	bank_size = ICH_FLASH_SECTOR_SIZE;
9015	iteration = ICH_FLASH_SECTOR_SIZE / ICH_FLASH_SEG_SIZE_256;
9016	} else if (hsfsts.hsf_status.berasesz == 0x1) {
9017	bank_size = ICH_FLASH_SEG_SIZE_4K;
9018	iteration = 1;
9019	} else if (hsfsts.hsf_status.berasesz == 0x3) {
9020	bank_size = ICH_FLASH_SEG_SIZE_64K;
9021	iteration = 1;
9022	} else {
9023	return error;
9024	}
9025
9026	for (j = 0; j < iteration ; j++) {
9027	do {
9028	count++;
9029	/* Steps */
9030	error = e1000_ich8_cycle_init(hw);
9031	if (error != E1000_SUCCESS) {
9032	error_flag = 1;
9033	break;
9034	}
9035
9036	/* Write a value 11 (block Erase) in Flash Cycle field in Hw flash
9037	* Control */
9038	hsflctl.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL);
9039	hsflctl.hsf_ctrl.flcycle = ICH_CYCLE_ERASE;
9040	E1000_WRITE_ICH_FLASH_REG16(hw, ICH_FLASH_HSFCTL, hsflctl.regval);
9041
9042	/* Write the last 24 bits of an index within the block into Flash
9043	* Linear address field in Flash Address. This probably needs to
9044	* be calculated here based off the on-chip erase sector size and
9045	* the software bank size (4, 8 or 64 KBytes) */
9046	flash_linear_address = bank * bank_size + j * sub_sector_size;
9047	flash_linear_address += hw->flash_base_addr;
9048	flash_linear_address &= ICH_FLASH_LINEAR_ADDR_MASK;
9049
9050	E1000_WRITE_ICH_FLASH_REG(hw, ICH_FLASH_FADDR, flash_linear_address);
9051
9052	error = e1000_ich8_flash_cycle(hw, ICH_FLASH_ERASE_TIMEOUT);
9053	/* Check if FCERR is set to 1. If 1, clear it and try the whole
9054	* sequence a few more times else Done */
9055	if (error == E1000_SUCCESS) {
9056	break;
9057	} else {
9058	hsfsts.regval = E1000_READ_ICH_FLASH_REG16(hw, ICH_FLASH_HSFSTS);
9059	if (hsfsts.hsf_status.flcerr == 1) {
9060	/* repeat for some time before giving up */
9061	continue;
9062	} else if (hsfsts.hsf_status.flcdone == 0) {
9063	error_flag = 1;
9064	break;
9065	}
9066	}
9067	} while ((count < ICH_FLASH_CYCLE_REPEAT_COUNT) && !error_flag);
9068	if (error_flag == 1)
9069	break;
9070	}
9071	if (error_flag != 1)
9072	error = E1000_SUCCESS;
9073	return error;
9074	}
9075
9076	static int32_t
9077	e1000_init_lcd_from_nvm_config_region(struct e1000_hw *hw,
9078	uint32_t cnf_base_addr, uint32_t cnf_size)
9079	{
9080	uint32_t ret_val = E1000_SUCCESS;
9081	uint16_t word_addr, reg_data, reg_addr;
9082	uint16_t i;
9083
9084	/* cnf_base_addr is in DWORD */
9085	word_addr = (uint16_t)(cnf_base_addr << 1);
9086
9087	/* cnf_size is returned in size of dwords */
9088	for (i = 0; i < cnf_size; i++) {
9089	ret_val = e1000_read_eeprom(hw, (word_addr + i*2), 1, &reg_data);
9090	if (ret_val)
9091	return ret_val;
9092
9093	ret_val = e1000_read_eeprom(hw, (word_addr + i*2 + 1), 1, &reg_addr);
9094	if (ret_val)
9095	return ret_val;
9096
9097	ret_val = e1000_get_software_flag(hw);
9098	if (ret_val != E1000_SUCCESS)
9099	return ret_val;
9100
9101	ret_val = e1000_write_phy_reg_ex(hw, (uint32_t)reg_addr, reg_data);
9102
9103	e1000_release_software_flag(hw);
9104	}
9105
9106	return ret_val;
9107	}
9108
9109
9110	/******************************************************************************
9111	* This function initializes the PHY from the NVM on ICH8 platforms. This
9112	* is needed due to an issue where the NVM configuration is not properly
9113	* autoloaded after power transitions. Therefore, after each PHY reset, we
9114	* will load the configuration data out of the NVM manually.
9115	*
9116	* hw: Struct containing variables accessed by shared code
9117	*****************************************************************************/
9118	static int32_t
9119	e1000_init_lcd_from_nvm(struct e1000_hw *hw)
9120	{
9121	uint32_t reg_data, cnf_base_addr, cnf_size, ret_val, loop;
9122
9123	if (hw->phy_type != e1000_phy_igp_3)
9124	return E1000_SUCCESS;
9125
9126	/* Check if SW needs configure the PHY */
9127	reg_data = E1000_READ_REG(hw, FEXTNVM);
9128	if (!(reg_data & FEXTNVM_SW_CONFIG))
9129	return E1000_SUCCESS;
9130
9131	/* Wait for basic configuration completes before proceeding*/
9132	loop = 0;
9133	do {
9134	reg_data = E1000_READ_REG(hw, STATUS) & E1000_STATUS_LAN_INIT_DONE;
9135	udelay(100);
9136	loop++;
9137	} while ((!reg_data) && (loop < 50));
9138
9139	/* Clear the Init Done bit for the next init event */
9140	reg_data = E1000_READ_REG(hw, STATUS);
9141	reg_data &= ~E1000_STATUS_LAN_INIT_DONE;
9142	E1000_WRITE_REG(hw, STATUS, reg_data);
9143
9144	/* Make sure HW does not configure LCD from PHY extended configuration
9145	before SW configuration */
9146	reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9147	if ((reg_data & E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE) == 0x0000) {
9148	reg_data = E1000_READ_REG(hw, EXTCNF_SIZE);
9149	cnf_size = reg_data & E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH;
9150	cnf_size >>= 16;
9151	if (cnf_size) {
9152	reg_data = E1000_READ_REG(hw, EXTCNF_CTRL);
9153	cnf_base_addr = reg_data & E1000_EXTCNF_CTRL_EXT_CNF_POINTER;
9154	/* cnf_base_addr is in DWORD */
9155	cnf_base_addr >>= 16;
9156
9157	/* Configure LCD from extended configuration region. */
9158	ret_val = e1000_init_lcd_from_nvm_config_region(hw, cnf_base_addr,
9159	cnf_size);
9160	if (ret_val)
9161	return ret_val;
9162	}
9163	}
9164
9165	return E1000_SUCCESS;
9166	}
9167
9168	/*
9169	* Local variables:
9170	* c-basic-offset: 8
9171	* c-indent-level: 8
9172	* tab-width: 8
9173	* End:
9174	*/

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