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source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/forcedeth.c

Last change on this file was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago
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1	/**************************************************************************
2	* forcedeth.c -- Etherboot device driver for the NVIDIA nForce
3	* media access controllers.
4	*
5	* Note: This driver is based on the Linux driver that was based on
6	* a cleanroom reimplementation which was based on reverse
7	* engineered documentation written by Carl-Daniel Hailfinger
8	* and Andrew de Quincey. It's neither supported nor endorsed
9	* by NVIDIA Corp. Use at your own risk.
10	*
11	* Written 2004 by Timothy Legge <tlegge@rogers.com>
12	*
13	* This program is free software; you can redistribute it and/or modify
14	* it under the terms of the GNU General Public License as published by
15	* the Free Software Foundation; either version 2 of the License, or
16	* (at your option) any later version.
17	*
18	* This program is distributed in the hope that it will be useful,
19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21	* GNU General Public License for more details.
22	*
23	* You should have received a copy of the GNU General Public License
24	* along with this program; if not, write to the Free Software
25	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
26	*
27	* Portions of this code based on:
28	* forcedeth: Ethernet driver for NVIDIA nForce media access controllers:
29	*
30	* (C) 2003 Manfred Spraul
31	* See Linux Driver for full information
32	*
33	* Linux Driver Version 0.30, 25 Sep 2004
34	* Linux Kernel 2.6.10
35	*
36	*
37	* REVISION HISTORY:
38	* ================
39	* v1.0 01-31-2004 timlegge Initial port of Linux driver
40	* v1.1 02-03-2004 timlegge Large Clean up, first release
41	* v1.2 05-14-2005 timlegge Add Linux 0.22 to .030 features
42	*
43	* Indent Options: indent -kr -i8
44	***************************************************************************/
45
46	FILE_LICENCE ( GPL2_OR_LATER );
47
48	/* to get some global routines like printf */
49	#include "etherboot.h"
50	/* to get the interface to the body of the program */
51	#include "nic.h"
52	/* to get the PCI support functions, if this is a PCI NIC */
53	#include <gpxe/pci.h>
54	/* Include timer support functions */
55	#include <gpxe/ethernet.h>
56	#include "mii.h"
57
58	#define drv_version "v1.2"
59	#define drv_date "05-14-2005"
60
61	//#define TFTM_DEBUG
62	#ifdef TFTM_DEBUG
63	#define dprintf(x) printf x
64	#else
65	#define dprintf(x)
66	#endif
67
68	#define ETH_DATA_LEN 1500
69
70	/* Condensed operations for readability. */
71	#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
72	#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
73
74	static unsigned long BASE;
75	/* NIC specific static variables go here */
76	#define PCI_DEVICE_ID_NVIDIA_NVENET_1 0x01c3
77	#define PCI_DEVICE_ID_NVIDIA_NVENET_2 0x0066
78	#define PCI_DEVICE_ID_NVIDIA_NVENET_4 0x0086
79	#define PCI_DEVICE_ID_NVIDIA_NVENET_5 0x008c
80	#define PCI_DEVICE_ID_NVIDIA_NVENET_3 0x00d6
81	#define PCI_DEVICE_ID_NVIDIA_NVENET_7 0x00df
82	#define PCI_DEVICE_ID_NVIDIA_NVENET_6 0x00e6
83	#define PCI_DEVICE_ID_NVIDIA_NVENET_8 0x0056
84	#define PCI_DEVICE_ID_NVIDIA_NVENET_9 0x0057
85	#define PCI_DEVICE_ID_NVIDIA_NVENET_10 0x0037
86	#define PCI_DEVICE_ID_NVIDIA_NVENET_11 0x0038
87	#define PCI_DEVICE_ID_NVIDIA_NVENET_15 0x0373
88
89
90	/*
91	* Hardware access:
92	*/
93
94	#define DEV_NEED_LASTPACKET1 0x0001 /* set LASTPACKET1 in tx flags */
95	#define DEV_IRQMASK_1 0x0002 /* use NVREG_IRQMASK_WANTED_1 for irq mask */
96	#define DEV_IRQMASK_2 0x0004 /* use NVREG_IRQMASK_WANTED_2 for irq mask */
97	#define DEV_NEED_TIMERIRQ 0x0008 /* set the timer irq flag in the irq mask */
98	#define DEV_NEED_LINKTIMER 0x0010 /* poll link settings. Relies on the timer irq */
99
100	enum {
101	NvRegIrqStatus = 0x000,
102	#define NVREG_IRQSTAT_MIIEVENT 0040
103	#define NVREG_IRQSTAT_MASK 0x1ff
104	NvRegIrqMask = 0x004,
105	#define NVREG_IRQ_RX_ERROR 0x0001
106	#define NVREG_IRQ_RX 0x0002
107	#define NVREG_IRQ_RX_NOBUF 0x0004
108	#define NVREG_IRQ_TX_ERR 0x0008
109	#define NVREG_IRQ_TX2 0x0010
110	#define NVREG_IRQ_TIMER 0x0020
111	#define NVREG_IRQ_LINK 0x0040
112	#define NVREG_IRQ_TX1 0x0100
113	#define NVREG_IRQMASK_WANTED_1 0x005f
114	#define NVREG_IRQMASK_WANTED_2 0x0147
115	#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR\|NVREG_IRQ_RX\|NVREG_IRQ_RX_NOBUF\|NVREG_IRQ_TX_ERR\|NVREG_IRQ_TX2\|NVREG_IRQ_TIMER\|NVREG_IRQ_LINK\|NVREG_IRQ_TX1))
116
117	NvRegUnknownSetupReg6 = 0x008,
118	#define NVREG_UNKSETUP6_VAL 3
119
120	/*
121	* NVREG_POLL_DEFAULT is the interval length of the timer source on the nic
122	* NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms
123	*/
124	NvRegPollingInterval = 0x00c,
125	#define NVREG_POLL_DEFAULT 970
126	NvRegMisc1 = 0x080,
127	#define NVREG_MISC1_HD 0x02
128	#define NVREG_MISC1_FORCE 0x3b0f3c
129
130	NvRegTransmitterControl = 0x084,
131	#define NVREG_XMITCTL_START 0x01
132	NvRegTransmitterStatus = 0x088,
133	#define NVREG_XMITSTAT_BUSY 0x01
134
135	NvRegPacketFilterFlags = 0x8c,
136	#define NVREG_PFF_ALWAYS 0x7F0008
137	#define NVREG_PFF_PROMISC 0x80
138	#define NVREG_PFF_MYADDR 0x20
139
140	NvRegOffloadConfig = 0x90,
141	#define NVREG_OFFLOAD_HOMEPHY 0x601
142	#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE
143	NvRegReceiverControl = 0x094,
144	#define NVREG_RCVCTL_START 0x01
145	NvRegReceiverStatus = 0x98,
146	#define NVREG_RCVSTAT_BUSY 0x01
147
148	NvRegRandomSeed = 0x9c,
149	#define NVREG_RNDSEED_MASK 0x00ff
150	#define NVREG_RNDSEED_FORCE 0x7f00
151	#define NVREG_RNDSEED_FORCE2 0x2d00
152	#define NVREG_RNDSEED_FORCE3 0x7400
153
154	NvRegUnknownSetupReg1 = 0xA0,
155	#define NVREG_UNKSETUP1_VAL 0x16070f
156	NvRegUnknownSetupReg2 = 0xA4,
157	#define NVREG_UNKSETUP2_VAL 0x16
158	NvRegMacAddrA = 0xA8,
159	NvRegMacAddrB = 0xAC,
160	NvRegMulticastAddrA = 0xB0,
161	#define NVREG_MCASTADDRA_FORCE 0x01
162	NvRegMulticastAddrB = 0xB4,
163	NvRegMulticastMaskA = 0xB8,
164	NvRegMulticastMaskB = 0xBC,
165
166	NvRegPhyInterface = 0xC0,
167	#define PHY_RGMII 0x10000000
168
169	NvRegTxRingPhysAddr = 0x100,
170	NvRegRxRingPhysAddr = 0x104,
171	NvRegRingSizes = 0x108,
172	#define NVREG_RINGSZ_TXSHIFT 0
173	#define NVREG_RINGSZ_RXSHIFT 16
174	NvRegUnknownTransmitterReg = 0x10c,
175	NvRegLinkSpeed = 0x110,
176	#define NVREG_LINKSPEED_FORCE 0x10000
177	#define NVREG_LINKSPEED_10 1000
178	#define NVREG_LINKSPEED_100 100
179	#define NVREG_LINKSPEED_1000 50
180	NvRegUnknownSetupReg5 = 0x130,
181	#define NVREG_UNKSETUP5_BIT31 (1<<31)
182	NvRegUnknownSetupReg3 = 0x13c,
183	#define NVREG_UNKSETUP3_VAL1 0x200010
184	NvRegTxRxControl = 0x144,
185	#define NVREG_TXRXCTL_KICK 0x0001
186	#define NVREG_TXRXCTL_BIT1 0x0002
187	#define NVREG_TXRXCTL_BIT2 0x0004
188	#define NVREG_TXRXCTL_IDLE 0x0008
189	#define NVREG_TXRXCTL_RESET 0x0010
190	#define NVREG_TXRXCTL_RXCHECK 0x0400
191	NvRegMIIStatus = 0x180,
192	#define NVREG_MIISTAT_ERROR 0x0001
193	#define NVREG_MIISTAT_LINKCHANGE 0x0008
194	#define NVREG_MIISTAT_MASK 0x000f
195	#define NVREG_MIISTAT_MASK2 0x000f
196	NvRegUnknownSetupReg4 = 0x184,
197	#define NVREG_UNKSETUP4_VAL 8
198
199	NvRegAdapterControl = 0x188,
200	#define NVREG_ADAPTCTL_START 0x02
201	#define NVREG_ADAPTCTL_LINKUP 0x04
202	#define NVREG_ADAPTCTL_PHYVALID 0x40000
203	#define NVREG_ADAPTCTL_RUNNING 0x100000
204	#define NVREG_ADAPTCTL_PHYSHIFT 24
205	NvRegMIISpeed = 0x18c,
206	#define NVREG_MIISPEED_BIT8 (1<<8)
207	#define NVREG_MIIDELAY 5
208	NvRegMIIControl = 0x190,
209	#define NVREG_MIICTL_INUSE 0x08000
210	#define NVREG_MIICTL_WRITE 0x00400
211	#define NVREG_MIICTL_ADDRSHIFT 5
212	NvRegMIIData = 0x194,
213	NvRegWakeUpFlags = 0x200,
214	#define NVREG_WAKEUPFLAGS_VAL 0x7770
215	#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24
216	#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16
217	#define NVREG_WAKEUPFLAGS_D3SHIFT 12
218	#define NVREG_WAKEUPFLAGS_D2SHIFT 8
219	#define NVREG_WAKEUPFLAGS_D1SHIFT 4
220	#define NVREG_WAKEUPFLAGS_D0SHIFT 0
221	#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01
222	#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02
223	#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04
224	#define NVREG_WAKEUPFLAGS_ENABLE 0x1111
225
226	NvRegPatternCRC = 0x204,
227	NvRegPatternMask = 0x208,
228	NvRegPowerCap = 0x268,
229	#define NVREG_POWERCAP_D3SUPP (1<<30)
230	#define NVREG_POWERCAP_D2SUPP (1<<26)
231	#define NVREG_POWERCAP_D1SUPP (1<<25)
232	NvRegPowerState = 0x26c,
233	#define NVREG_POWERSTATE_POWEREDUP 0x8000
234	#define NVREG_POWERSTATE_VALID 0x0100
235	#define NVREG_POWERSTATE_MASK 0x0003
236	#define NVREG_POWERSTATE_D0 0x0000
237	#define NVREG_POWERSTATE_D1 0x0001
238	#define NVREG_POWERSTATE_D2 0x0002
239	#define NVREG_POWERSTATE_D3 0x0003
240	};
241
242	#define FLAG_MASK_V1 0xffff0000
243	#define FLAG_MASK_V2 0xffffc000
244	#define LEN_MASK_V1 (0xffffffff ^ FLAG_MASK_V1)
245	#define LEN_MASK_V2 (0xffffffff ^ FLAG_MASK_V2)
246
247	#define NV_TX_LASTPACKET (1<<16)
248	#define NV_TX_RETRYERROR (1<<19)
249	#define NV_TX_LASTPACKET1 (1<<24)
250	#define NV_TX_DEFERRED (1<<26)
251	#define NV_TX_CARRIERLOST (1<<27)
252	#define NV_TX_LATECOLLISION (1<<28)
253	#define NV_TX_UNDERFLOW (1<<29)
254	#define NV_TX_ERROR (1<<30)
255	#define NV_TX_VALID (1<<31)
256
257	#define NV_TX2_LASTPACKET (1<<29)
258	#define NV_TX2_RETRYERROR (1<<18)
259	#define NV_TX2_LASTPACKET1 (1<<23)
260	#define NV_TX2_DEFERRED (1<<25)
261	#define NV_TX2_CARRIERLOST (1<<26)
262	#define NV_TX2_LATECOLLISION (1<<27)
263	#define NV_TX2_UNDERFLOW (1<<28)
264	/* error and valid are the same for both */
265	#define NV_TX2_ERROR (1<<30)
266	#define NV_TX2_VALID (1<<31)
267
268	#define NV_RX_DESCRIPTORVALID (1<<16)
269	#define NV_RX_MISSEDFRAME (1<<17)
270	#define NV_RX_SUBSTRACT1 (1<<18)
271	#define NV_RX_ERROR1 (1<<23)
272	#define NV_RX_ERROR2 (1<<24)
273	#define NV_RX_ERROR3 (1<<25)
274	#define NV_RX_ERROR4 (1<<26)
275	#define NV_RX_CRCERR (1<<27)
276	#define NV_RX_OVERFLOW (1<<28)
277	#define NV_RX_FRAMINGERR (1<<29)
278	#define NV_RX_ERROR (1<<30)
279	#define NV_RX_AVAIL (1<<31)
280
281	#define NV_RX2_CHECKSUMMASK (0x1C000000)
282	#define NV_RX2_CHECKSUMOK1 (0x10000000)
283	#define NV_RX2_CHECKSUMOK2 (0x14000000)
284	#define NV_RX2_CHECKSUMOK3 (0x18000000)
285	#define NV_RX2_DESCRIPTORVALID (1<<29)
286	#define NV_RX2_SUBSTRACT1 (1<<25)
287	#define NV_RX2_ERROR1 (1<<18)
288	#define NV_RX2_ERROR2 (1<<19)
289	#define NV_RX2_ERROR3 (1<<20)
290	#define NV_RX2_ERROR4 (1<<21)
291	#define NV_RX2_CRCERR (1<<22)
292	#define NV_RX2_OVERFLOW (1<<23)
293	#define NV_RX2_FRAMINGERR (1<<24)
294	/* error and avail are the same for both */
295	#define NV_RX2_ERROR (1<<30)
296	#define NV_RX2_AVAIL (1<<31)
297
298	/* Miscelaneous hardware related defines: */
299	#define NV_PCI_REGSZ 0x270
300
301	/* various timeout delays: all in usec */
302	#define NV_TXRX_RESET_DELAY 4
303	#define NV_TXSTOP_DELAY1 10
304	#define NV_TXSTOP_DELAY1MAX 500000
305	#define NV_TXSTOP_DELAY2 100
306	#define NV_RXSTOP_DELAY1 10
307	#define NV_RXSTOP_DELAY1MAX 500000
308	#define NV_RXSTOP_DELAY2 100
309	#define NV_SETUP5_DELAY 5
310	#define NV_SETUP5_DELAYMAX 50000
311	#define NV_POWERUP_DELAY 5
312	#define NV_POWERUP_DELAYMAX 5000
313	#define NV_MIIBUSY_DELAY 50
314	#define NV_MIIPHY_DELAY 10
315	#define NV_MIIPHY_DELAYMAX 10000
316
317	#define NV_WAKEUPPATTERNS 5
318	#define NV_WAKEUPMASKENTRIES 4
319
320	/* General driver defaults */
321	#define NV_WATCHDOG_TIMEO (5*HZ)
322
323	#define RX_RING 4
324	#define TX_RING 2
325
326	/*
327	* If your nic mysteriously hangs then try to reduce the limits
328	* to 1/0: It might be required to set NV_TX_LASTPACKET in the
329	* last valid ring entry. But this would be impossible to
330	* implement - probably a disassembly error.
331	*/
332	#define TX_LIMIT_STOP 63
333	#define TX_LIMIT_START 62
334
335	/* rx/tx mac addr + type + vlan + align + slack*/
336	#define RX_NIC_BUFSIZE (ETH_DATA_LEN + 64)
337	/* even more slack */
338	#define RX_ALLOC_BUFSIZE (ETH_DATA_LEN + 128)
339
340	#define OOM_REFILL (1+HZ/20)
341	#define POLL_WAIT (1+HZ/100)
342	#define LINK_TIMEOUT (3*HZ)
343
344	/*
345	* desc_ver values:
346	* This field has two purposes:
347	* - Newer nics uses a different ring layout. The layout is selected by
348	* comparing np->desc_ver with DESC_VER_xy.
349	* - It contains bits that are forced on when writing to NvRegTxRxControl.
350	*/
351	#define DESC_VER_1 0x0
352	#define DESC_VER_2 (0x02100\|NVREG_TXRXCTL_RXCHECK)
353
354	/* PHY defines */
355	#define PHY_OUI_MARVELL 0x5043
356	#define PHY_OUI_CICADA 0x03f1
357	#define PHYID1_OUI_MASK 0x03ff
358	#define PHYID1_OUI_SHFT 6
359	#define PHYID2_OUI_MASK 0xfc00
360	#define PHYID2_OUI_SHFT 10
361	#define PHY_INIT1 0x0f000
362	#define PHY_INIT2 0x0e00
363	#define PHY_INIT3 0x01000
364	#define PHY_INIT4 0x0200
365	#define PHY_INIT5 0x0004
366	#define PHY_INIT6 0x02000
367	#define PHY_GIGABIT 0x0100
368
369	#define PHY_TIMEOUT 0x1
370	#define PHY_ERROR 0x2
371
372	#define PHY_100 0x1
373	#define PHY_1000 0x2
374	#define PHY_HALF 0x100
375
376
377	/* Bit to know if MAC addr is stored in correct order */
378	#define MAC_ADDR_CORRECT 0x01
379
380	/* Big endian: should work, but is untested */
381	struct ring_desc {
382	u32 PacketBuffer;
383	u32 FlagLen;
384	};
385
386
387	/* Define the TX and RX Descriptor and Buffers */
388	struct {
389	struct ring_desc tx_ring[TX_RING];
390	unsigned char txb[TX_RING * RX_NIC_BUFSIZE];
391	struct ring_desc rx_ring[RX_RING];
392	unsigned char rxb[RX_RING * RX_NIC_BUFSIZE];
393	} forcedeth_bufs __shared;
394	#define tx_ring forcedeth_bufs.tx_ring
395	#define rx_ring forcedeth_bufs.rx_ring
396	#define txb forcedeth_bufs.txb
397	#define rxb forcedeth_bufs.rxb
398
399	/* Private Storage for the NIC */
400	static struct forcedeth_private {
401	/* General data:
402	* Locking: spin_lock(&np->lock); */
403	int in_shutdown;
404	u32 linkspeed;
405	int duplex;
406	int phyaddr;
407	int wolenabled;
408	unsigned int phy_oui;
409	u16 gigabit;
410
411	/* General data: RO fields */
412	u8 *ring_addr;
413	u32 orig_mac[2];
414	u32 irqmask;
415	u32 desc_ver;
416	/* rx specific fields.
417	* Locking: Within irq hander or disable_irq+spin_lock(&np->lock);
418	*/
419	unsigned int cur_rx, refill_rx;
420
421	/*
422	* tx specific fields.
423	*/
424	unsigned int next_tx, nic_tx;
425	u32 tx_flags;
426	} npx;
427
428	static struct forcedeth_private *np;
429
430	static inline void pci_push(u8 * base)
431	{
432	/* force out pending posted writes */
433	readl(base);
434	}
435
436	static inline u32 nv_descr_getlength(struct ring_desc *prd, u32 v)
437	{
438	return le32_to_cpu(prd->FlagLen)
439	& ((v == DESC_VER_1) ? LEN_MASK_V1 : LEN_MASK_V2);
440	}
441
442	static int reg_delay(int offset, u32 mask,
443	u32 target, int delay, int delaymax, const char *msg)
444	{
445	u8 base = (u8 ) BASE;
446
447	pci_push(base);
448	do {
449	udelay(delay);
450	delaymax -= delay;
451	if (delaymax < 0) {
452	if (msg)
453	printf("%s", msg);
454	return 1;
455	}
456	} while ((readl(base + offset) & mask) != target);
457	return 0;
458	}
459
460	#define MII_READ (-1)
461
462	/* mii_rw: read/write a register on the PHY.
463	*
464	* Caller must guarantee serialization
465	*/
466	static int mii_rw(struct nic *nic __unused, int addr, int miireg,
467	int value)
468	{
469	u8 base = (u8 ) BASE;
470	u32 reg;
471	int retval;
472
473	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
474
475	reg = readl(base + NvRegMIIControl);
476	if (reg & NVREG_MIICTL_INUSE) {
477	writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl);
478	udelay(NV_MIIBUSY_DELAY);
479	}
480
481	reg =
482	(addr << NVREG_MIICTL_ADDRSHIFT) \| miireg;
483	if (value != MII_READ) {
484	writel(value, base + NvRegMIIData);
485	reg \|= NVREG_MIICTL_WRITE;
486	}
487	writel(reg, base + NvRegMIIControl);
488
489	if (reg_delay(NvRegMIIControl, NVREG_MIICTL_INUSE, 0,
490	NV_MIIPHY_DELAY, NV_MIIPHY_DELAYMAX, NULL)) {
491	dprintf(("mii_rw of reg %d at PHY %d timed out.\n",
492	miireg, addr));
493	retval = -1;
494	} else if (value != MII_READ) {
495	/* it was a write operation - fewer failures are detectable */
496	dprintf(("mii_rw wrote 0x%x to reg %d at PHY %d\n",
497	value, miireg, addr));
498	retval = 0;
499	} else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) {
500	dprintf(("mii_rw of reg %d at PHY %d failed.\n",
501	miireg, addr));
502	retval = -1;
503	} else {
504	retval = readl(base + NvRegMIIData);
505	dprintf(("mii_rw read from reg %d at PHY %d: 0x%x.\n",
506	miireg, addr, retval));
507	}
508	return retval;
509	}
510
511	static int phy_reset(struct nic *nic)
512	{
513
514	u32 miicontrol;
515	unsigned int tries = 0;
516
517	miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
518	miicontrol \|= BMCR_RESET;
519	if (mii_rw(nic, np->phyaddr, MII_BMCR, miicontrol)) {
520	return -1;
521	}
522
523	/* wait for 500ms */
524	mdelay(500);
525
526	/* must wait till reset is deasserted */
527	while (miicontrol & BMCR_RESET) {
528	mdelay(10);
529	miicontrol = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
530	/* FIXME: 100 tries seem excessive */
531	if (tries++ > 100)
532	return -1;
533	}
534	return 0;
535	}
536
537	static int phy_init(struct nic *nic)
538	{
539	u8 base = (u8 ) BASE;
540	u32 phyinterface, phy_reserved, mii_status, mii_control,
541	mii_control_1000, reg;
542
543	/* set advertise register */
544	reg = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
545	reg \|=
546	(ADVERTISE_10HALF \| ADVERTISE_10FULL \| ADVERTISE_100HALF \|
547	ADVERTISE_100FULL \| 0x800 \| 0x400);
548	if (mii_rw(nic, np->phyaddr, MII_ADVERTISE, reg)) {
549	printf("phy write to advertise failed.\n");
550	return PHY_ERROR;
551	}
552
553	/* get phy interface type */
554	phyinterface = readl(base + NvRegPhyInterface);
555
556	/* see if gigabit phy */
557	mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
558
559	if (mii_status & PHY_GIGABIT) {
560	np->gigabit = PHY_GIGABIT;
561	mii_control_1000 =
562	mii_rw(nic, np->phyaddr, MII_CTRL1000, MII_READ);
563	mii_control_1000 &= ~ADVERTISE_1000HALF;
564	if (phyinterface & PHY_RGMII)
565	mii_control_1000 \|= ADVERTISE_1000FULL;
566	else
567	mii_control_1000 &= ~ADVERTISE_1000FULL;
568
569	if (mii_rw
570	(nic, np->phyaddr, MII_CTRL1000, mii_control_1000)) {
571	printf("phy init failed.\n");
572	return PHY_ERROR;
573	}
574	} else
575	np->gigabit = 0;
576
577	/* reset the phy */
578	if (phy_reset(nic)) {
579	printf("phy reset failed\n");
580	return PHY_ERROR;
581	}
582
583	/* phy vendor specific configuration */
584	if ((np->phy_oui == PHY_OUI_CICADA) && (phyinterface & PHY_RGMII)) {
585	phy_reserved =
586	mii_rw(nic, np->phyaddr, MII_RESV1, MII_READ);
587	phy_reserved &= ~(PHY_INIT1 \| PHY_INIT2);
588	phy_reserved \|= (PHY_INIT3 \| PHY_INIT4);
589	if (mii_rw(nic, np->phyaddr, MII_RESV1, phy_reserved)) {
590	printf("phy init failed.\n");
591	return PHY_ERROR;
592	}
593	phy_reserved =
594	mii_rw(nic, np->phyaddr, MII_NCONFIG, MII_READ);
595	phy_reserved \|= PHY_INIT5;
596	if (mii_rw(nic, np->phyaddr, MII_NCONFIG, phy_reserved)) {
597	printf("phy init failed.\n");
598	return PHY_ERROR;
599	}
600	}
601	if (np->phy_oui == PHY_OUI_CICADA) {
602	phy_reserved =
603	mii_rw(nic, np->phyaddr, MII_SREVISION, MII_READ);
604	phy_reserved \|= PHY_INIT6;
605	if (mii_rw(nic, np->phyaddr, MII_SREVISION, phy_reserved)) {
606	printf("phy init failed.\n");
607	return PHY_ERROR;
608	}
609	}
610
611	/* restart auto negotiation */
612	mii_control = mii_rw(nic, np->phyaddr, MII_BMCR, MII_READ);
613	mii_control \|= (BMCR_ANRESTART \| BMCR_ANENABLE);
614	if (mii_rw(nic, np->phyaddr, MII_BMCR, mii_control)) {
615	return PHY_ERROR;
616	}
617
618	return 0;
619	}
620
621	static void start_rx(struct nic *nic __unused)
622	{
623	u8 base = (u8 ) BASE;
624
625	dprintf(("start_rx\n"));
626	/* Already running? Stop it. */
627	if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) {
628	writel(0, base + NvRegReceiverControl);
629	pci_push(base);
630	}
631	writel(np->linkspeed, base + NvRegLinkSpeed);
632	pci_push(base);
633	writel(NVREG_RCVCTL_START, base + NvRegReceiverControl);
634	pci_push(base);
635	}
636
637	static void stop_rx(void)
638	{
639	u8 base = (u8 ) BASE;
640
641	dprintf(("stop_rx\n"));
642	writel(0, base + NvRegReceiverControl);
643	reg_delay(NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0,
644	NV_RXSTOP_DELAY1, NV_RXSTOP_DELAY1MAX,
645	"stop_rx: ReceiverStatus remained busy");
646
647	udelay(NV_RXSTOP_DELAY2);
648	writel(0, base + NvRegLinkSpeed);
649	}
650
651	static void start_tx(struct nic *nic __unused)
652	{
653	u8 base = (u8 ) BASE;
654
655	dprintf(("start_tx\n"));
656	writel(NVREG_XMITCTL_START, base + NvRegTransmitterControl);
657	pci_push(base);
658	}
659
660	static void stop_tx(void)
661	{
662	u8 base = (u8 ) BASE;
663
664	dprintf(("stop_tx\n"));
665	writel(0, base + NvRegTransmitterControl);
666	reg_delay(NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0,
667	NV_TXSTOP_DELAY1, NV_TXSTOP_DELAY1MAX,
668	"stop_tx: TransmitterStatus remained busy");
669
670	udelay(NV_TXSTOP_DELAY2);
671	writel(0, base + NvRegUnknownTransmitterReg);
672	}
673
674
675	static void txrx_reset(struct nic *nic __unused)
676	{
677	u8 base = (u8 ) BASE;
678
679	dprintf(("txrx_reset\n"));
680	writel(NVREG_TXRXCTL_BIT2 \| NVREG_TXRXCTL_RESET \| np->desc_ver,
681	base + NvRegTxRxControl);
682
683	pci_push(base);
684	udelay(NV_TXRX_RESET_DELAY);
685	writel(NVREG_TXRXCTL_BIT2 \| np->desc_ver, base + NvRegTxRxControl);
686	pci_push(base);
687	}
688
689	/*
690	* alloc_rx: fill rx ring entries.
691	* Return 1 if the allocations for the skbs failed and the
692	* rx engine is without Available descriptors
693	*/
694	static int alloc_rx(struct nic *nic __unused)
695	{
696	unsigned int refill_rx = np->refill_rx;
697	int i;
698	//while (np->cur_rx != refill_rx) {
699	for (i = 0; i < RX_RING; i++) {
700	//int nr = refill_rx % RX_RING;
701	rx_ring[i].PacketBuffer =
702	virt_to_le32desc(&rxb[i * RX_NIC_BUFSIZE]);
703	wmb();
704	rx_ring[i].FlagLen =
705	cpu_to_le32(RX_NIC_BUFSIZE \| NV_RX_AVAIL);
706	/* printf("alloc_rx: Packet %d marked as Available\n",
707	refill_rx); */
708	refill_rx++;
709	}
710	np->refill_rx = refill_rx;
711	if (np->cur_rx - refill_rx == RX_RING)
712	return 1;
713	return 0;
714	}
715
716	static int update_linkspeed(struct nic *nic)
717	{
718	int adv, lpa;
719	u32 newls;
720	int newdup = np->duplex;
721	u32 mii_status;
722	int retval = 0;
723	u32 control_1000, status_1000, phyreg;
724	u8 base = (u8 ) BASE;
725	int i;
726
727	/* BMSR_LSTATUS is latched, read it twice:
728	* we want the current value.
729	*/
730	mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
731	mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
732
733	#if 1
734	//yhlu
735	for(i=0;i<30;i++) {
736	mii_status = mii_rw(nic, np->phyaddr, MII_BMSR, MII_READ);
737	if((mii_status & BMSR_LSTATUS) && (mii_status & BMSR_ANEGCOMPLETE)) break;
738	mdelay(100);
739	}
740	#endif
741
742	if (!(mii_status & BMSR_LSTATUS)) {
743	printf
744	("no link detected by phy - falling back to 10HD.\n");
745	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
746	newdup = 0;
747	retval = 0;
748	goto set_speed;
749	}
750
751	/* check auto negotiation is complete */
752	if (!(mii_status & BMSR_ANEGCOMPLETE)) {
753	/* still in autonegotiation - configure nic for 10 MBit HD and wait. */
754	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
755	newdup = 0;
756	retval = 0;
757	printf("autoneg not completed - falling back to 10HD.\n");
758	goto set_speed;
759	}
760
761	retval = 1;
762	if (np->gigabit == PHY_GIGABIT) {
763	control_1000 =
764	mii_rw(nic, np->phyaddr, MII_CTRL1000, MII_READ);
765	status_1000 =
766	mii_rw(nic, np->phyaddr, MII_STAT1000, MII_READ);
767
768	if ((control_1000 & ADVERTISE_1000FULL) &&
769	(status_1000 & LPA_1000FULL)) {
770	printf
771	("update_linkspeed: GBit ethernet detected.\n");
772	newls =
773	NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_1000;
774	newdup = 1;
775	goto set_speed;
776	}
777	}
778
779	adv = mii_rw(nic, np->phyaddr, MII_ADVERTISE, MII_READ);
780	lpa = mii_rw(nic, np->phyaddr, MII_LPA, MII_READ);
781	dprintf(("update_linkspeed: PHY advertises 0x%hX, lpa 0x%hX.\n",
782	adv, lpa));
783
784	/* FIXME: handle parallel detection properly, handle gigabit ethernet */
785	lpa = lpa & adv;
786	if (lpa & LPA_100FULL) {
787	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_100;
788	newdup = 1;
789	} else if (lpa & LPA_100HALF) {
790	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_100;
791	newdup = 0;
792	} else if (lpa & LPA_10FULL) {
793	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
794	newdup = 1;
795	} else if (lpa & LPA_10HALF) {
796	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
797	newdup = 0;
798	} else {
799	printf("bad ability %hX - falling back to 10HD.\n", lpa);
800	newls = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
801	newdup = 0;
802	}
803
804	set_speed:
805	if (np->duplex == newdup && np->linkspeed == newls)
806	return retval;
807
808	dprintf(("changing link setting from %d/%s to %d/%s.\n",
809	np->linkspeed, np->duplex ? "Full-Duplex": "Half-Duplex", newls, newdup ? "Full-Duplex": "Half-Duplex"));
810
811	np->duplex = newdup;
812	np->linkspeed = newls;
813
814	if (np->gigabit == PHY_GIGABIT) {
815	phyreg = readl(base + NvRegRandomSeed);
816	phyreg &= ~(0x3FF00);
817	if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10)
818	phyreg \|= NVREG_RNDSEED_FORCE3;
819	else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
820	phyreg \|= NVREG_RNDSEED_FORCE2;
821	else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
822	phyreg \|= NVREG_RNDSEED_FORCE;
823	writel(phyreg, base + NvRegRandomSeed);
824	}
825
826	phyreg = readl(base + NvRegPhyInterface);
827	phyreg &= ~(PHY_HALF \| PHY_100 \| PHY_1000);
828	if (np->duplex == 0)
829	phyreg \|= PHY_HALF;
830	if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100)
831	phyreg \|= PHY_100;
832	else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000)
833	phyreg \|= PHY_1000;
834	writel(phyreg, base + NvRegPhyInterface);
835
836	writel(NVREG_MISC1_FORCE \| (np->duplex ? 0 : NVREG_MISC1_HD),
837	base + NvRegMisc1);
838	pci_push(base);
839	writel(np->linkspeed, base + NvRegLinkSpeed);
840	pci_push(base);
841
842	return retval;
843	}
844
845	#if 0 /* Not used */
846	static void nv_linkchange(struct nic *nic)
847	{
848	if (update_linkspeed(nic)) {
849	// if (netif_carrier_ok(nic)) {
850	stop_rx();
851	//= } else {
852	// netif_carrier_on(dev);
853	// printk(KERN_INFO "%s: link up.\n", dev->name);
854	// }
855	start_rx(nic);
856	} else {
857	// if (netif_carrier_ok(dev)) {
858	// netif_carrier_off(dev);
859	// printk(KERN_INFO "%s: link down.\n", dev->name);
860	stop_rx();
861	// }
862	}
863	}
864	#endif
865
866	static int init_ring(struct nic *nic)
867	{
868	int i;
869
870	np->next_tx = np->nic_tx = 0;
871	for (i = 0; i < TX_RING; i++)
872	tx_ring[i].FlagLen = 0;
873
874	np->cur_rx = 0;
875	np->refill_rx = 0;
876	for (i = 0; i < RX_RING; i++)
877	rx_ring[i].FlagLen = 0;
878	return alloc_rx(nic);
879	}
880
881	static void set_multicast(struct nic *nic)
882	{
883
884	u8 base = (u8 ) BASE;
885	u32 addr[2];
886	u32 mask[2];
887	u32 pff;
888	u32 alwaysOff[2];
889	u32 alwaysOn[2];
890
891	memset(addr, 0, sizeof(addr));
892	memset(mask, 0, sizeof(mask));
893
894	pff = NVREG_PFF_MYADDR;
895
896	alwaysOn[0] = alwaysOn[1] = alwaysOff[0] = alwaysOff[1] = 0;
897
898	addr[0] = alwaysOn[0];
899	addr[1] = alwaysOn[1];
900	mask[0] = alwaysOn[0] \| alwaysOff[0];
901	mask[1] = alwaysOn[1] \| alwaysOff[1];
902
903	addr[0] \|= NVREG_MCASTADDRA_FORCE;
904	pff \|= NVREG_PFF_ALWAYS;
905	stop_rx();
906	writel(addr[0], base + NvRegMulticastAddrA);
907	writel(addr[1], base + NvRegMulticastAddrB);
908	writel(mask[0], base + NvRegMulticastMaskA);
909	writel(mask[1], base + NvRegMulticastMaskB);
910	writel(pff, base + NvRegPacketFilterFlags);
911	start_rx(nic);
912	}
913
914	/**************************************************************************
915	RESET - Reset the NIC to prepare for use
916	***************************************************************************/
917	static int forcedeth_reset(struct nic *nic)
918	{
919	u8 base = (u8 ) BASE;
920	int ret, oom, i;
921	ret = 0;
922	dprintf(("forcedeth: open\n"));
923
924	/* 1) erase previous misconfiguration */
925	/* 4.1-1: stop adapter: ignored, 4.3 seems to be overkill */
926	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
927	writel(0, base + NvRegMulticastAddrB);
928	writel(0, base + NvRegMulticastMaskA);
929	writel(0, base + NvRegMulticastMaskB);
930	writel(0, base + NvRegPacketFilterFlags);
931
932	writel(0, base + NvRegTransmitterControl);
933	writel(0, base + NvRegReceiverControl);
934
935	writel(0, base + NvRegAdapterControl);
936
937	/* 2) initialize descriptor rings */
938	oom = init_ring(nic);
939
940	writel(0, base + NvRegLinkSpeed);
941	writel(0, base + NvRegUnknownTransmitterReg);
942	txrx_reset(nic);
943	writel(0, base + NvRegUnknownSetupReg6);
944
945	np->in_shutdown = 0;
946
947	/* 3) set mac address */
948	{
949	u32 mac[2];
950
951	mac[0] =
952	(nic->node_addr[0] << 0) + (nic->node_addr[1] << 8) +
953	(nic->node_addr[2] << 16) + (nic->node_addr[3] << 24);
954	mac[1] =
955	(nic->node_addr[4] << 0) + (nic->node_addr[5] << 8);
956
957	writel(mac[0], base + NvRegMacAddrA);
958	writel(mac[1], base + NvRegMacAddrB);
959	}
960
961	/* 4) give hw rings */
962	writel((u32) virt_to_le32desc(&rx_ring[0]),
963	base + NvRegRxRingPhysAddr);
964	writel((u32) virt_to_le32desc(&tx_ring[0]),
965	base + NvRegTxRingPhysAddr);
966
967	writel(((RX_RING - 1) << NVREG_RINGSZ_RXSHIFT) +
968	((TX_RING - 1) << NVREG_RINGSZ_TXSHIFT),
969	base + NvRegRingSizes);
970
971	/* 5) continue setup */
972	np->linkspeed = NVREG_LINKSPEED_FORCE \| NVREG_LINKSPEED_10;
973	np->duplex = 0;
974	writel(np->linkspeed, base + NvRegLinkSpeed);
975	writel(NVREG_UNKSETUP3_VAL1, base + NvRegUnknownSetupReg3);
976	writel(np->desc_ver, base + NvRegTxRxControl);
977	pci_push(base);
978	writel(NVREG_TXRXCTL_BIT1 \| np->desc_ver, base + NvRegTxRxControl);
979	reg_delay(NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31,
980	NVREG_UNKSETUP5_BIT31, NV_SETUP5_DELAY,
981	NV_SETUP5_DELAYMAX,
982	"open: SetupReg5, Bit 31 remained off\n");
983
984	writel(0, base + NvRegUnknownSetupReg4);
985	// writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
986	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
987	#if 0
988	printf("%d-Mbs Link, %s-Duplex\n",
989	np->linkspeed & NVREG_LINKSPEED_10 ? 10 : 100,
990	np->duplex ? "Full" : "Half");
991	#endif
992
993	/* 6) continue setup */
994	writel(NVREG_MISC1_FORCE \| NVREG_MISC1_HD, base + NvRegMisc1);
995	writel(readl(base + NvRegTransmitterStatus),
996	base + NvRegTransmitterStatus);
997	writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags);
998	writel(NVREG_OFFLOAD_NORMAL, base + NvRegOffloadConfig);
999
1000	writel(readl(base + NvRegReceiverStatus),
1001	base + NvRegReceiverStatus);
1002
1003	/* Get a random number */
1004	i = random();
1005	writel(NVREG_RNDSEED_FORCE \| (i & NVREG_RNDSEED_MASK),
1006	base + NvRegRandomSeed);
1007	writel(NVREG_UNKSETUP1_VAL, base + NvRegUnknownSetupReg1);
1008	writel(NVREG_UNKSETUP2_VAL, base + NvRegUnknownSetupReg2);
1009	writel(NVREG_POLL_DEFAULT, base + NvRegPollingInterval);
1010	writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6);
1011	writel((np->
1012	phyaddr << NVREG_ADAPTCTL_PHYSHIFT) \|
1013	NVREG_ADAPTCTL_PHYVALID \| NVREG_ADAPTCTL_RUNNING,
1014	base + NvRegAdapterControl);
1015	writel(NVREG_MIISPEED_BIT8 \| NVREG_MIIDELAY, base + NvRegMIISpeed);
1016	writel(NVREG_UNKSETUP4_VAL, base + NvRegUnknownSetupReg4);
1017	writel(NVREG_WAKEUPFLAGS_VAL, base + NvRegWakeUpFlags);
1018
1019	i = readl(base + NvRegPowerState);
1020	if ((i & NVREG_POWERSTATE_POWEREDUP) == 0)
1021	writel(NVREG_POWERSTATE_POWEREDUP \| i,
1022	base + NvRegPowerState);
1023
1024	pci_push(base);
1025	udelay(10);
1026	writel(readl(base + NvRegPowerState) \| NVREG_POWERSTATE_VALID,
1027	base + NvRegPowerState);
1028
1029	writel(0, base + NvRegIrqMask);
1030	pci_push(base);
1031	writel(NVREG_MIISTAT_MASK2, base + NvRegMIIStatus);
1032	writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus);
1033	pci_push(base);
1034	/*
1035	writel(np->irqmask, base + NvRegIrqMask);
1036	*/
1037	writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA);
1038	writel(0, base + NvRegMulticastAddrB);
1039	writel(0, base + NvRegMulticastMaskA);
1040	writel(0, base + NvRegMulticastMaskB);
1041	writel(NVREG_PFF_ALWAYS \| NVREG_PFF_MYADDR,
1042	base + NvRegPacketFilterFlags);
1043
1044	set_multicast(nic);
1045	/* One manual link speed update: Interrupts are enabled, future link
1046	* speed changes cause interrupts and are handled by nv_link_irq().
1047	*/
1048	{
1049	u32 miistat;
1050	miistat = readl(base + NvRegMIIStatus);
1051	writel(NVREG_MIISTAT_MASK, base + NvRegMIIStatus);
1052	dprintf(("startup: got 0x%hX.\n", miistat));
1053	}
1054	ret = update_linkspeed(nic);
1055
1056	//start_rx(nic);
1057	start_tx(nic);
1058
1059	if (ret) {
1060	//Start Connection netif_carrier_on(dev);
1061	} else {
1062	printf("no link during initialization.\n");
1063	}
1064
1065	return ret;
1066	}
1067
1068	/*
1069	* extern void hex_dump(const char *data, const unsigned int len);
1070	*/
1071	/**************************************************************************
1072	POLL - Wait for a frame
1073	***************************************************************************/
1074	static int forcedeth_poll(struct nic *nic, int retrieve)
1075	{
1076	/* return true if there's an ethernet packet ready to read */
1077	/* nic->packet should contain data on return */
1078	/* nic->packetlen should contain length of data */
1079
1080	int len;
1081	int i;
1082	u32 Flags;
1083
1084	i = np->cur_rx % RX_RING;
1085
1086	Flags = le32_to_cpu(rx_ring[i].FlagLen);
1087	len = nv_descr_getlength(&rx_ring[i], np->desc_ver);
1088
1089	if (Flags & NV_RX_AVAIL)
1090	return 0; /* still owned by hardware, */
1091
1092	if (np->desc_ver == DESC_VER_1) {
1093	if (!(Flags & NV_RX_DESCRIPTORVALID))
1094	return 0;
1095	} else {
1096	if (!(Flags & NV_RX2_DESCRIPTORVALID))
1097	return 0;
1098	}
1099
1100	if (!retrieve)
1101	return 1;
1102
1103	/* got a valid packet - forward it to the network core */
1104	nic->packetlen = len;
1105	memcpy(nic->packet, rxb + (i * RX_NIC_BUFSIZE), nic->packetlen);
1106	/*
1107	* hex_dump(rxb + (i * RX_NIC_BUFSIZE), len);
1108	*/
1109	wmb();
1110	np->cur_rx++;
1111	alloc_rx(nic);
1112	return 1;
1113	}
1114
1115
1116	/**************************************************************************
1117	TRANSMIT - Transmit a frame
1118	***************************************************************************/
1119	static void forcedeth_transmit(struct nic nic, const char d, /* Destination */
1120	unsigned int t, /* Type */
1121	unsigned int s, /* size */
1122	const char *p)
1123	{ /* Packet */
1124	/* send the packet to destination */
1125	u8 *ptxb;
1126	u16 nstype;
1127	u8 base = (u8 ) BASE;
1128	int nr = np->next_tx % TX_RING;
1129
1130	/* point to the current txb incase multiple tx_rings are used */
1131	ptxb = txb + (nr * RX_NIC_BUFSIZE);
1132	//np->tx_skbuff[nr] = ptxb;
1133
1134	/* copy the packet to ring buffer */
1135	memcpy(ptxb, d, ETH_ALEN); /* dst */
1136	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
1137	nstype = htons((u16) t); /* type */
1138	memcpy(ptxb + 2 * ETH_ALEN, (u8 ) & nstype, 2); / type */
1139	memcpy(ptxb + ETH_HLEN, p, s);
1140
1141	s += ETH_HLEN;
1142	while (s < ETH_ZLEN) /* pad to min length */
1143	ptxb[s++] = '\0';
1144
1145	tx_ring[nr].PacketBuffer = (u32) virt_to_le32desc(ptxb);
1146
1147	wmb();
1148	tx_ring[nr].FlagLen = cpu_to_le32((s - 1) \| np->tx_flags);
1149
1150	writel(NVREG_TXRXCTL_KICK \| np->desc_ver, base + NvRegTxRxControl);
1151	pci_push(base);
1152	np->next_tx++;
1153	}
1154
1155	/**************************************************************************
1156	DISABLE - Turn off ethernet interface
1157	***************************************************************************/
1158	static void forcedeth_disable ( struct nic *nic __unused ) {
1159	/* put the card in its initial state */
1160	/* This function serves 3 purposes.
1161	* This disables DMA and interrupts so we don't receive
1162	* unexpected packets or interrupts from the card after
1163	* etherboot has finished.
1164	* This frees resources so etherboot may use
1165	* this driver on another interface
1166	* This allows etherboot to reinitialize the interface
1167	* if something is something goes wrong.
1168	*/
1169	u8 base = (u8 ) BASE;
1170	np->in_shutdown = 1;
1171	stop_tx();
1172	stop_rx();
1173
1174	/* disable interrupts on the nic or we will lock up */
1175	writel(0, base + NvRegIrqMask);
1176	pci_push(base);
1177	dprintf(("Irqmask is zero again\n"));
1178
1179	/* specia op:o write back the misordered MAC address - otherwise
1180	* the next probe_nic would see a wrong address.
1181	*/
1182	writel(np->orig_mac[0], base + NvRegMacAddrA);
1183	writel(np->orig_mac[1], base + NvRegMacAddrB);
1184	}
1185
1186	/**************************************************************************
1187	IRQ - Enable, Disable, or Force interrupts
1188	***************************************************************************/
1189	static void forcedeth_irq(struct nic *nic __unused,
1190	irq_action_t action __unused)
1191	{
1192	switch (action) {
1193	case DISABLE:
1194	break;
1195	case ENABLE:
1196	break;
1197	case FORCE:
1198	break;
1199	}
1200	}
1201
1202	static struct nic_operations forcedeth_operations = {
1203	.connect = dummy_connect,
1204	.poll = forcedeth_poll,
1205	.transmit = forcedeth_transmit,
1206	.irq = forcedeth_irq,
1207
1208	};
1209
1210	/**************************************************************************
1211	PROBE - Look for an adapter, this routine's visible to the outside
1212	***************************************************************************/
1213	#define IORESOURCE_MEM 0x00000200
1214	#define board_found 1
1215	#define valid_link 0
1216	static int forcedeth_probe ( struct nic nic, struct pci_device pci ) {
1217
1218	unsigned long addr;
1219	int sz;
1220	u8 *base;
1221	int i;
1222	struct pci_device_id *ids = pci->driver->ids;
1223	int id_count = pci->driver->id_count;
1224	unsigned int flags = 0;
1225
1226	if (pci->ioaddr == 0)
1227	return 0;
1228
1229	printf("forcedeth.c: Found %s, vendor=0x%hX, device=0x%hX\n",
1230	pci->driver_name, pci->vendor, pci->device);
1231
1232	nic->ioaddr = pci->ioaddr;
1233	nic->irqno = 0;
1234
1235	/* point to private storage */
1236	np = &npx;
1237
1238	adjust_pci_device(pci);
1239
1240	addr = pci_bar_start(pci, PCI_BASE_ADDRESS_0);
1241	sz = pci_bar_size(pci, PCI_BASE_ADDRESS_0);
1242
1243	/* BASE is used throughout to address the card */
1244	BASE = (unsigned long) ioremap(addr, sz);
1245	if (!BASE)
1246	return 0;
1247
1248	/* handle different descriptor versions */
1249	if (pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_1 \|\|
1250	pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_2 \|\|
1251	pci->device == PCI_DEVICE_ID_NVIDIA_NVENET_3)
1252	np->desc_ver = DESC_VER_1;
1253	else
1254	np->desc_ver = DESC_VER_2;
1255
1256	//rx_ring[0] = rx_ring;
1257	//tx_ring[0] = tx_ring;
1258
1259	/* read the mac address */
1260	base = (u8 *) BASE;
1261	np->orig_mac[0] = readl(base + NvRegMacAddrA);
1262	np->orig_mac[1] = readl(base + NvRegMacAddrB);
1263
1264	/* lookup the flags from pci_device_id */
1265	for(i = 0; i < id_count; i++) {
1266	if(pci->vendor == ids[i].vendor &&
1267	pci->device == ids[i].device) {
1268	flags = ids[i].driver_data;
1269	break;
1270	}
1271	}
1272
1273	/* read MAC address */
1274	if(flags & MAC_ADDR_CORRECT) {
1275	nic->node_addr[0] = (np->orig_mac[0] >> 0) & 0xff;
1276	nic->node_addr[1] = (np->orig_mac[0] >> 8) & 0xff;
1277	nic->node_addr[2] = (np->orig_mac[0] >> 16) & 0xff;
1278	nic->node_addr[3] = (np->orig_mac[0] >> 24) & 0xff;
1279	nic->node_addr[4] = (np->orig_mac[1] >> 0) & 0xff;
1280	nic->node_addr[5] = (np->orig_mac[1] >> 8) & 0xff;
1281	} else {
1282	nic->node_addr[0] = (np->orig_mac[1] >> 8) & 0xff;
1283	nic->node_addr[1] = (np->orig_mac[1] >> 0) & 0xff;
1284	nic->node_addr[2] = (np->orig_mac[0] >> 24) & 0xff;
1285	nic->node_addr[3] = (np->orig_mac[0] >> 16) & 0xff;
1286	nic->node_addr[4] = (np->orig_mac[0] >> 8) & 0xff;
1287	nic->node_addr[5] = (np->orig_mac[0] >> 0) & 0xff;
1288	}
1289	#ifdef LINUX
1290	if (!is_valid_ether_addr(dev->dev_addr)) {
1291	/*
1292	* Bad mac address. At least one bios sets the mac address
1293	* to 01:23:45:67:89:ab
1294	*/
1295	printk(KERN_ERR
1296	"%s: Invalid Mac address detected: %02x:%02x:%02x:%02x:%02x:%02x\n",
1297	pci_name(pci_dev), dev->dev_addr[0],
1298	dev->dev_addr[1], dev->dev_addr[2],
1299	dev->dev_addr[3], dev->dev_addr[4],
1300	dev->dev_addr[5]);
1301	printk(KERN_ERR
1302	"Please complain to your hardware vendor. Switching to a random MAC.\n");
1303	dev->dev_addr[0] = 0x00;
1304	dev->dev_addr[1] = 0x00;
1305	dev->dev_addr[2] = 0x6c;
1306	get_random_bytes(&dev->dev_addr[3], 3);
1307	}
1308	#endif
1309
1310	DBG ( "%s: MAC Address %s\n", pci->driver_name, eth_ntoa ( nic->node_addr ) );
1311
1312	/* disable WOL */
1313	writel(0, base + NvRegWakeUpFlags);
1314	np->wolenabled = 0;
1315
1316	if (np->desc_ver == DESC_VER_1) {
1317	np->tx_flags = NV_TX_LASTPACKET \| NV_TX_VALID;
1318	} else {
1319	np->tx_flags = NV_TX2_LASTPACKET \| NV_TX2_VALID;
1320	}
1321
1322	switch (pci->device) {
1323	case 0x01C3: // nforce
1324	case 0x054C:
1325	// DEV_IRQMASK_1\|DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER,
1326	np->irqmask = NVREG_IRQMASK_WANTED_2 \| NVREG_IRQ_TIMER;
1327	// np->need_linktimer = 1;
1328	// np->link_timeout = jiffies + LINK_TIMEOUT;
1329	break;
1330	case 0x0066:
1331	/* Fall Through */
1332	case 0x00D6:
1333	// DEV_NEED_LASTPACKET1\|DEV_IRQMASK_2\|DEV_NEED_TIMERIRQ\|DEV_NEED_LINKTIMER
1334	np->irqmask = NVREG_IRQMASK_WANTED_2;
1335	np->irqmask \|= NVREG_IRQ_TIMER;
1336	// np->need_linktimer = 1;
1337	// np->link_timeout = jiffies + LINK_TIMEOUT;
1338	if (np->desc_ver == DESC_VER_1)
1339	np->tx_flags \|= NV_TX_LASTPACKET1;
1340	else
1341	np->tx_flags \|= NV_TX2_LASTPACKET1;
1342	break;
1343	case 0x0373:
1344	/* Fall Through */
1345	case 0x0086:
1346	/* Fall Through */
1347	case 0x008c:
1348	/* Fall Through */
1349	case 0x00e6:
1350	/* Fall Through */
1351	case 0x00df:
1352	/* Fall Through */
1353	case 0x0056:
1354	/* Fall Through */
1355	case 0x0057:
1356	/* Fall Through */
1357	case 0x0037:
1358	/* Fall Through */
1359	case 0x0038:
1360	//DEV_NEED_LASTPACKET1\|DEV_IRQMASK_2\|DEV_NEED_TIMERIRQ
1361	np->irqmask = NVREG_IRQMASK_WANTED_2;
1362	np->irqmask \|= NVREG_IRQ_TIMER;
1363	// np->need_linktimer = 1;
1364	// np->link_timeout = jiffies + LINK_TIMEOUT;
1365	if (np->desc_ver == DESC_VER_1)
1366	np->tx_flags \|= NV_TX_LASTPACKET1;
1367	else
1368	np->tx_flags \|= NV_TX2_LASTPACKET1;
1369	break;
1370	default:
1371	printf
1372	("Your card was undefined in this driver. Review driver_data in Linux driver and send a patch\n");
1373	}
1374
1375	/* find a suitable phy */
1376	for (i = 1; i < 32; i++) {
1377	int id1, id2;
1378	id1 = mii_rw(nic, i, MII_PHYSID1, MII_READ);
1379	if (id1 < 0 \|\| id1 == 0xffff)
1380	continue;
1381	id2 = mii_rw(nic, i, MII_PHYSID2, MII_READ);
1382	if (id2 < 0 \|\| id2 == 0xffff)
1383	continue;
1384	id1 = (id1 & PHYID1_OUI_MASK) << PHYID1_OUI_SHFT;
1385	id2 = (id2 & PHYID2_OUI_MASK) >> PHYID2_OUI_SHFT;
1386	dprintf
1387	(("%s: open: Found PHY %hX:%hX at address %d.\n",
1388	pci->driver_name, id1, id2, i));
1389	np->phyaddr = i;
1390	np->phy_oui = id1 \| id2;
1391	break;
1392	}
1393	if (i == 32) {
1394	/* PHY in isolate mode? No phy attached and user wants to
1395	* test loopback? Very odd, but can be correct.
1396	*/
1397	printf
1398	("%s: open: Could not find a valid PHY.\n", pci->driver_name);
1399	}
1400
1401	if (i != 32) {
1402	/* reset it */
1403	phy_init(nic);
1404	}
1405
1406	dprintf(("%s: forcedeth.c: subsystem: %hX:%hX bound to %s\n",
1407	pci->driver_name, pci->vendor, pci->dev_id, pci->driver_name));
1408	if(!forcedeth_reset(nic)) return 0; // no valid link
1409
1410	/* point to NIC specific routines */
1411	nic->nic_op = &forcedeth_operations;
1412	return 1;
1413	}
1414
1415	static struct pci_device_id forcedeth_nics[] = {
1416	PCI_ROM(0x10de, 0x01C3, "nforce", "nForce NVENET_1 Ethernet Controller", 0),
1417	PCI_ROM(0x10de, 0x0066, "nforce2", "nForce NVENET_2 Ethernet Controller", 0),
1418	PCI_ROM(0x10de, 0x00D6, "nforce3", "nForce NVENET_3 Ethernet Controller", 0),
1419	PCI_ROM(0x10de, 0x0086, "nforce4", "nForce NVENET_4 Ethernet Controller", 0),
1420	PCI_ROM(0x10de, 0x008c, "nforce5", "nForce NVENET_5 Ethernet Controller", 0),
1421	PCI_ROM(0x10de, 0x00e6, "nforce6", "nForce NVENET_6 Ethernet Controller", 0),
1422	PCI_ROM(0x10de, 0x00df, "nforce7", "nForce NVENET_7 Ethernet Controller", 0),
1423	PCI_ROM(0x10de, 0x0056, "nforce8", "nForce NVENET_8 Ethernet Controller", 0),
1424	PCI_ROM(0x10de, 0x0057, "nforce9", "nForce NVENET_9 Ethernet Controller", 0),
1425	PCI_ROM(0x10de, 0x0037, "nforce10", "nForce NVENET_10 Ethernet Controller", 0),
1426	PCI_ROM(0x10de, 0x0038, "nforce11", "nForce NVENET_11 Ethernet Controller", 0),
1427	PCI_ROM(0x10de, 0x0373, "nforce15", "nForce NVENET_15 Ethernet Controller", 0),
1428	PCI_ROM(0x10de, 0x0269, "nforce16", "nForce NVENET_16 Ethernet Controller", 0),
1429	PCI_ROM(0x10de, 0x0760, "nforce17", "nForce NVENET_17 Ethernet Controller", MAC_ADDR_CORRECT),
1430	PCI_ROM(0x10de, 0x054c, "nforce67", "nForce NVENET_67 Ethernet Controller", MAC_ADDR_CORRECT),
1431	};
1432
1433	PCI_DRIVER ( forcedeth_driver, forcedeth_nics, PCI_NO_CLASS );
1434
1435	DRIVER ( "forcedeth", nic_driver, pci_driver, forcedeth_driver,
1436	forcedeth_probe, forcedeth_disable );
1437
1438	/*
1439	* Local variables:
1440	* c-basic-offset: 8
1441	* c-indent-level: 8
1442	* tab-width: 8
1443	* End:
1444	*/

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