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source: bootcd/isolinux/syslinux-6.03/gpxe/src/drivers/net/pcnet32.c @ e16e8f2

Last change on this file since e16e8f2 was e16e8f2, checked in by Edwin Eefting <edwin@datux.nl>, 3 years ago
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1	/**************************************************************************
2	*
3	* pcnet32.c -- Etherboot device driver for the AMD PCnet32
4	* Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
5	*
6	* This program is free software; you can redistribute it and/or modify
7	* it under the terms of the GNU General Public License as published by
8	* the Free Software Foundation; either version 2 of the License, or
9	* (at your option) any later version.
10	*
11	* This program is distributed in the hope that it will be useful,
12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14	* GNU General Public License for more details.
15	*
16	* You should have received a copy of the GNU General Public License
17	* along with this program; if not, write to the Free Software
18	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
19	*
20	* Portions of this code based on:
21	* pcnet32.c: An AMD PCnet32 ethernet driver for linux:
22	*
23	* (C) 1996-1999 Thomas Bogendoerfer
24	* See Linux Driver for full information
25	*
26	* The transmit and poll functions were written with reference to:
27	* lance.c - LANCE NIC driver for Etherboot written by Ken Yap
28	*
29	* Linux Driver Version 1.27a, 10.02.2002
30	*
31	*
32	* REVISION HISTORY:
33	* ================
34	* v1.0 08-06-2003 timlegge Initial port of Linux driver
35	* v1.1 08-23-2003 timlegge Add multicast support
36	* v1.2 01-17-2004 timlegge Initial driver output cleanup
37	* v1.3 03-29-2004 timlegge More driver cleanup
38	*
39	* Indent Options: indent -kr -i8
40	***************************************************************************/
41
42	FILE_LICENCE ( GPL2_OR_LATER );
43
44	#include "etherboot.h"
45	#include "nic.h"
46	#include <gpxe/pci.h>
47	#include <gpxe/ethernet.h>
48	#include "mii.h"
49
50	/* void hex_dump(const char data, const unsigned int len); /
51
52	/* Etherboot Specific definations */
53	#define drv_version "v1.3"
54	#define drv_date "03-29-2004"
55
56	static u32 ioaddr; /* Globally used for the card's io address */
57	static struct nic_operations pcnet32_operations;
58
59	#ifdef EDEBUG
60	#define dprintf(x) printf x
61	#else
62	#define dprintf(x)
63	#endif
64
65	/* Condensed operations for readability. */
66	#define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
67	#define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
68
69	/* End Etherboot Specific */
70
71	static int cards_found = 0 /* __initdata */ ;
72
73	#ifdef REMOVE
74	/* FIXME: Remove these they are probably pointless */
75
76	/*
77	* VLB I/O addresses
78	*/
79	static unsigned int pcnet32_portlist[] /__initdata / =
80	{ 0x300, 0x320, 0x340, 0x360, 0 };
81
82	static int pcnet32_debug = 1;
83	static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
84	static int pcnet32vlb; /* check for VLB cards ? */
85
86	static struct net_device *pcnet32_dev;
87
88	static int max_interrupt_work = 80;
89	static int rx_copybreak = 200;
90	#endif
91	#define PCNET32_PORT_AUI 0x00
92	#define PCNET32_PORT_10BT 0x01
93	#define PCNET32_PORT_GPSI 0x02
94	#define PCNET32_PORT_MII 0x03
95
96	#define PCNET32_PORT_PORTSEL 0x03
97	#define PCNET32_PORT_ASEL 0x04
98	#define PCNET32_PORT_100 0x40
99	#define PCNET32_PORT_FD 0x80
100
101	#define PCNET32_DMA_MASK 0xffffffff
102
103	/*
104	* table to translate option values from tulip
105	* to internal options
106	*/
107	static unsigned char options_mapping[] = {
108	PCNET32_PORT_ASEL, /* 0 Auto-select */
109	PCNET32_PORT_AUI, /* 1 BNC/AUI */
110	PCNET32_PORT_AUI, /* 2 AUI/BNC */
111	PCNET32_PORT_ASEL, /* 3 not supported */
112	PCNET32_PORT_10BT \| PCNET32_PORT_FD, /* 4 10baseT-FD */
113	PCNET32_PORT_ASEL, /* 5 not supported */
114	PCNET32_PORT_ASEL, /* 6 not supported */
115	PCNET32_PORT_ASEL, /* 7 not supported */
116	PCNET32_PORT_ASEL, /* 8 not supported */
117	PCNET32_PORT_MII, /* 9 MII 10baseT */
118	PCNET32_PORT_MII \| PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
119	PCNET32_PORT_MII, /* 11 MII (autosel) */
120	PCNET32_PORT_10BT, /* 12 10BaseT */
121	PCNET32_PORT_MII \| PCNET32_PORT_100, /* 13 MII 100BaseTx */
122	PCNET32_PORT_MII \| PCNET32_PORT_100 \| PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
123	PCNET32_PORT_ASEL /* 15 not supported */
124	};
125
126	#define MAX_UNITS 8 /* More are supported, limit only on options */
127	static int options[MAX_UNITS];
128	static int full_duplex[MAX_UNITS];
129
130	/*
131	* Theory of Operation
132	*
133	* This driver uses the same software structure as the normal lance
134	* driver. So look for a verbose description in lance.c. The differences
135	* to the normal lance driver is the use of the 32bit mode of PCnet32
136	* and PCnetPCI chips. Because these chips are 32bit chips, there is no
137	* 16MB limitation and we don't need bounce buffers.
138	*/
139
140
141
142	/*
143	* Set the number of Tx and Rx buffers, using Log_2(# buffers).
144	* Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
145	* That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
146	*/
147	#ifndef PCNET32_LOG_TX_BUFFERS
148	#define PCNET32_LOG_TX_BUFFERS 1
149	#define PCNET32_LOG_RX_BUFFERS 2
150	#endif
151
152	#define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
153	#define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
154	/* FIXME: Fix this to allow multiple tx_ring descriptors */
155	#define TX_RING_LEN_BITS 0x0000 /PCNET32_LOG_TX_BUFFERS) << 12) /
156
157	#define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
158	#define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
159	#define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
160
161	#define PKT_BUF_SZ 1544
162
163	/* Offsets from base I/O address. */
164	#define PCNET32_WIO_RDP 0x10
165	#define PCNET32_WIO_RAP 0x12
166	#define PCNET32_WIO_RESET 0x14
167	#define PCNET32_WIO_BDP 0x16
168
169	#define PCNET32_DWIO_RDP 0x10
170	#define PCNET32_DWIO_RAP 0x14
171	#define PCNET32_DWIO_RESET 0x18
172	#define PCNET32_DWIO_BDP 0x1C
173
174	#define PCNET32_TOTAL_SIZE 0x20
175
176	/* The PCNET32 Rx and Tx ring descriptors. */
177	struct pcnet32_rx_head {
178	u32 base;
179	s16 buf_length;
180	s16 status;
181	u32 msg_length;
182	u32 reserved;
183	};
184
185	struct pcnet32_tx_head {
186	u32 base;
187	s16 length;
188	s16 status;
189	u32 misc;
190	u32 reserved;
191	};
192
193	/* The PCNET32 32-Bit initialization block, described in databook. */
194	struct pcnet32_init_block {
195	u16 mode;
196	u16 tlen_rlen;
197	u8 phys_addr[6];
198	u16 reserved;
199	u32 filter[2];
200	/* Receive and transmit ring base, along with extra bits. */
201	u32 rx_ring;
202	u32 tx_ring;
203	};
204	/* PCnet32 access functions */
205	struct pcnet32_access {
206	u16(*read_csr) (unsigned long, int);
207	void (*write_csr) (unsigned long, int, u16);
208	u16(*read_bcr) (unsigned long, int);
209	void (*write_bcr) (unsigned long, int, u16);
210	u16(*read_rap) (unsigned long);
211	void (*write_rap) (unsigned long, u16);
212	void (*reset) (unsigned long);
213	};
214
215	/* Define the TX and RX Descriptors and Rings */
216	struct {
217	struct pcnet32_tx_head tx_ring[TX_RING_SIZE]
218	__attribute__ ((aligned(16)));
219	struct pcnet32_rx_head rx_ring[RX_RING_SIZE]
220	__attribute__ ((aligned(16)));
221	unsigned char txb[TX_RING_SIZE][PKT_BUF_SZ];
222	unsigned char rxb[RX_RING_SIZE][PKT_BUF_SZ];
223	} pcnet32_bufs __shared;
224
225
226	/*
227	* The first three fields of pcnet32_private are read by the ethernet device
228	* so we allocate the structure should be allocated by pci_alloc_consistent().
229	*/
230	#define MII_CNT 4
231	struct pcnet32_private {
232	struct pcnet32_init_block init_block;
233	struct pci_dev pci_dev; / Pointer to the associated pci device structure */
234	const char *name;
235	/* The saved address of a sent-in-place packet/buffer, for skfree(). */
236	struct sk_buff *tx_skbuff[TX_RING_SIZE];
237	struct sk_buff *rx_skbuff[RX_RING_SIZE];
238	struct pcnet32_access a;
239	unsigned int cur_rx, cur_tx; /* The next free ring entry */
240	char tx_full;
241	int options;
242	int shared_irq:1, /* shared irq possible */
243	ltint:1, /* enable TxDone-intr inhibitor */
244	dxsuflo:1, /* disable transmit stop on uflo */
245	mii:1; /* mii port available */
246	struct mii_if_info mii_if;
247	unsigned char phys[MII_CNT];
248	struct net_device *next;
249	int full_duplex:1;
250	} lpx;
251
252	static struct pcnet32_private *lp;
253
254	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num);
255	#if 0
256	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
257	int val);
258	#endif
259	enum pci_flags_bit {
260	PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
261	PCI_ADDR0 = 0x10 << 0, PCI_ADDR1 = 0x10 << 1, PCI_ADDR2 =
262	0x10 << 2, PCI_ADDR3 = 0x10 << 3,
263	};
264
265
266	static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
267	{
268	outw(index, addr + PCNET32_WIO_RAP);
269	return inw(addr + PCNET32_WIO_RDP);
270	}
271
272	static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
273	{
274	outw(index, addr + PCNET32_WIO_RAP);
275	outw(val, addr + PCNET32_WIO_RDP);
276	}
277
278	static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
279	{
280	outw(index, addr + PCNET32_WIO_RAP);
281	return inw(addr + PCNET32_WIO_BDP);
282	}
283
284	static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
285	{
286	outw(index, addr + PCNET32_WIO_RAP);
287	outw(val, addr + PCNET32_WIO_BDP);
288	}
289
290	static u16 pcnet32_wio_read_rap(unsigned long addr)
291	{
292	return inw(addr + PCNET32_WIO_RAP);
293	}
294
295	static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
296	{
297	outw(val, addr + PCNET32_WIO_RAP);
298	}
299
300	static void pcnet32_wio_reset(unsigned long addr)
301	{
302	inw(addr + PCNET32_WIO_RESET);
303	}
304
305	static int pcnet32_wio_check(unsigned long addr)
306	{
307	outw(88, addr + PCNET32_WIO_RAP);
308	return (inw(addr + PCNET32_WIO_RAP) == 88);
309	}
310
311	static struct pcnet32_access pcnet32_wio = {
312	read_csr:pcnet32_wio_read_csr,
313	write_csr:pcnet32_wio_write_csr,
314	read_bcr:pcnet32_wio_read_bcr,
315	write_bcr:pcnet32_wio_write_bcr,
316	read_rap:pcnet32_wio_read_rap,
317	write_rap:pcnet32_wio_write_rap,
318	reset:pcnet32_wio_reset
319	};
320
321	static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
322	{
323	outl(index, addr + PCNET32_DWIO_RAP);
324	return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
325	}
326
327	static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
328	{
329	outl(index, addr + PCNET32_DWIO_RAP);
330	outl(val, addr + PCNET32_DWIO_RDP);
331	}
332
333	static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
334	{
335	outl(index, addr + PCNET32_DWIO_RAP);
336	return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
337	}
338
339	static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
340	{
341	outl(index, addr + PCNET32_DWIO_RAP);
342	outl(val, addr + PCNET32_DWIO_BDP);
343	}
344
345	static u16 pcnet32_dwio_read_rap(unsigned long addr)
346	{
347	return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
348	}
349
350	static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
351	{
352	outl(val, addr + PCNET32_DWIO_RAP);
353	}
354
355	static void pcnet32_dwio_reset(unsigned long addr)
356	{
357	inl(addr + PCNET32_DWIO_RESET);
358	}
359
360	static int pcnet32_dwio_check(unsigned long addr)
361	{
362	outl(88, addr + PCNET32_DWIO_RAP);
363	return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
364	}
365
366	static struct pcnet32_access pcnet32_dwio = {
367	read_csr:pcnet32_dwio_read_csr,
368	write_csr:pcnet32_dwio_write_csr,
369	read_bcr:pcnet32_dwio_read_bcr,
370	write_bcr:pcnet32_dwio_write_bcr,
371	read_rap:pcnet32_dwio_read_rap,
372	write_rap:pcnet32_dwio_write_rap,
373	reset:pcnet32_dwio_reset
374	};
375
376
377	/* Initialize the PCNET32 Rx and Tx rings. */
378	static int pcnet32_init_ring(struct nic *nic)
379	{
380	int i;
381
382	lp->tx_full = 0;
383	lp->cur_rx = lp->cur_tx = 0;
384
385	for (i = 0; i < RX_RING_SIZE; i++) {
386	pcnet32_bufs.rx_ring[i].base =
387	virt_to_le32desc(&pcnet32_bufs.rxb[i]);
388	pcnet32_bufs.rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
389	pcnet32_bufs.rx_ring[i].status = le16_to_cpu(0x8000);
390	}
391
392	/* The Tx buffer address is filled in as needed, but we do need to clear
393	the upper ownership bit. */
394	for (i = 0; i < TX_RING_SIZE; i++) {
395	pcnet32_bufs.tx_ring[i].base = 0;
396	pcnet32_bufs.tx_ring[i].status = 0;
397	}
398
399
400	lp->init_block.tlen_rlen =
401	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
402	for (i = 0; i < 6; i++)
403	lp->init_block.phys_addr[i] = nic->node_addr[i];
404	lp->init_block.rx_ring = virt_to_le32desc(&pcnet32_bufs.rx_ring[0]);
405	lp->init_block.tx_ring = virt_to_le32desc(&pcnet32_bufs.tx_ring[0]);
406	return 0;
407	}
408
409	/**************************************************************************
410	RESET - Reset adapter
411	***************************************************************************/
412	static void pcnet32_reset(struct nic *nic)
413	{
414	/* put the card in its initial state */
415	u16 val;
416	int i;
417
418	/* Reset the PCNET32 */
419	lp->a.reset(ioaddr);
420
421	/* switch pcnet32 to 32bit mode */
422	lp->a.write_bcr(ioaddr, 20, 2);
423
424	/* set/reset autoselect bit */
425	val = lp->a.read_bcr(ioaddr, 2) & ~2;
426	if (lp->options & PCNET32_PORT_ASEL)
427	val \|= 2;
428	lp->a.write_bcr(ioaddr, 2, val);
429
430	/* handle full duplex setting */
431	if (lp->full_duplex) {
432	val = lp->a.read_bcr(ioaddr, 9) & ~3;
433	if (lp->options & PCNET32_PORT_FD) {
434	val \|= 1;
435	if (lp->options ==
436	(PCNET32_PORT_FD \| PCNET32_PORT_AUI))
437	val \|= 2;
438	} else if (lp->options & PCNET32_PORT_ASEL) {
439	/* workaround of xSeries250, turn on for 79C975 only */
440	i = ((lp->a.
441	read_csr(ioaddr,
442	88) \| (lp->a.read_csr(ioaddr,
443	89) << 16)) >>
444	12) & 0xffff;
445	if (i == 0x2627)
446	val \|= 3;
447	}
448	lp->a.write_bcr(ioaddr, 9, val);
449	}
450
451	/* set/reset GPSI bit in test register */
452	val = lp->a.read_csr(ioaddr, 124) & ~0x10;
453	if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
454	val \|= 0x10;
455	lp->a.write_csr(ioaddr, 124, val);
456
457	if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
458	val = lp->a.read_bcr(ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
459	if (lp->options & PCNET32_PORT_FD)
460	val \|= 0x10;
461	if (lp->options & PCNET32_PORT_100)
462	val \|= 0x08;
463	lp->a.write_bcr(ioaddr, 32, val);
464	} else {
465	if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
466	val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
467	val \|= 0x20;
468	lp->a.write_bcr(ioaddr, 32, val);
469	}
470	}
471
472	#ifdef DO_DXSUFLO
473	if (lp->dxsuflo) { /* Disable transmit stop on underflow */
474	val = lp->a.read_csr(ioaddr, 3);
475	val \|= 0x40;
476	lp->a.write_csr(ioaddr, 3, val);
477	}
478	#endif
479	if (1)
480	{
481	//disable interrupts
482	val = lp->a.read_csr(ioaddr, 3);
483	val = val
484	\| (1 << 14) //BABLM intr disabled
485	\| (1 << 12) //MISSM missed frame mask intr disabled
486	\| (1 << 10) //RINTM receive intr disabled
487	\| (1 << 9) //TINTM transmit intr disabled
488	\| (1 << 8) //IDONM init done intr disabled
489	;
490	lp->a.write_csr(ioaddr, 3, val);
491	}
492
493	if (lp->ltint) { /* Enable TxDone-intr inhibitor */
494	val = lp->a.read_csr(ioaddr, 5);
495	val \|= (1 << 14);
496	lp->a.write_csr(ioaddr, 5, val);
497	}
498	lp->init_block.mode =
499	le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
500	lp->init_block.filter[0] = 0xffffffff;
501	lp->init_block.filter[1] = 0xffffffff;
502
503	pcnet32_init_ring(nic);
504
505
506	/* Re-initialize the PCNET32, and start it when done. */
507	lp->a.write_csr(ioaddr, 1,
508	(virt_to_bus(&lp->init_block)) & 0xffff);
509	lp->a.write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
510	lp->a.write_csr(ioaddr, 4, 0x0915);
511	lp->a.write_csr(ioaddr, 0, 0x0001);
512
513
514	i = 0;
515	while (i++ < 100)
516	if (lp->a.read_csr(ioaddr, 0) & 0x0100)
517	break;
518	/*
519	* We used to clear the InitDone bit, 0x0100, here but Mark Stockton
520	* reports that doing so triggers a bug in the '974.
521	*/
522	lp->a.write_csr(ioaddr, 0, 0x0042);
523
524	dprintf(("pcnet32 open, csr0 %hX.\n", lp->a.read_csr(ioaddr, 0)));
525
526	}
527
528	/**************************************************************************
529	POLL - Wait for a frame
530	***************************************************************************/
531	static int pcnet32_poll(struct nic *nic __unused, int retrieve)
532	{
533	/* return true if there's an ethernet packet ready to read */
534	/* nic->packet should contain data on return */
535	/* nic->packetlen should contain length of data */
536
537	signed char status;
538	int entry;
539
540	entry = lp->cur_rx & RX_RING_MOD_MASK;
541	status = (le16_to_cpu(pcnet32_bufs.rx_ring[entry].status) >> 8);
542
543	if (status < 0)
544	return 0;
545
546	if ( ! retrieve ) return 1;
547
548	if (status == 0x03) {
549	nic->packetlen =
550	(le32_to_cpu(pcnet32_bufs.rx_ring[entry].msg_length)
551	& 0xfff) - 4;
552	memcpy(nic->packet, &pcnet32_bufs.rxb[entry], nic->packetlen);
553
554	/* Andrew Boyd of QNX reports that some revs of the 79C765
555	* clear the buffer length */
556	pcnet32_bufs.rx_ring[entry].buf_length
557	= le16_to_cpu(-PKT_BUF_SZ);
558	/* prime for next receive */
559	pcnet32_bufs.rx_ring[entry].status \|= le16_to_cpu(0x8000);
560	/* Switch to the next Rx ring buffer */
561	lp->cur_rx++;
562
563	} else {
564	return 0;
565	}
566
567	return 1;
568	}
569
570	/**************************************************************************
571	TRANSMIT - Transmit a frame
572	***************************************************************************/
573	static void pcnet32_transmit(struct nic nic __unused, const char d, /* Destination */
574	unsigned int t, /* Type */
575	unsigned int s, /* size */
576	const char *p)
577	{ /* Packet */
578	/* send the packet to destination */
579	unsigned long time;
580	u8 *ptxb;
581	u16 nstype;
582	u16 status;
583	int entry = 0; /lp->cur_tx & TX_RING_MOD_MASK; /
584
585	status = 0x8300;
586	/* point to the current txb incase multiple tx_rings are used */
587	ptxb = pcnet32_bufs.txb[lp->cur_tx];
588
589	/* copy the packet to ring buffer */
590	memcpy(ptxb, d, ETH_ALEN); /* dst */
591	memcpy(ptxb + ETH_ALEN, nic->node_addr, ETH_ALEN); /* src */
592	nstype = htons((u16) t); /* type */
593	memcpy(ptxb + 2 * ETH_ALEN, (u8 ) & nstype, 2); / type */
594	memcpy(ptxb + ETH_HLEN, p, s);
595
596	s += ETH_HLEN;
597	while (s < ETH_ZLEN) /* pad to min length */
598	ptxb[s++] = '\0';
599
600	pcnet32_bufs.tx_ring[entry].length = le16_to_cpu(-s);
601	pcnet32_bufs.tx_ring[entry].misc = 0x00000000;
602	pcnet32_bufs.tx_ring[entry].base = (u32) virt_to_le32desc(ptxb);
603
604	/* we set the top byte as the very last thing */
605	pcnet32_bufs.tx_ring[entry].status = le16_to_cpu(status);
606
607
608	/* Trigger an immediate send poll */
609	lp->a.write_csr(ioaddr, 0, 0x0048);
610
611	/* wait for transmit complete */
612	lp->cur_tx = 0; /* (lp->cur_tx + 1); */
613	time = currticks() + TICKS_PER_SEC; /* wait one second */
614	while (currticks() < time &&
615	((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0));
616
617	if ((short) le16_to_cpu(pcnet32_bufs.tx_ring[entry].status) < 0)
618	printf("PCNET32 timed out on transmit\n");
619
620	/* Stop pointing at the current txb
621	* otherwise the card continues to send the packet */
622	pcnet32_bufs.tx_ring[entry].base = 0;
623
624	}
625
626	/**************************************************************************
627	DISABLE - Turn off ethernet interface
628	***************************************************************************/
629	static void pcnet32_disable ( struct nic *nic __unused ) {
630	/* Stop the PCNET32 here -- it ocassionally polls memory if we don't */
631	lp->a.write_csr(ioaddr, 0, 0x0004);
632
633	/*
634	* Switch back to 16-bit mode to avoid problems with dumb
635	* DOS packet driver after a warm reboot
636	*/
637	lp->a.write_bcr(ioaddr, 20, 0);
638	}
639
640	/**************************************************************************
641	IRQ - Enable, Disable, or Force interrupts
642	***************************************************************************/
643	static void pcnet32_irq(struct nic *nic __unused, irq_action_t action __unused)
644	{
645	switch ( action ) {
646	case DISABLE :
647	break;
648	case ENABLE :
649	break;
650	case FORCE :
651	break;
652	}
653	}
654
655
656	/**************************************************************************
657	PROBE - Look for an adapter, this routine's visible to the outside
658	You should omit the last argument struct pci_device * for a non-PCI NIC
659	***************************************************************************/
660	static int pcnet32_probe ( struct nic nic, struct pci_device pci ) {
661
662	int i, media;
663	int fdx, mii, fset, dxsuflo, ltint;
664	int chip_version;
665	struct pcnet32_access *a = NULL;
666	char *chipname;
667	u8 promaddr[6];
668	int shared = 1;
669
670	if (pci->ioaddr == 0)
671	return 0;
672
673	/* BASE is used throughout to address the card */
674	ioaddr = pci->ioaddr;
675	printf("pcnet32.c: Found %s, Vendor=0x%hX Device=0x%hX\n",
676	pci->driver_name, pci->vendor, pci->device);
677
678	nic->irqno = 0;
679	nic->ioaddr = pci->ioaddr & ~3;
680
681	/* reset the chip */
682	pcnet32_wio_reset(ioaddr);
683
684	/* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
685	if (pcnet32_wio_read_csr(ioaddr, 0) == 4
686	&& pcnet32_wio_check(ioaddr)) {
687	a = &pcnet32_wio;
688	} else {
689	pcnet32_dwio_reset(ioaddr);
690	if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
691	&& pcnet32_dwio_check(ioaddr)) {
692	a = &pcnet32_dwio;
693	} else
694	return 0;
695	}
696
697	chip_version =
698	a->read_csr(ioaddr, 88) \| (a->read_csr(ioaddr, 89) << 16);
699
700	dprintf(("PCnet chip version is 0x%X\n", chip_version));
701	if ((chip_version & 0xfff) != 0x003)
702	return 0;
703
704	/* initialize variables */
705	fdx = mii = fset = dxsuflo = ltint = 0;
706	chip_version = (chip_version >> 12) & 0xffff;
707
708	switch (chip_version) {
709	case 0x2420:
710	chipname = "PCnet/PCI 79C970"; /* PCI */
711	break;
712	case 0x2430:
713	if (shared)
714	chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
715	else
716	chipname = "PCnet/32 79C965"; /* 486/VL bus */
717	break;
718	case 0x2621:
719	chipname = "PCnet/PCI II 79C970A"; /* PCI */
720	fdx = 1;
721	break;
722	case 0x2623:
723	chipname = "PCnet/FAST 79C971"; /* PCI */
724	fdx = 1;
725	mii = 1;
726	fset = 1;
727	ltint = 1;
728	break;
729	case 0x2624:
730	chipname = "PCnet/FAST+ 79C972"; /* PCI */
731	fdx = 1;
732	mii = 1;
733	fset = 1;
734	break;
735	case 0x2625:
736	chipname = "PCnet/FAST III 79C973"; /* PCI */
737	fdx = 1;
738	mii = 1;
739	break;
740	case 0x2626:
741	chipname = "PCnet/Home 79C978"; /* PCI */
742	fdx = 1;
743	/*
744	* This is based on specs published at www.amd.com. This section
745	* assumes that a card with a 79C978 wants to go into 1Mb HomePNA
746	* mode. The 79C978 can also go into standard ethernet, and there
747	* probably should be some sort of module option to select the
748	* mode by which the card should operate
749	*/
750	/* switch to home wiring mode */
751	media = a->read_bcr(ioaddr, 49);
752
753	printf("media reset to %#x.\n", media);
754	a->write_bcr(ioaddr, 49, media);
755	break;
756	case 0x2627:
757	chipname = "PCnet/FAST III 79C975"; /* PCI */
758	fdx = 1;
759	mii = 1;
760	break;
761	default:
762	chipname = "UNKNOWN";
763	printf("PCnet version %#x, no PCnet32 chip.\n",
764	chip_version);
765	return 0;
766	}
767
768	/*
769	* On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
770	* starting until the packet is loaded. Strike one for reliability, lose
771	* one for latency - although on PCI this isnt a big loss. Older chips
772	* have FIFO's smaller than a packet, so you can't do this.
773	*/
774
775	if (fset) {
776	a->write_bcr(ioaddr, 18,
777	(a->read_bcr(ioaddr, 18) \| 0x0800));
778	a->write_csr(ioaddr, 80,
779	(a->read_csr(ioaddr, 80) & 0x0C00) \| 0x0c00);
780	dxsuflo = 1;
781	ltint = 1;
782	}
783
784	DBG ( "%s at %hX,", chipname, (unsigned int) ioaddr );
785
786	/* read PROM address */
787	for (i = 0; i < 6; i++)
788	promaddr[i] = inb(ioaddr + i);
789
790	/* Update the nic structure with the MAC Address */
791	for (i = 0; i < ETH_ALEN; i++) {
792	nic->node_addr[i] = promaddr[i];
793	}
794
795	/* Print out some hardware info */
796	DBG ( "%s: IO Addr 0x%hX, MAC Addr %s\n ", chipname, (unsigned int) ioaddr,
797	eth_ntoa ( nic->node_addr ) );
798
799	/* Set to pci bus master */
800	adjust_pci_device(pci);
801
802	/* point to private storage */
803	lp = &lpx;
804
805	#if EBDEBUG
806	if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
807	i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
808	dprintf((" tx_start_pt(0x%hX):", i));
809	switch (i >> 10) {
810	case 0:
811	dprintf((" 20 bytes,"));
812	break;
813	case 1:
814	dprintf((" 64 bytes,"));
815	break;
816	case 2:
817	dprintf((" 128 bytes,"));
818	break;
819	case 3:
820	dprintf(("~220 bytes,"));
821	break;
822	}
823	i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
824	dprintf((" BCR18(%hX):", i & 0xffff));
825	if (i & (1 << 5))
826	dprintf(("BurstWrEn "));
827	if (i & (1 << 6))
828	dprintf(("BurstRdEn "));
829	if (i & (1 << 7))
830	dprintf(("DWordIO "));
831	if (i & (1 << 11))
832	dprintf(("NoUFlow "));
833	i = a->read_bcr(ioaddr, 25);
834	dprintf((" SRAMSIZE=0x%hX,", i << 8));
835	i = a->read_bcr(ioaddr, 26);
836	dprintf((" SRAM_BND=0x%hX,", i << 8));
837	i = a->read_bcr(ioaddr, 27);
838	if (i & (1 << 14))
839	dprintf(("LowLatRx"));
840	}
841	#endif
842	lp->name = chipname;
843	lp->shared_irq = shared;
844	lp->full_duplex = fdx;
845	lp->dxsuflo = dxsuflo;
846	lp->ltint = ltint;
847	lp->mii = mii;
848	/* FIXME: Fix Options for only one card */
849	if ((cards_found >= MAX_UNITS)
850	\|\| ((unsigned int) options[cards_found] > sizeof(options_mapping)))
851	lp->options = PCNET32_PORT_ASEL;
852	else
853	lp->options = options_mapping[options[cards_found]];
854
855	if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
856	((cards_found >= MAX_UNITS) \|\| full_duplex[cards_found]))
857	lp->options \|= PCNET32_PORT_FD;
858
859	if (!a) {
860	printf("No access methods\n");
861	return 0;
862	}
863
864	// lp->a = *a;
865	// Causes a loader:
866	// bin/blib.a(pcnet32.o)(.text+0x6b6): In function `pcnet32_probe':
867	// drivers/net/pcnet32.c:871: undefined reference to `memcpy'
868	// make: *** [bin/pcnet32.dsk.tmp] Error 1
869	// So we do:
870	memcpy ( &lp->a, a, sizeof ( lp->a ) );
871	// To explicity call memcpy.
872
873	/* detect special T1/E1 WAN card by checking for MAC address */
874	if (nic->node_addr[0] == 0x00 && nic->node_addr[1] == 0xe0
875	&& nic->node_addr[2] == 0x75)
876	lp->options = PCNET32_PORT_FD \| PCNET32_PORT_GPSI;
877
878	lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
879	lp->init_block.tlen_rlen =
880	le16_to_cpu(TX_RING_LEN_BITS \| RX_RING_LEN_BITS);
881	for (i = 0; i < 6; i++)
882	lp->init_block.phys_addr[i] = nic->node_addr[i];
883	lp->init_block.filter[0] = 0xffffffff;
884	lp->init_block.filter[1] = 0xffffffff;
885	lp->init_block.rx_ring = virt_to_bus(&pcnet32_bufs.rx_ring);
886	lp->init_block.tx_ring = virt_to_bus(&pcnet32_bufs.tx_ring);
887
888	/* switch pcnet32 to 32bit mode */
889	a->write_bcr(ioaddr, 20, 2);
890
891	a->write_csr(ioaddr, 1, (virt_to_bus(&lp->init_block)) & 0xffff);
892	a->write_csr(ioaddr, 2, (virt_to_bus(&lp->init_block)) >> 16);
893
894	/*
895	* To auto-IRQ we enable the initialization-done and DMA error
896	* interrupts. For ISA boards we get a DMA error, but VLB and PCI
897	* boards will work.
898	*/
899	/* Trigger an initialization just for the interrupt. */
900
901
902	// a->write_csr(ioaddr, 0, 0x41);
903	// mdelay(1);
904
905	cards_found++;
906
907	/* point to NIC specific routines */
908	pcnet32_reset(nic);
909	if (mii) {
910	int tmp;
911	int phy, phy_idx = 0;
912	u16 mii_lpa;
913	lp->phys[0] = 1; /* Default Setting */
914	for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
915	int mii_status = mdio_read(nic, phy, MII_BMSR);
916	if (mii_status != 0xffff && mii_status != 0x0000) {
917	lp->phys[phy_idx++] = phy;
918	lp->mii_if.advertising =
919	mdio_read(nic, phy, MII_ADVERTISE);
920	if ((mii_status & 0x0040) == 0) {
921	tmp = phy;
922	dprintf (("MII PHY found at address %d, status "
923	"%hX advertising %hX\n", phy, mii_status,
924	lp->mii_if.advertising));
925	}
926	}
927	}
928	if (phy_idx == 0)
929	printf("No MII transceiver found!\n");
930	lp->mii_if.phy_id = lp->phys[0];
931
932	lp->mii_if.advertising =
933	mdio_read(nic, lp->phys[0], MII_ADVERTISE);
934
935	mii_lpa = mdio_read(nic, lp->phys[0], MII_LPA);
936	lp->mii_if.advertising &= mii_lpa;
937	if (lp->mii_if.advertising & ADVERTISE_100FULL)
938	printf("100Mbps Full-Duplex\n");
939	else if (lp->mii_if.advertising & ADVERTISE_100HALF)
940	printf("100Mbps Half-Duplex\n");
941	else if (lp->mii_if.advertising & ADVERTISE_10FULL)
942	printf("10Mbps Full-Duplex\n");
943	else if (lp->mii_if.advertising & ADVERTISE_10HALF)
944	printf("10Mbps Half-Duplex\n");
945	else
946	printf("\n");
947	} else {
948	/* The older chips are fixed 10Mbps, and some support full duplex,
949	* although not via autonegotiation, but only via configuration. */
950	if (fdx)
951	printf("10Mbps Full-Duplex\n");
952	else
953	printf("10Mbps Half-Duplex\n");
954	}
955
956	nic->nic_op = &pcnet32_operations;
957
958	return 1;
959	}
960	static int mdio_read(struct nic *nic __unused, int phy_id, int reg_num)
961	{
962	u16 val_out;
963	int phyaddr;
964
965	if (!lp->mii)
966	return 0;
967
968	phyaddr = lp->a.read_bcr(ioaddr, 33);
969
970	lp->a.write_bcr(ioaddr, 33,
971	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
972	val_out = lp->a.read_bcr(ioaddr, 34);
973	lp->a.write_bcr(ioaddr, 33, phyaddr);
974
975	return val_out;
976	}
977
978	#if 0
979	static void mdio_write(struct nic *nic __unused, int phy_id, int reg_num,
980	int val)
981	{
982	int phyaddr;
983
984	if (!lp->mii)
985	return;
986
987	phyaddr = lp->a.read_bcr(ioaddr, 33);
988
989	lp->a.write_bcr(ioaddr, 33,
990	((phy_id & 0x1f) << 5) \| (reg_num & 0x1f));
991	lp->a.write_bcr(ioaddr, 34, val);
992	lp->a.write_bcr(ioaddr, 33, phyaddr);
993	}
994	#endif
995
996	static struct nic_operations pcnet32_operations = {
997	.connect = dummy_connect,
998	.poll = pcnet32_poll,
999	.transmit = pcnet32_transmit,
1000	.irq = pcnet32_irq,
1001
1002	};
1003
1004	static struct pci_device_id pcnet32_nics[] = {
1005	PCI_ROM(0x1022, 0x2000, "pcnet32", "AMD PCnet/PCI", 0),
1006	PCI_ROM(0x1022, 0x2625, "pcnetfastiii", "AMD PCNet FAST III", 0),
1007	PCI_ROM(0x1022, 0x2001, "amdhomepna", "AMD PCnet/HomePNA", 0),
1008	};
1009
1010	PCI_DRIVER ( pcnet32_driver, pcnet32_nics, PCI_NO_CLASS );
1011
1012	DRIVER ( "PCNET32/PCI", nic_driver, pci_driver, pcnet32_driver,
1013	pcnet32_probe, pcnet32_disable );
1014
1015	/*
1016	* Local variables:
1017	* c-basic-offset: 8
1018	* c-indent-level: 8
1019	* tab-width: 8
1020	* End:
1021	*/

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