1 | /************************************************************************** |
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2 | * |
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3 | * tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN |
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4 | * Written 2003-2003 by Timothy Legge <tlegge@rogers.com> |
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5 | * |
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6 | * This program is free software; you can redistribute it and/or modify |
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7 | * it under the terms of the GNU General Public License as published by |
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8 | * the Free Software Foundation; either version 2 of the License, or |
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9 | * (at your option) any later version. |
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10 | * |
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11 | * This program is distributed in the hope that it will be useful, |
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12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
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13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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14 | * GNU General Public License for more details. |
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15 | * |
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16 | * You should have received a copy of the GNU General Public License |
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17 | * along with this program; if not, write to the Free Software |
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18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
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19 | * |
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20 | * Portions of this code (almost all) based on: |
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21 | * tlan.c: Linux ThunderLan Driver: |
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22 | * |
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23 | * by James Banks |
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24 | * |
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25 | * (C) 1997-1998 Caldera, Inc. |
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26 | * (C) 1998 James Banks |
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27 | * (C) 1999-2001 Torben Mathiasen |
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28 | * (C) 2002 Samuel Chessman |
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29 | * |
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30 | * REVISION HISTORY: |
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31 | * ================ |
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32 | * v1.0 07-08-2003 timlegge Initial not quite working version |
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33 | * |
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34 | * Indent Style: indent -kr -i8 |
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35 | ***************************************************************************/ |
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36 | |
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37 | FILE_LICENCE ( GPL2_OR_LATER ); |
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38 | |
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39 | /***************************************************************** |
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40 | * TLan Definitions |
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41 | * |
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42 | ****************************************************************/ |
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43 | |
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44 | #define FALSE 0 |
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45 | #define TRUE 1 |
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46 | |
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47 | #define TLAN_MIN_FRAME_SIZE 64 |
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48 | #define TLAN_MAX_FRAME_SIZE 1600 |
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49 | |
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50 | #define TLAN_NUM_RX_LISTS 4 |
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51 | #define TLAN_NUM_TX_LISTS 2 |
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52 | |
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53 | #define TLAN_IGNORE 0 |
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54 | #define TLAN_RECORD 1 |
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55 | /* |
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56 | #define TLAN_DBG(lvl, format, args...) if (debug&lvl) printf("TLAN: " format, ##args ); |
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57 | */ |
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58 | #define TLAN_DEBUG_GNRL 0x0001 |
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59 | #define TLAN_DEBUG_TX 0x0002 |
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60 | #define TLAN_DEBUG_RX 0x0004 |
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61 | #define TLAN_DEBUG_LIST 0x0008 |
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62 | #define TLAN_DEBUG_PROBE 0x0010 |
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63 | |
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64 | #define TX_TIMEOUT (10*HZ) /* We need time for auto-neg */ |
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65 | #define MAX_TLAN_BOARDS 8 /* Max number of boards installed at a time */ |
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66 | |
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67 | |
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68 | /***************************************************************** |
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69 | * Device Identification Definitions |
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70 | * |
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71 | ****************************************************************/ |
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72 | |
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73 | #define PCI_DEVICE_ID_NETELLIGENT_10_T2 0xB012 |
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74 | #define PCI_DEVICE_ID_NETELLIGENT_10_100_WS_5100 0xB030 |
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75 | #ifndef PCI_DEVICE_ID_OLICOM_OC2183 |
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76 | #define PCI_DEVICE_ID_OLICOM_OC2183 0x0013 |
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77 | #endif |
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78 | #ifndef PCI_DEVICE_ID_OLICOM_OC2325 |
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79 | #define PCI_DEVICE_ID_OLICOM_OC2325 0x0012 |
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80 | #endif |
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81 | #ifndef PCI_DEVICE_ID_OLICOM_OC2326 |
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82 | #define PCI_DEVICE_ID_OLICOM_OC2326 0x0014 |
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83 | #endif |
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84 | |
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85 | typedef struct tlan_adapter_entry { |
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86 | u16 vendorId; |
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87 | u16 deviceId; |
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88 | char *deviceLabel; |
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89 | u32 flags; |
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90 | u16 addrOfs; |
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91 | } TLanAdapterEntry; |
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92 | |
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93 | #define TLAN_ADAPTER_NONE 0x00000000 |
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94 | #define TLAN_ADAPTER_UNMANAGED_PHY 0x00000001 |
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95 | #define TLAN_ADAPTER_BIT_RATE_PHY 0x00000002 |
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96 | #define TLAN_ADAPTER_USE_INTERN_10 0x00000004 |
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97 | #define TLAN_ADAPTER_ACTIVITY_LED 0x00000008 |
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98 | |
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99 | #define TLAN_SPEED_DEFAULT 0 |
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100 | #define TLAN_SPEED_10 10 |
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101 | #define TLAN_SPEED_100 100 |
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102 | |
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103 | #define TLAN_DUPLEX_DEFAULT 0 |
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104 | #define TLAN_DUPLEX_HALF 1 |
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105 | #define TLAN_DUPLEX_FULL 2 |
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106 | |
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107 | |
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108 | |
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109 | /***************************************************************** |
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110 | * EISA Definitions |
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111 | * |
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112 | ****************************************************************/ |
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113 | |
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114 | #define EISA_ID 0xc80 /* EISA ID Registers */ |
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115 | #define EISA_ID0 0xc80 /* EISA ID Register 0 */ |
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116 | #define EISA_ID1 0xc81 /* EISA ID Register 1 */ |
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117 | #define EISA_ID2 0xc82 /* EISA ID Register 2 */ |
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118 | #define EISA_ID3 0xc83 /* EISA ID Register 3 */ |
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119 | #define EISA_CR 0xc84 /* EISA Control Register */ |
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120 | #define EISA_REG0 0xc88 /* EISA Configuration Register 0 */ |
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121 | #define EISA_REG1 0xc89 /* EISA Configuration Register 1 */ |
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122 | #define EISA_REG2 0xc8a /* EISA Configuration Register 2 */ |
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123 | #define EISA_REG3 0xc8f /* EISA Configuration Register 3 */ |
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124 | #define EISA_APROM 0xc90 /* Ethernet Address PROM */ |
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125 | |
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126 | |
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127 | |
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128 | /***************************************************************** |
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129 | * Rx/Tx List Definitions |
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130 | * |
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131 | ****************************************************************/ |
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132 | |
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133 | #define TLAN_BUFFERS_PER_LIST 10 |
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134 | #define TLAN_LAST_BUFFER 0x80000000 |
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135 | #define TLAN_CSTAT_UNUSED 0x8000 |
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136 | #define TLAN_CSTAT_FRM_CMP 0x4000 |
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137 | #define TLAN_CSTAT_READY 0x3000 |
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138 | #define TLAN_CSTAT_EOC 0x0800 |
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139 | #define TLAN_CSTAT_RX_ERROR 0x0400 |
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140 | #define TLAN_CSTAT_PASS_CRC 0x0200 |
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141 | #define TLAN_CSTAT_DP_PR 0x0100 |
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142 | |
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143 | |
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144 | |
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145 | |
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146 | |
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147 | |
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148 | /***************************************************************** |
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149 | * PHY definitions |
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150 | * |
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151 | ****************************************************************/ |
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152 | |
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153 | #define TLAN_PHY_MAX_ADDR 0x1F |
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154 | #define TLAN_PHY_NONE 0x20 |
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155 | |
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156 | |
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157 | |
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158 | /***************************************************************** |
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159 | * TLan Driver Timer Definitions |
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160 | * |
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161 | ****************************************************************/ |
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162 | |
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163 | #define TLAN_TIMER_LINK_BEAT 1 |
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164 | #define TLAN_TIMER_ACTIVITY 2 |
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165 | #define TLAN_TIMER_PHY_PDOWN 3 |
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166 | #define TLAN_TIMER_PHY_PUP 4 |
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167 | #define TLAN_TIMER_PHY_RESET 5 |
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168 | #define TLAN_TIMER_PHY_START_LINK 6 |
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169 | #define TLAN_TIMER_PHY_FINISH_AN 7 |
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170 | #define TLAN_TIMER_FINISH_RESET 8 |
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171 | |
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172 | #define TLAN_TIMER_ACT_DELAY (HZ/10) |
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173 | |
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174 | |
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175 | |
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176 | |
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177 | /***************************************************************** |
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178 | * TLan Driver Eeprom Definitions |
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179 | * |
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180 | ****************************************************************/ |
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181 | |
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182 | #define TLAN_EEPROM_ACK 0 |
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183 | #define TLAN_EEPROM_STOP 1 |
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184 | |
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185 | |
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186 | |
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187 | |
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188 | /***************************************************************** |
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189 | * Host Register Offsets and Contents |
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190 | * |
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191 | ****************************************************************/ |
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192 | |
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193 | #define TLAN_HOST_CMD 0x00 |
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194 | #define TLAN_HC_GO 0x80000000 |
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195 | #define TLAN_HC_STOP 0x40000000 |
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196 | #define TLAN_HC_ACK 0x20000000 |
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197 | #define TLAN_HC_CS_MASK 0x1FE00000 |
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198 | #define TLAN_HC_EOC 0x00100000 |
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199 | #define TLAN_HC_RT 0x00080000 |
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200 | #define TLAN_HC_NES 0x00040000 |
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201 | #define TLAN_HC_AD_RST 0x00008000 |
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202 | #define TLAN_HC_LD_TMR 0x00004000 |
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203 | #define TLAN_HC_LD_THR 0x00002000 |
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204 | #define TLAN_HC_REQ_INT 0x00001000 |
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205 | #define TLAN_HC_INT_OFF 0x00000800 |
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206 | #define TLAN_HC_INT_ON 0x00000400 |
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207 | #define TLAN_HC_AC_MASK 0x000000FF |
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208 | #define TLAN_CH_PARM 0x04 |
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209 | #define TLAN_DIO_ADR 0x08 |
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210 | #define TLAN_DA_ADR_INC 0x8000 |
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211 | #define TLAN_DA_RAM_ADR 0x4000 |
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212 | #define TLAN_HOST_INT 0x0A |
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213 | #define TLAN_HI_IV_MASK 0x1FE0 |
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214 | #define TLAN_HI_IT_MASK 0x001C |
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215 | #define TLAN_DIO_DATA 0x0C |
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216 | |
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217 | |
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218 | /* ThunderLAN Internal Register DIO Offsets */ |
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219 | |
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220 | #define TLAN_NET_CMD 0x00 |
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221 | #define TLAN_NET_CMD_NRESET 0x80 |
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222 | #define TLAN_NET_CMD_NWRAP 0x40 |
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223 | #define TLAN_NET_CMD_CSF 0x20 |
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224 | #define TLAN_NET_CMD_CAF 0x10 |
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225 | #define TLAN_NET_CMD_NOBRX 0x08 |
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226 | #define TLAN_NET_CMD_DUPLEX 0x04 |
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227 | #define TLAN_NET_CMD_TRFRAM 0x02 |
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228 | #define TLAN_NET_CMD_TXPACE 0x01 |
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229 | #define TLAN_NET_SIO 0x01 |
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230 | #define TLAN_NET_SIO_MINTEN 0x80 |
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231 | #define TLAN_NET_SIO_ECLOK 0x40 |
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232 | #define TLAN_NET_SIO_ETXEN 0x20 |
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233 | #define TLAN_NET_SIO_EDATA 0x10 |
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234 | #define TLAN_NET_SIO_NMRST 0x08 |
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235 | #define TLAN_NET_SIO_MCLK 0x04 |
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236 | #define TLAN_NET_SIO_MTXEN 0x02 |
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237 | #define TLAN_NET_SIO_MDATA 0x01 |
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238 | #define TLAN_NET_STS 0x02 |
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239 | #define TLAN_NET_STS_MIRQ 0x80 |
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240 | #define TLAN_NET_STS_HBEAT 0x40 |
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241 | #define TLAN_NET_STS_TXSTOP 0x20 |
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242 | #define TLAN_NET_STS_RXSTOP 0x10 |
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243 | #define TLAN_NET_STS_RSRVD 0x0F |
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244 | #define TLAN_NET_MASK 0x03 |
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245 | #define TLAN_NET_MASK_MASK7 0x80 |
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246 | #define TLAN_NET_MASK_MASK6 0x40 |
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247 | #define TLAN_NET_MASK_MASK5 0x20 |
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248 | #define TLAN_NET_MASK_MASK4 0x10 |
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249 | #define TLAN_NET_MASK_RSRVD 0x0F |
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250 | #define TLAN_NET_CONFIG 0x04 |
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251 | #define TLAN_NET_CFG_RCLK 0x8000 |
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252 | #define TLAN_NET_CFG_TCLK 0x4000 |
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253 | #define TLAN_NET_CFG_BIT 0x2000 |
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254 | #define TLAN_NET_CFG_RXCRC 0x1000 |
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255 | #define TLAN_NET_CFG_PEF 0x0800 |
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256 | #define TLAN_NET_CFG_1FRAG 0x0400 |
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257 | #define TLAN_NET_CFG_1CHAN 0x0200 |
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258 | #define TLAN_NET_CFG_MTEST 0x0100 |
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259 | #define TLAN_NET_CFG_PHY_EN 0x0080 |
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260 | #define TLAN_NET_CFG_MSMASK 0x007F |
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261 | #define TLAN_MAN_TEST 0x06 |
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262 | #define TLAN_DEF_VENDOR_ID 0x08 |
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263 | #define TLAN_DEF_DEVICE_ID 0x0A |
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264 | #define TLAN_DEF_REVISION 0x0C |
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265 | #define TLAN_DEF_SUBCLASS 0x0D |
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266 | #define TLAN_DEF_MIN_LAT 0x0E |
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267 | #define TLAN_DEF_MAX_LAT 0x0F |
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268 | #define TLAN_AREG_0 0x10 |
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269 | #define TLAN_AREG_1 0x16 |
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270 | #define TLAN_AREG_2 0x1C |
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271 | #define TLAN_AREG_3 0x22 |
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272 | #define TLAN_HASH_1 0x28 |
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273 | #define TLAN_HASH_2 0x2C |
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274 | #define TLAN_GOOD_TX_FRMS 0x30 |
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275 | #define TLAN_TX_UNDERUNS 0x33 |
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276 | #define TLAN_GOOD_RX_FRMS 0x34 |
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277 | #define TLAN_RX_OVERRUNS 0x37 |
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278 | #define TLAN_DEFERRED_TX 0x38 |
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279 | #define TLAN_CRC_ERRORS 0x3A |
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280 | #define TLAN_CODE_ERRORS 0x3B |
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281 | #define TLAN_MULTICOL_FRMS 0x3C |
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282 | #define TLAN_SINGLECOL_FRMS 0x3E |
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283 | #define TLAN_EXCESSCOL_FRMS 0x40 |
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284 | #define TLAN_LATE_COLS 0x41 |
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285 | #define TLAN_CARRIER_LOSS 0x42 |
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286 | #define TLAN_ACOMMIT 0x43 |
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287 | #define TLAN_LED_REG 0x44 |
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288 | #define TLAN_LED_ACT 0x10 |
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289 | #define TLAN_LED_LINK 0x01 |
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290 | #define TLAN_BSIZE_REG 0x45 |
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291 | #define TLAN_MAX_RX 0x46 |
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292 | #define TLAN_INT_DIS 0x48 |
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293 | #define TLAN_ID_TX_EOC 0x04 |
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294 | #define TLAN_ID_RX_EOF 0x02 |
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295 | #define TLAN_ID_RX_EOC 0x01 |
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296 | |
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297 | |
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298 | |
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299 | /* ThunderLAN Interrupt Codes */ |
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300 | |
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301 | #define TLAN_INT_NUMBER_OF_INTS 8 |
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302 | |
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303 | #define TLAN_INT_NONE 0x0000 |
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304 | #define TLAN_INT_TX_EOF 0x0001 |
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305 | #define TLAN_INT_STAT_OVERFLOW 0x0002 |
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306 | #define TLAN_INT_RX_EOF 0x0003 |
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307 | #define TLAN_INT_DUMMY 0x0004 |
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308 | #define TLAN_INT_TX_EOC 0x0005 |
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309 | #define TLAN_INT_STATUS_CHECK 0x0006 |
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310 | #define TLAN_INT_RX_EOC 0x0007 |
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311 | |
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312 | |
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313 | |
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314 | /* ThunderLAN MII Registers */ |
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315 | |
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316 | /* ThunderLAN Specific MII/PHY Registers */ |
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317 | |
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318 | #define TLAN_TLPHY_ID 0x10 |
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319 | #define TLAN_TLPHY_CTL 0x11 |
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320 | #define TLAN_TC_IGLINK 0x8000 |
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321 | #define TLAN_TC_SWAPOL 0x4000 |
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322 | #define TLAN_TC_AUISEL 0x2000 |
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323 | #define TLAN_TC_SQEEN 0x1000 |
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324 | #define TLAN_TC_MTEST 0x0800 |
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325 | #define TLAN_TC_RESERVED 0x07F8 |
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326 | #define TLAN_TC_NFEW 0x0004 |
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327 | #define TLAN_TC_INTEN 0x0002 |
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328 | #define TLAN_TC_TINT 0x0001 |
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329 | #define TLAN_TLPHY_STS 0x12 |
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330 | #define TLAN_TS_MINT 0x8000 |
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331 | #define TLAN_TS_PHOK 0x4000 |
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332 | #define TLAN_TS_POLOK 0x2000 |
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333 | #define TLAN_TS_TPENERGY 0x1000 |
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334 | #define TLAN_TS_RESERVED 0x0FFF |
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335 | #define TLAN_TLPHY_PAR 0x19 |
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336 | #define TLAN_PHY_CIM_STAT 0x0020 |
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337 | #define TLAN_PHY_SPEED_100 0x0040 |
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338 | #define TLAN_PHY_DUPLEX_FULL 0x0080 |
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339 | #define TLAN_PHY_AN_EN_STAT 0x0400 |
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340 | |
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341 | /* National Sem. & Level1 PHY id's */ |
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342 | #define NAT_SEM_ID1 0x2000 |
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343 | #define NAT_SEM_ID2 0x5C01 |
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344 | #define LEVEL1_ID1 0x7810 |
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345 | #define LEVEL1_ID2 0x0000 |
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346 | |
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347 | #define CIRC_INC( a, b ) if ( ++a >= b ) a = 0 |
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348 | |
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349 | /* Routines to access internal registers. */ |
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350 | |
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351 | static inline u8 TLan_DioRead8(u16 base_addr, u16 internal_addr) |
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352 | { |
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353 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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354 | return (inb((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x3))); |
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355 | |
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356 | } /* TLan_DioRead8 */ |
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357 | |
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358 | |
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359 | |
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360 | |
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361 | static inline u16 TLan_DioRead16(u16 base_addr, u16 internal_addr) |
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362 | { |
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363 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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364 | return (inw((base_addr + TLAN_DIO_DATA) + (internal_addr & 0x2))); |
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365 | |
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366 | } /* TLan_DioRead16 */ |
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367 | |
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368 | |
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369 | |
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370 | |
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371 | static inline u32 TLan_DioRead32(u16 base_addr, u16 internal_addr) |
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372 | { |
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373 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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374 | return (inl(base_addr + TLAN_DIO_DATA)); |
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375 | |
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376 | } /* TLan_DioRead32 */ |
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377 | |
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378 | |
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379 | |
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380 | |
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381 | static inline void TLan_DioWrite8(u16 base_addr, u16 internal_addr, u8 data) |
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382 | { |
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383 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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384 | outb(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x3)); |
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385 | |
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386 | } |
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387 | |
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388 | |
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389 | |
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390 | |
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391 | static inline void TLan_DioWrite16(u16 base_addr, u16 internal_addr, u16 data) |
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392 | { |
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393 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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394 | outw(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); |
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395 | |
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396 | } |
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397 | |
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398 | |
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399 | |
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400 | |
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401 | static inline void TLan_DioWrite32(u16 base_addr, u16 internal_addr, u32 data) |
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402 | { |
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403 | outw(internal_addr, base_addr + TLAN_DIO_ADR); |
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404 | outl(data, base_addr + TLAN_DIO_DATA + (internal_addr & 0x2)); |
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405 | |
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406 | } |
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407 | |
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408 | |
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409 | |
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410 | #if 0 |
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411 | static inline void TLan_ClearBit(u8 bit, u16 port) |
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412 | { |
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413 | outb_p(inb_p(port) & ~bit, port); |
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414 | } |
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415 | |
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416 | |
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417 | |
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418 | |
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419 | static inline int TLan_GetBit(u8 bit, u16 port) |
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420 | { |
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421 | return ((int) (inb_p(port) & bit)); |
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422 | } |
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423 | |
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424 | |
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425 | |
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426 | |
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427 | static inline void TLan_SetBit(u8 bit, u16 port) |
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428 | { |
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429 | outb_p(inb_p(port) | bit, port); |
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430 | } |
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431 | #endif |
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432 | |
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433 | #define TLan_ClearBit( bit, port ) outb_p(inb_p(port) & ~bit, port) |
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434 | #define TLan_GetBit( bit, port ) ((int) (inb_p(port) & bit)) |
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435 | #define TLan_SetBit( bit, port ) outb_p(inb_p(port) | bit, port) |
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436 | |
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437 | #ifdef I_LIKE_A_FAST_HASH_FUNCTION |
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438 | /* given 6 bytes, view them as 8 6-bit numbers and return the XOR of those */ |
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439 | /* the code below is about seven times as fast as the original code */ |
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440 | static inline u32 TLan_HashFunc(u8 * a) |
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441 | { |
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442 | u8 hash; |
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443 | |
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444 | hash = (a[0] ^ a[3]); /* & 077 */ |
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445 | hash ^= ((a[0] ^ a[3]) >> 6); /* & 003 */ |
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446 | hash ^= ((a[1] ^ a[4]) << 2); /* & 074 */ |
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447 | hash ^= ((a[1] ^ a[4]) >> 4); /* & 017 */ |
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448 | hash ^= ((a[2] ^ a[5]) << 4); /* & 060 */ |
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449 | hash ^= ((a[2] ^ a[5]) >> 2); /* & 077 */ |
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450 | |
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451 | return (hash & 077); |
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452 | } |
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453 | |
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454 | #else /* original code */ |
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455 | |
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456 | static inline u32 xor(u32 a, u32 b) |
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457 | { |
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458 | return ((a && !b) || (!a && b)); |
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459 | } |
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460 | |
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461 | #define XOR8( a, b, c, d, e, f, g, h ) xor( a, xor( b, xor( c, xor( d, xor( e, xor( f, xor( g, h ) ) ) ) ) ) ) |
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462 | #define DA( a, bit ) ( ( (u8) a[bit/8] ) & ( (u8) ( 1 << bit%8 ) ) ) |
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463 | |
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464 | static inline u32 TLan_HashFunc(u8 * a) |
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465 | { |
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466 | u32 hash; |
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467 | |
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468 | hash = |
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469 | XOR8(DA(a, 0), DA(a, 6), DA(a, 12), DA(a, 18), DA(a, 24), |
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470 | DA(a, 30), DA(a, 36), DA(a, 42)); |
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471 | hash |= |
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472 | XOR8(DA(a, 1), DA(a, 7), DA(a, 13), DA(a, 19), DA(a, 25), |
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473 | DA(a, 31), DA(a, 37), DA(a, 43)) << 1; |
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474 | hash |= |
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475 | XOR8(DA(a, 2), DA(a, 8), DA(a, 14), DA(a, 20), DA(a, 26), |
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476 | DA(a, 32), DA(a, 38), DA(a, 44)) << 2; |
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477 | hash |= |
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478 | XOR8(DA(a, 3), DA(a, 9), DA(a, 15), DA(a, 21), DA(a, 27), |
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479 | DA(a, 33), DA(a, 39), DA(a, 45)) << 3; |
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480 | hash |= |
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481 | XOR8(DA(a, 4), DA(a, 10), DA(a, 16), DA(a, 22), DA(a, 28), |
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482 | DA(a, 34), DA(a, 40), DA(a, 46)) << 4; |
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483 | hash |= |
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484 | XOR8(DA(a, 5), DA(a, 11), DA(a, 17), DA(a, 23), DA(a, 29), |
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485 | DA(a, 35), DA(a, 41), DA(a, 47)) << 5; |
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486 | |
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487 | return hash; |
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488 | |
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489 | } |
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490 | |
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491 | #endif /* I_LIKE_A_FAST_HASH_FUNCTION */ |
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