| 1 | /* |
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| 2 | * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved. |
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| 3 | * |
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| 4 | * Redistribution and use in source and binary forms, with or without |
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| 5 | * modification, are permitted provided that the following conditions are |
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| 6 | * met: 1. Redistributions of source code must retain the above copyright |
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| 7 | * notice, this list of conditions and the following disclaimer. 2. The name |
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| 8 | * of the author may not be used to endorse or promote products derived from |
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| 9 | * this software without specific prior written permission |
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| 10 | * |
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| 11 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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| 12 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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| 13 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO |
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| 14 | * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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| 15 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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| 16 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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| 17 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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| 18 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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| 19 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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| 20 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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| 21 | * |
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| 22 | October 2, 1994 |
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| 23 | |
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| 24 | Modified by: Andres Vega Garcia |
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| 25 | |
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| 26 | INRIA - Sophia Antipolis, France |
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| 27 | e-mail: avega@sophia.inria.fr |
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| 28 | finger: avega@pax.inria.fr |
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| 29 | |
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| 30 | */ |
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| 31 | |
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| 32 | FILE_LICENCE ( BSD3 ); |
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| 33 | |
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| 34 | /* |
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| 35 | * Created from if_epreg.h by Fred Gray (fgray@rice.edu) to support the |
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| 36 | * 3c590 family. |
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| 37 | */ |
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| 38 | |
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| 39 | /* |
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| 40 | * Modified by Shusuke Nisiyama <shu@athena.qe.eng.hokudai.ac.jp> |
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| 41 | * for etherboot |
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| 42 | * Mar. 14, 2000 |
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| 43 | */ |
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| 44 | |
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| 45 | /* |
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| 46 | * Ethernet software status per interface. |
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| 47 | */ |
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| 48 | |
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| 49 | /* |
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| 50 | * Some global constants |
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| 51 | */ |
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| 52 | |
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| 53 | #define TX_INIT_RATE 16 |
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| 54 | #define TX_INIT_MAX_RATE 64 |
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| 55 | #define RX_INIT_LATENCY 64 |
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| 56 | #define RX_INIT_EARLY_THRESH 64 |
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| 57 | #define MIN_RX_EARLY_THRESHF 16 /* not less than ether_header */ |
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| 58 | #define MIN_RX_EARLY_THRESHL 4 |
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| 59 | |
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| 60 | #define EEPROMSIZE 0x40 |
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| 61 | #define MAX_EEPROMBUSY 1000 |
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| 62 | #define VX_LAST_TAG 0xd7 |
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| 63 | #define VX_MAX_BOARDS 16 |
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| 64 | #define VX_ID_PORT 0x100 |
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| 65 | |
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| 66 | /* |
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| 67 | * some macros to acces long named fields |
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| 68 | */ |
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| 69 | #define BASE (eth_nic_base) |
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| 70 | |
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| 71 | /* |
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| 72 | * Commands to read/write EEPROM trough EEPROM command register (Window 0, |
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| 73 | * Offset 0xa) |
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| 74 | */ |
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| 75 | #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */ |
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| 76 | #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */ |
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| 77 | #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */ |
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| 78 | #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */ |
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| 79 | |
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| 80 | #define EEPROM_BUSY (1<<15) |
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| 81 | |
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| 82 | /* |
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| 83 | * Some short functions, worth to let them be a macro |
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| 84 | */ |
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| 85 | |
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| 86 | /************************************************************************** |
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| 87 | * * |
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| 88 | * These define the EEPROM data structure. They are used in the probe |
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| 89 | * function to verify the existence of the adapter after having sent |
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| 90 | * the ID_Sequence. |
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| 91 | * |
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| 92 | * There are others but only the ones we use are defined here. |
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| 93 | * |
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| 94 | **************************************************************************/ |
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| 95 | |
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| 96 | #define EEPROM_NODE_ADDR_0 0x0 /* Word */ |
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| 97 | #define EEPROM_NODE_ADDR_1 0x1 /* Word */ |
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| 98 | #define EEPROM_NODE_ADDR_2 0x2 /* Word */ |
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| 99 | #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */ |
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| 100 | #define EEPROM_MFG_ID 0x7 /* 0x6d50 */ |
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| 101 | #define EEPROM_ADDR_CFG 0x8 /* Base addr */ |
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| 102 | #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */ |
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| 103 | #define EEPROM_OEM_ADDR_0 0xa /* Word */ |
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| 104 | #define EEPROM_OEM_ADDR_1 0xb /* Word */ |
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| 105 | #define EEPROM_OEM_ADDR_2 0xc /* Word */ |
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| 106 | #define EEPROM_SOFT_INFO_2 0xf /* Software information 2 */ |
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| 107 | |
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| 108 | #define NO_RX_OVN_ANOMALY (1<<5) |
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| 109 | |
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| 110 | /************************************************************************** |
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| 111 | * * |
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| 112 | * These are the registers for the 3Com 3c509 and their bit patterns when * |
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| 113 | * applicable. They have been taken out the the "EtherLink III Parallel * |
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| 114 | * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual * |
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| 115 | * from 3com. * |
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| 116 | * * |
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| 117 | **************************************************************************/ |
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| 118 | |
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| 119 | #define VX_COMMAND 0x0e /* Write. BASE+0x0e is always a |
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| 120 | * command reg. */ |
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| 121 | #define VX_STATUS 0x0e /* Read. BASE+0x0e is always status |
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| 122 | * reg. */ |
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| 123 | #define VX_WINDOW 0x0f /* Read. BASE+0x0f is always window |
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| 124 | * reg. */ |
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| 125 | /* |
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| 126 | * Window 0 registers. Setup. |
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| 127 | */ |
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| 128 | /* Write */ |
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| 129 | #define VX_W0_EEPROM_DATA 0x0c |
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| 130 | #define VX_W0_EEPROM_COMMAND 0x0a |
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| 131 | #define VX_W0_RESOURCE_CFG 0x08 |
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| 132 | #define VX_W0_ADDRESS_CFG 0x06 |
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| 133 | #define VX_W0_CONFIG_CTRL 0x04 |
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| 134 | /* Read */ |
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| 135 | #define VX_W0_PRODUCT_ID 0x02 |
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| 136 | #define VX_W0_MFG_ID 0x00 |
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| 137 | |
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| 138 | |
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| 139 | /* |
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| 140 | * Window 1 registers. Operating Set. |
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| 141 | */ |
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| 142 | /* Write */ |
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| 143 | #define VX_W1_TX_PIO_WR_2 0x02 |
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| 144 | #define VX_W1_TX_PIO_WR_1 0x00 |
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| 145 | /* Read */ |
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| 146 | #define VX_W1_FREE_TX 0x0c |
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| 147 | #define VX_W1_TX_STATUS 0x0b /* byte */ |
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| 148 | #define VX_W1_TIMER 0x0a /* byte */ |
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| 149 | #define VX_W1_RX_STATUS 0x08 |
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| 150 | #define VX_W1_RX_PIO_RD_2 0x02 |
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| 151 | #define VX_W1_RX_PIO_RD_1 0x00 |
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| 152 | |
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| 153 | /* |
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| 154 | * Window 2 registers. Station Address Setup/Read |
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| 155 | */ |
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| 156 | /* Read/Write */ |
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| 157 | #define VX_W2_ADDR_5 0x05 |
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| 158 | #define VX_W2_ADDR_4 0x04 |
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| 159 | #define VX_W2_ADDR_3 0x03 |
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| 160 | #define VX_W2_ADDR_2 0x02 |
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| 161 | #define VX_W2_ADDR_1 0x01 |
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| 162 | #define VX_W2_ADDR_0 0x00 |
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| 163 | |
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| 164 | /* |
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| 165 | * Window 3 registers. FIFO Management. |
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| 166 | */ |
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| 167 | /* Read */ |
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| 168 | #define VX_W3_INTERNAL_CFG 0x00 |
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| 169 | #define VX_W3_RESET_OPT 0x08 |
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| 170 | #define VX_W3_FREE_TX 0x0c |
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| 171 | #define VX_W3_FREE_RX 0x0a |
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| 172 | |
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| 173 | /* |
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| 174 | * Window 4 registers. Diagnostics. |
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| 175 | */ |
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| 176 | /* Read/Write */ |
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| 177 | #define VX_W4_MEDIA_TYPE 0x0a |
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| 178 | #define VX_W4_CTRLR_STATUS 0x08 |
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| 179 | #define VX_W4_NET_DIAG 0x06 |
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| 180 | #define VX_W4_FIFO_DIAG 0x04 |
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| 181 | #define VX_W4_HOST_DIAG 0x02 |
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| 182 | #define VX_W4_TX_DIAG 0x00 |
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| 183 | |
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| 184 | /* |
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| 185 | * Window 5 Registers. Results and Internal status. |
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| 186 | */ |
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| 187 | /* Read */ |
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| 188 | #define VX_W5_READ_0_MASK 0x0c |
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| 189 | #define VX_W5_INTR_MASK 0x0a |
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| 190 | #define VX_W5_RX_FILTER 0x08 |
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| 191 | #define VX_W5_RX_EARLY_THRESH 0x06 |
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| 192 | #define VX_W5_TX_AVAIL_THRESH 0x02 |
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| 193 | #define VX_W5_TX_START_THRESH 0x00 |
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| 194 | |
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| 195 | /* |
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| 196 | * Window 6 registers. Statistics. |
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| 197 | */ |
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| 198 | /* Read/Write */ |
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| 199 | #define TX_TOTAL_OK 0x0c |
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| 200 | #define RX_TOTAL_OK 0x0a |
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| 201 | #define TX_DEFERRALS 0x08 |
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| 202 | #define RX_FRAMES_OK 0x07 |
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| 203 | #define TX_FRAMES_OK 0x06 |
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| 204 | #define RX_OVERRUNS 0x05 |
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| 205 | #define TX_COLLISIONS 0x04 |
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| 206 | #define TX_AFTER_1_COLLISION 0x03 |
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| 207 | #define TX_AFTER_X_COLLISIONS 0x02 |
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| 208 | #define TX_NO_SQE 0x01 |
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| 209 | #define TX_CD_LOST 0x00 |
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| 210 | |
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| 211 | /**************************************** |
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| 212 | * |
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| 213 | * Register definitions. |
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| 214 | * |
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| 215 | ****************************************/ |
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| 216 | |
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| 217 | /* |
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| 218 | * Command register. All windows. |
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| 219 | * |
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| 220 | * 16 bit register. |
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| 221 | * 15-11: 5-bit code for command to be executed. |
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| 222 | * 10-0: 11-bit arg if any. For commands with no args; |
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| 223 | * this can be set to anything. |
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| 224 | */ |
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| 225 | #define GLOBAL_RESET (unsigned short) 0x0000 /* Wait at least 1ms |
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| 226 | * after issuing */ |
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| 227 | #define WINDOW_SELECT (unsigned short) (0x1<<11) |
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| 228 | #define START_TRANSCEIVER (unsigned short) (0x2<<11) /* Read ADDR_CFG reg to |
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| 229 | * determine whether |
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| 230 | * this is needed. If |
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| 231 | * so; wait 800 uSec |
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| 232 | * before using trans- |
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| 233 | * ceiver. */ |
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| 234 | #define RX_DISABLE (unsigned short) (0x3<<11) /* state disabled on |
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| 235 | * power-up */ |
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| 236 | #define RX_ENABLE (unsigned short) (0x4<<11) |
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| 237 | #define RX_RESET (unsigned short) (0x5<<11) |
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| 238 | #define RX_DISCARD_TOP_PACK (unsigned short) (0x8<<11) |
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| 239 | #define TX_ENABLE (unsigned short) (0x9<<11) |
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| 240 | #define TX_DISABLE (unsigned short) (0xa<<11) |
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| 241 | #define TX_RESET (unsigned short) (0xb<<11) |
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| 242 | #define REQ_INTR (unsigned short) (0xc<<11) |
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| 243 | /* |
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| 244 | * The following C_* acknowledge the various interrupts. Some of them don't |
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| 245 | * do anything. See the manual. |
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| 246 | */ |
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| 247 | #define ACK_INTR (unsigned short) (0x6800) |
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| 248 | # define C_INTR_LATCH (unsigned short) (ACK_INTR|0x1) |
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| 249 | # define C_CARD_FAILURE (unsigned short) (ACK_INTR|0x2) |
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| 250 | # define C_TX_COMPLETE (unsigned short) (ACK_INTR|0x4) |
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| 251 | # define C_TX_AVAIL (unsigned short) (ACK_INTR|0x8) |
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| 252 | # define C_RX_COMPLETE (unsigned short) (ACK_INTR|0x10) |
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| 253 | # define C_RX_EARLY (unsigned short) (ACK_INTR|0x20) |
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| 254 | # define C_INT_RQD (unsigned short) (ACK_INTR|0x40) |
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| 255 | # define C_UPD_STATS (unsigned short) (ACK_INTR|0x80) |
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| 256 | #define SET_INTR_MASK (unsigned short) (0xe<<11) |
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| 257 | #define SET_RD_0_MASK (unsigned short) (0xf<<11) |
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| 258 | #define SET_RX_FILTER (unsigned short) (0x10<<11) |
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| 259 | # define FIL_INDIVIDUAL (unsigned short) (0x1) |
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| 260 | # define FIL_MULTICAST (unsigned short) (0x02) |
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| 261 | # define FIL_BRDCST (unsigned short) (0x04) |
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| 262 | # define FIL_PROMISC (unsigned short) (0x08) |
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| 263 | #define SET_RX_EARLY_THRESH (unsigned short) (0x11<<11) |
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| 264 | #define SET_TX_AVAIL_THRESH (unsigned short) (0x12<<11) |
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| 265 | #define SET_TX_START_THRESH (unsigned short) (0x13<<11) |
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| 266 | #define STATS_ENABLE (unsigned short) (0x15<<11) |
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| 267 | #define STATS_DISABLE (unsigned short) (0x16<<11) |
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| 268 | #define STOP_TRANSCEIVER (unsigned short) (0x17<<11) |
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| 269 | |
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| 270 | /* |
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| 271 | * Status register. All windows. |
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| 272 | * |
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| 273 | * 15-13: Window number(0-7). |
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| 274 | * 12: Command_in_progress. |
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| 275 | * 11: reserved. |
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| 276 | * 10: reserved. |
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| 277 | * 9: reserved. |
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| 278 | * 8: reserved. |
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| 279 | * 7: Update Statistics. |
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| 280 | * 6: Interrupt Requested. |
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| 281 | * 5: RX Early. |
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| 282 | * 4: RX Complete. |
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| 283 | * 3: TX Available. |
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| 284 | * 2: TX Complete. |
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| 285 | * 1: Adapter Failure. |
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| 286 | * 0: Interrupt Latch. |
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| 287 | */ |
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| 288 | #define S_INTR_LATCH (unsigned short) (0x1) |
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| 289 | #define S_CARD_FAILURE (unsigned short) (0x2) |
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| 290 | #define S_TX_COMPLETE (unsigned short) (0x4) |
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| 291 | #define S_TX_AVAIL (unsigned short) (0x8) |
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| 292 | #define S_RX_COMPLETE (unsigned short) (0x10) |
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| 293 | #define S_RX_EARLY (unsigned short) (0x20) |
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| 294 | #define S_INT_RQD (unsigned short) (0x40) |
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| 295 | #define S_UPD_STATS (unsigned short) (0x80) |
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| 296 | #define S_COMMAND_IN_PROGRESS (unsigned short) (0x1000) |
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| 297 | |
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| 298 | #define VX_BUSY_WAIT while (inw(BASE + VX_STATUS) & S_COMMAND_IN_PROGRESS) |
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| 299 | |
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| 300 | /* Address Config. Register. |
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| 301 | * Window 0/Port 06 |
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| 302 | */ |
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| 303 | |
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| 304 | #define ACF_CONNECTOR_BITS 14 |
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| 305 | #define ACF_CONNECTOR_UTP 0 |
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| 306 | #define ACF_CONNECTOR_AUI 1 |
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| 307 | #define ACF_CONNECTOR_BNC 3 |
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| 308 | |
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| 309 | #define INTERNAL_CONNECTOR_BITS 20 |
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| 310 | #define INTERNAL_CONNECTOR_MASK 0x01700000 |
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| 311 | |
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| 312 | /* |
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| 313 | * FIFO Registers. RX Status. |
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| 314 | * |
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| 315 | * 15: Incomplete or FIFO empty. |
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| 316 | * 14: 1: Error in RX Packet 0: Incomplete or no error. |
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| 317 | * 13-11: Type of error. |
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| 318 | * 1000 = Overrun. |
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| 319 | * 1011 = Run Packet Error. |
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| 320 | * 1100 = Alignment Error. |
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| 321 | * 1101 = CRC Error. |
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| 322 | * 1001 = Oversize Packet Error (>1514 bytes) |
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| 323 | * 0010 = Dribble Bits. |
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| 324 | * (all other error codes, no errors.) |
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| 325 | * |
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| 326 | * 10-0: RX Bytes (0-1514) |
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| 327 | */ |
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| 328 | #define ERR_INCOMPLETE (unsigned short) (0x8000) |
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| 329 | #define ERR_RX (unsigned short) (0x4000) |
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| 330 | #define ERR_MASK (unsigned short) (0x7800) |
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| 331 | #define ERR_OVERRUN (unsigned short) (0x4000) |
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| 332 | #define ERR_RUNT (unsigned short) (0x5800) |
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| 333 | #define ERR_ALIGNMENT (unsigned short) (0x6000) |
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| 334 | #define ERR_CRC (unsigned short) (0x6800) |
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| 335 | #define ERR_OVERSIZE (unsigned short) (0x4800) |
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| 336 | #define ERR_DRIBBLE (unsigned short) (0x1000) |
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| 337 | |
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| 338 | /* |
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| 339 | * TX Status. |
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| 340 | * |
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| 341 | * Reports the transmit status of a completed transmission. Writing this |
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| 342 | * register pops the transmit completion stack. |
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| 343 | * |
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| 344 | * Window 1/Port 0x0b. |
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| 345 | * |
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| 346 | * 7: Complete |
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| 347 | * 6: Interrupt on successful transmission requested. |
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| 348 | * 5: Jabber Error (TP Only, TX Reset required. ) |
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| 349 | * 4: Underrun (TX Reset required. ) |
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| 350 | * 3: Maximum Collisions. |
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| 351 | * 2: TX Status Overflow. |
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| 352 | * 1-0: Undefined. |
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| 353 | * |
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| 354 | */ |
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| 355 | #define TXS_COMPLETE 0x80 |
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| 356 | #define TXS_INTR_REQ 0x40 |
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| 357 | #define TXS_JABBER 0x20 |
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| 358 | #define TXS_UNDERRUN 0x10 |
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| 359 | #define TXS_MAX_COLLISION 0x8 |
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| 360 | #define TXS_STATUS_OVERFLOW 0x4 |
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| 361 | |
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| 362 | #define RS_AUI (1<<5) |
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| 363 | #define RS_BNC (1<<4) |
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| 364 | #define RS_UTP (1<<3) |
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| 365 | #define RS_T4 (1<<0) |
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| 366 | #define RS_TX (1<<1) |
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| 367 | #define RS_FX (1<<2) |
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| 368 | #define RS_MII (1<<6) |
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| 369 | |
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| 370 | |
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| 371 | /* |
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| 372 | * FIFO Status (Window 4) |
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| 373 | * |
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| 374 | * Supports FIFO diagnostics |
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| 375 | * |
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| 376 | * Window 4/Port 0x04.1 |
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| 377 | * |
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| 378 | * 15: 1=RX receiving (RO). Set when a packet is being received |
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| 379 | * into the RX FIFO. |
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| 380 | * 14: Reserved |
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| 381 | * 13: 1=RX underrun (RO). Generates Adapter Failure interrupt. |
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| 382 | * Requires RX Reset or Global Reset command to recover. |
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| 383 | * It is generated when you read past the end of a packet - |
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| 384 | * reading past what has been received so far will give bad |
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| 385 | * data. |
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| 386 | * 12: 1=RX status overrun (RO). Set when there are already 8 |
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| 387 | * packets in the RX FIFO. While this bit is set, no additional |
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| 388 | * packets are received. Requires no action on the part of |
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| 389 | * the host. The condition is cleared once a packet has been |
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| 390 | * read out of the RX FIFO. |
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| 391 | * 11: 1=RX overrun (RO). Set when the RX FIFO is full (there |
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| 392 | * may not be an overrun packet yet). While this bit is set, |
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| 393 | * no additional packets will be received (some additional |
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| 394 | * bytes can still be pending between the wire and the RX |
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| 395 | * FIFO). Requires no action on the part of the host. The |
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| 396 | * condition is cleared once a few bytes have been read out |
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| 397 | * from the RX FIFO. |
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| 398 | * 10: 1=TX overrun (RO). Generates adapter failure interrupt. |
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| 399 | * Requires TX Reset or Global Reset command to recover. |
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| 400 | * Disables Transmitter. |
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| 401 | * 9-8: Unassigned. |
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| 402 | * 7-0: Built in self test bits for the RX and TX FIFO's. |
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| 403 | */ |
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| 404 | #define FIFOS_RX_RECEIVING (unsigned short) 0x8000 |
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| 405 | #define FIFOS_RX_UNDERRUN (unsigned short) 0x2000 |
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| 406 | #define FIFOS_RX_STATUS_OVERRUN (unsigned short) 0x1000 |
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| 407 | #define FIFOS_RX_OVERRUN (unsigned short) 0x0800 |
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| 408 | #define FIFOS_TX_OVERRUN (unsigned short) 0x0400 |
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| 409 | |
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| 410 | /* |
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| 411 | * Misc defines for various things. |
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| 412 | */ |
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| 413 | #define TAG_ADAPTER 0xd0 |
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| 414 | #define ACTIVATE_ADAPTER_TO_CONFIG 0xff |
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| 415 | #define ENABLE_DRQ_IRQ 0x0001 |
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| 416 | #define MFG_ID 0x506d /* `TCM' */ |
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| 417 | #define PROD_ID 0x5090 |
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| 418 | #define GO_WINDOW(x) outw(WINDOW_SELECT|(x),BASE+VX_COMMAND) |
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| 419 | #define JABBER_GUARD_ENABLE 0x40 |
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| 420 | #define LINKBEAT_ENABLE 0x80 |
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| 421 | #define ENABLE_UTP (JABBER_GUARD_ENABLE | LINKBEAT_ENABLE) |
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| 422 | #define DISABLE_UTP 0x0 |
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| 423 | #define RX_BYTES_MASK (unsigned short) (0x07ff) |
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| 424 | #define RX_ERROR 0x4000 |
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| 425 | #define RX_INCOMPLETE 0x8000 |
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| 426 | #define TX_INDICATE 1<<15 |
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| 427 | #define is_eeprom_busy(b) (inw((b)+VX_W0_EEPROM_COMMAND)&EEPROM_BUSY) |
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| 428 | |
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| 429 | #define VX_IOSIZE 0x20 |
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| 430 | |
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| 431 | #define VX_CONNECTORS 8 |
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| 432 | |
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| 433 | /* |
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| 434 | * Local variables: |
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| 435 | * c-basic-offset: 8 |
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| 436 | * End: |
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| 437 | */ |
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