| 1 | /* |
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| 2 | * i82365.h 1.15 1999/10/25 20:03:34 |
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| 3 | * |
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| 4 | * The contents of this file may be used under the |
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| 5 | * terms of the GNU General Public License version 2 (the "GPL"). |
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| 6 | * |
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| 7 | * Software distributed under the License is distributed on an "AS IS" |
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| 8 | * basis, WITHOUT WARRANTY OF ANY KIND, either express or implied. See |
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| 9 | * the License for the specific language governing rights and |
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| 10 | * limitations under the License. |
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| 11 | * |
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| 12 | * The initial developer of the original code is David A. Hinds |
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| 13 | * <dahinds@users.sourceforge.net>. Portions created by David A. Hinds |
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| 14 | * are Copyright (C) 1999 David A. Hinds. All Rights Reserved. |
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| 15 | */ |
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| 16 | |
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| 17 | #ifndef _LINUX_I82365_H |
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| 18 | #define _LINUX_I82365_H |
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| 19 | |
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| 20 | /* register definitions for the Intel 82365SL PCMCIA controller */ |
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| 21 | |
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| 22 | /* Offsets for PCIC registers */ |
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| 23 | #define I365_IDENT 0x00 /* Identification and revision */ |
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| 24 | #define I365_STATUS 0x01 /* Interface status */ |
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| 25 | #define I365_POWER 0x02 /* Power and RESETDRV control */ |
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| 26 | #define I365_INTCTL 0x03 /* Interrupt and general control */ |
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| 27 | #define I365_CSC 0x04 /* Card status change */ |
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| 28 | #define I365_CSCINT 0x05 /* Card status change interrupt control */ |
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| 29 | #define I365_ADDRWIN 0x06 /* Address window enable */ |
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| 30 | #define I365_IOCTL 0x07 /* I/O control */ |
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| 31 | #define I365_GENCTL 0x16 /* Card detect and general control */ |
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| 32 | #define I365_GBLCTL 0x1E /* Global control register */ |
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| 33 | |
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| 34 | /* Offsets for I/O and memory window registers */ |
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| 35 | #define I365_IO(map) (0x08+((map)<<2)) |
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| 36 | #define I365_MEM(map) (0x10+((map)<<3)) |
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| 37 | #define I365_W_START 0 |
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| 38 | #define I365_W_STOP 2 |
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| 39 | #define I365_W_OFF 4 |
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| 40 | |
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| 41 | /* Flags for I365_STATUS */ |
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| 42 | #define I365_CS_BVD1 0x01 |
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| 43 | #define I365_CS_STSCHG 0x01 |
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| 44 | #define I365_CS_BVD2 0x02 |
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| 45 | #define I365_CS_SPKR 0x02 |
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| 46 | #define I365_CS_DETECT 0x0C |
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| 47 | #define I365_CS_WRPROT 0x10 |
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| 48 | #define I365_CS_READY 0x20 /* Inverted */ |
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| 49 | #define I365_CS_POWERON 0x40 |
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| 50 | #define I365_CS_GPI 0x80 |
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| 51 | |
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| 52 | /* Flags for I365_POWER */ |
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| 53 | #define I365_PWR_OFF 0x00 /* Turn off the socket */ |
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| 54 | #define I365_PWR_OUT 0x80 /* Output enable */ |
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| 55 | #define I365_PWR_NORESET 0x40 /* Disable RESETDRV on resume */ |
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| 56 | #define I365_PWR_AUTO 0x20 /* Auto pwr switch enable */ |
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| 57 | #define I365_VCC_MASK 0x18 /* Mask for turning off Vcc */ |
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| 58 | /* There are different layouts for B-step and DF-step chips: the B |
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| 59 | step has independent Vpp1/Vpp2 control, and the DF step has only |
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| 60 | Vpp1 control, plus 3V control */ |
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| 61 | #define I365_VCC_5V 0x10 /* Vcc = 5.0v */ |
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| 62 | #define I365_VCC_3V 0x18 /* Vcc = 3.3v */ |
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| 63 | #define I365_VPP2_MASK 0x0c /* Mask for turning off Vpp2 */ |
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| 64 | #define I365_VPP2_5V 0x04 /* Vpp2 = 5.0v */ |
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| 65 | #define I365_VPP2_12V 0x08 /* Vpp2 = 12.0v */ |
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| 66 | #define I365_VPP1_MASK 0x03 /* Mask for turning off Vpp1 */ |
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| 67 | #define I365_VPP1_5V 0x01 /* Vpp2 = 5.0v */ |
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| 68 | #define I365_VPP1_12V 0x02 /* Vpp2 = 12.0v */ |
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| 69 | |
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| 70 | /* Flags for I365_INTCTL */ |
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| 71 | #define I365_RING_ENA 0x80 |
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| 72 | #define I365_PC_RESET 0x40 |
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| 73 | #define I365_PC_IOCARD 0x20 |
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| 74 | #define I365_INTR_ENA 0x10 |
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| 75 | #define I365_IRQ_MASK 0x0F |
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| 76 | |
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| 77 | /* Flags for I365_CSC and I365_CSCINT*/ |
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| 78 | #define I365_CSC_BVD1 0x01 |
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| 79 | #define I365_CSC_STSCHG 0x01 |
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| 80 | #define I365_CSC_BVD2 0x02 |
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| 81 | #define I365_CSC_READY 0x04 |
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| 82 | #define I365_CSC_DETECT 0x08 |
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| 83 | #define I365_CSC_ANY 0x0F |
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| 84 | #define I365_CSC_GPI 0x10 |
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| 85 | |
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| 86 | /* Flags for I365_ADDRWIN */ |
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| 87 | #define I365_ENA_IO(map) (0x40 << (map)) |
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| 88 | #define I365_ENA_MEM(map) (0x01 << (map)) |
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| 89 | |
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| 90 | /* Flags for I365_IOCTL */ |
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| 91 | #define I365_IOCTL_MASK(map) (0x0F << (map<<2)) |
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| 92 | #define I365_IOCTL_WAIT(map) (0x08 << (map<<2)) |
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| 93 | #define I365_IOCTL_0WS(map) (0x04 << (map<<2)) |
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| 94 | #define I365_IOCTL_IOCS16(map) (0x02 << (map<<2)) |
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| 95 | #define I365_IOCTL_16BIT(map) (0x01 << (map<<2)) |
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| 96 | |
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| 97 | /* Flags for I365_GENCTL */ |
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| 98 | #define I365_CTL_16DELAY 0x01 |
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| 99 | #define I365_CTL_RESET 0x02 |
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| 100 | #define I365_CTL_GPI_ENA 0x04 |
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| 101 | #define I365_CTL_GPI_CTL 0x08 |
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| 102 | #define I365_CTL_RESUME 0x10 |
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| 103 | #define I365_CTL_SW_IRQ 0x20 |
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| 104 | |
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| 105 | /* Flags for I365_GBLCTL */ |
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| 106 | #define I365_GBL_PWRDOWN 0x01 |
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| 107 | #define I365_GBL_CSC_LEV 0x02 |
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| 108 | #define I365_GBL_WRBACK 0x04 |
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| 109 | #define I365_GBL_IRQ_0_LEV 0x08 |
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| 110 | #define I365_GBL_IRQ_1_LEV 0x10 |
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| 111 | |
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| 112 | /* Flags for memory window registers */ |
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| 113 | #define I365_MEM_16BIT 0x8000 /* In memory start high byte */ |
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| 114 | #define I365_MEM_0WS 0x4000 |
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| 115 | #define I365_MEM_WS1 0x8000 /* In memory stop high byte */ |
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| 116 | #define I365_MEM_WS0 0x4000 |
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| 117 | #define I365_MEM_WRPROT 0x8000 /* In offset high byte */ |
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| 118 | #define I365_MEM_REG 0x4000 |
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| 119 | |
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| 120 | #define I365_REG(slot, reg) (((slot) << 6) + reg) |
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| 121 | |
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| 122 | #endif /* _LINUX_I82365_H */ |
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| 123 | |
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| 124 | //***************************************************************************** |
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| 125 | //***************************************************************************** |
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| 126 | //***************************************************************************** |
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| 127 | //***************************************************************************** |
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| 128 | //***************************************************************************** |
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| 129 | // Beginning vg468.h (for VADEM chipset) |
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| 130 | |
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| 131 | #ifndef _LINUX_VG468_H |
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| 132 | #define _LINUX_VG468_H |
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| 133 | |
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| 134 | /* Special bit in I365_IDENT used for Vadem chip detection */ |
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| 135 | #define I365_IDENT_VADEM 0x08 |
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| 136 | |
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| 137 | /* Special definitions in I365_POWER */ |
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| 138 | #define VG468_VPP2_MASK 0x0c |
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| 139 | #define VG468_VPP2_5V 0x04 |
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| 140 | #define VG468_VPP2_12V 0x08 |
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| 141 | |
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| 142 | /* Unique Vadem registers */ |
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| 143 | #define VG469_VSENSE 0x1f /* Card voltage sense */ |
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| 144 | #define VG469_VSELECT 0x2f /* Card voltage select */ |
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| 145 | #define VG468_CTL 0x38 /* Control register */ |
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| 146 | #define VG468_TIMER 0x39 /* Timer control */ |
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| 147 | #define VG468_MISC 0x3a /* Miscellaneous */ |
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| 148 | #define VG468_GPIO_CFG 0x3b /* GPIO configuration */ |
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| 149 | #define VG469_EXT_MODE 0x3c /* Extended mode register */ |
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| 150 | #define VG468_SELECT 0x3d /* Programmable chip select */ |
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| 151 | #define VG468_SELECT_CFG 0x3e /* Chip select configuration */ |
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| 152 | #define VG468_ATA 0x3f /* ATA control */ |
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| 153 | |
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| 154 | /* Flags for VG469_VSENSE */ |
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| 155 | #define VG469_VSENSE_A_VS1 0x01 |
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| 156 | #define VG469_VSENSE_A_VS2 0x02 |
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| 157 | #define VG469_VSENSE_B_VS1 0x04 |
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| 158 | #define VG469_VSENSE_B_VS2 0x08 |
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| 159 | |
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| 160 | /* Flags for VG469_VSELECT */ |
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| 161 | #define VG469_VSEL_VCC 0x03 |
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| 162 | #define VG469_VSEL_5V 0x00 |
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| 163 | #define VG469_VSEL_3V 0x03 |
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| 164 | #define VG469_VSEL_MAX 0x0c |
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| 165 | #define VG469_VSEL_EXT_STAT 0x10 |
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| 166 | #define VG469_VSEL_EXT_BUS 0x20 |
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| 167 | #define VG469_VSEL_MIXED 0x40 |
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| 168 | #define VG469_VSEL_ISA 0x80 |
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| 169 | |
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| 170 | /* Flags for VG468_CTL */ |
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| 171 | #define VG468_CTL_SLOW 0x01 /* 600ns memory timing */ |
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| 172 | #define VG468_CTL_ASYNC 0x02 /* Asynchronous bus clocking */ |
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| 173 | #define VG468_CTL_TSSI 0x08 /* Tri-state some outputs */ |
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| 174 | #define VG468_CTL_DELAY 0x10 /* Card detect debounce */ |
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| 175 | #define VG468_CTL_INPACK 0x20 /* Obey INPACK signal? */ |
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| 176 | #define VG468_CTL_POLARITY 0x40 /* VCCEN polarity */ |
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| 177 | #define VG468_CTL_COMPAT 0x80 /* Compatibility stuff */ |
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| 178 | |
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| 179 | #define VG469_CTL_WS_COMPAT 0x04 /* Wait state compatibility */ |
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| 180 | #define VG469_CTL_STRETCH 0x10 /* LED stretch */ |
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| 181 | |
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| 182 | /* Flags for VG468_TIMER */ |
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| 183 | #define VG468_TIMER_ZEROPWR 0x10 /* Zero power control */ |
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| 184 | #define VG468_TIMER_SIGEN 0x20 /* Power up */ |
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| 185 | #define VG468_TIMER_STATUS 0x40 /* Activity timer status */ |
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| 186 | #define VG468_TIMER_RES 0x80 /* Timer resolution */ |
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| 187 | #define VG468_TIMER_MASK 0x0f /* Activity timer timeout */ |
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| 188 | |
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| 189 | /* Flags for VG468_MISC */ |
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| 190 | #define VG468_MISC_GPIO 0x04 /* General-purpose IO */ |
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| 191 | #define VG468_MISC_DMAWSB 0x08 /* DMA wait state control */ |
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| 192 | #define VG469_MISC_LEDENA 0x10 /* LED enable */ |
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| 193 | #define VG468_MISC_VADEMREV 0x40 /* Vadem revision control */ |
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| 194 | #define VG468_MISC_UNLOCK 0x80 /* Unique register lock */ |
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| 195 | |
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| 196 | /* Flags for VG469_EXT_MODE_A */ |
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| 197 | #define VG469_MODE_VPPST 0x03 /* Vpp steering control */ |
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| 198 | #define VG469_MODE_INT_SENSE 0x04 /* Internal voltage sense */ |
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| 199 | #define VG469_MODE_CABLE 0x08 |
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| 200 | #define VG469_MODE_COMPAT 0x10 /* i82365sl B or DF step */ |
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| 201 | #define VG469_MODE_TEST 0x20 |
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| 202 | #define VG469_MODE_RIO 0x40 /* Steer RIO to INTR? */ |
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| 203 | |
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| 204 | /* Flags for VG469_EXT_MODE_B */ |
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| 205 | #define VG469_MODE_B_3V 0x01 /* 3.3v for socket B */ |
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| 206 | |
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| 207 | #endif /* _LINUX_VG468_H */ |
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| 208 | |
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| 209 | |
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| 210 | //***************************************************************************** |
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| 211 | //***************************************************************************** |
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| 212 | //***************************************************************************** |
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| 213 | //***************************************************************************** |
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| 214 | //***************************************************************************** |
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| 215 | // Beginning ricoh.h (RICOH chipsets) |
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| 216 | |
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| 217 | #ifndef _LINUX_RICOH_H |
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| 218 | #define _LINUX_RICOH_H |
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| 219 | |
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| 220 | |
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| 221 | #define RF5C_MODE_CTL 0x1f /* Mode control */ |
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| 222 | #define RF5C_PWR_CTL 0x2f /* Mixed voltage control */ |
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| 223 | #define RF5C_CHIP_ID 0x3a /* Chip identification */ |
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| 224 | #define RF5C_MODE_CTL_3 0x3b /* Mode control 3 */ |
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| 225 | |
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| 226 | /* I/O window address offset */ |
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| 227 | #define RF5C_IO_OFF(w) (0x36+((w)<<1)) |
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| 228 | |
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| 229 | /* Flags for RF5C_MODE_CTL */ |
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| 230 | #define RF5C_MODE_ATA 0x01 /* ATA mode */ |
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| 231 | #define RF5C_MODE_LED_ENA 0x02 /* IRQ 12 is LED */ |
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| 232 | #define RF5C_MODE_CA21 0x04 |
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| 233 | #define RF5C_MODE_CA22 0x08 |
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| 234 | #define RF5C_MODE_CA23 0x10 |
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| 235 | #define RF5C_MODE_CA24 0x20 |
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| 236 | #define RF5C_MODE_CA25 0x40 |
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| 237 | #define RF5C_MODE_3STATE_BIT7 0x80 |
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| 238 | |
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| 239 | /* Flags for RF5C_PWR_CTL */ |
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| 240 | #define RF5C_PWR_VCC_3V 0x01 |
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| 241 | #define RF5C_PWR_IREQ_HIGH 0x02 |
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| 242 | #define RF5C_PWR_INPACK_ENA 0x04 |
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| 243 | #define RF5C_PWR_5V_DET 0x08 |
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| 244 | #define RF5C_PWR_TC_SEL 0x10 /* Terminal Count: irq 11 or 15 */ |
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| 245 | #define RF5C_PWR_DREQ_LOW 0x20 |
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| 246 | #define RF5C_PWR_DREQ_OFF 0x00 /* DREQ steering control */ |
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| 247 | #define RF5C_PWR_DREQ_INPACK 0x40 |
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| 248 | #define RF5C_PWR_DREQ_SPKR 0x80 |
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| 249 | #define RF5C_PWR_DREQ_IOIS16 0xc0 |
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| 250 | |
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| 251 | /* Values for RF5C_CHIP_ID */ |
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| 252 | #define RF5C_CHIP_RF5C296 0x32 |
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| 253 | #define RF5C_CHIP_RF5C396 0xb2 |
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| 254 | |
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| 255 | /* Flags for RF5C_MODE_CTL_3 */ |
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| 256 | #define RF5C_MCTL3_DISABLE 0x01 /* Disable PCMCIA interface */ |
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| 257 | #define RF5C_MCTL3_DMA_ENA 0x02 |
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| 258 | |
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| 259 | /* Register definitions for Ricoh PCI-to-CardBus bridges */ |
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| 260 | |
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| 261 | /* Extra bits in CB_BRIDGE_CONTROL */ |
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| 262 | #define RL5C46X_BCR_3E0_ENA 0x0800 |
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| 263 | #define RL5C46X_BCR_3E2_ENA 0x1000 |
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| 264 | |
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| 265 | /* Bridge Configuration Register */ |
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| 266 | #define RL5C4XX_CONFIG 0x80 /* 16 bit */ |
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| 267 | #define RL5C4XX_CONFIG_IO_1_MODE 0x0200 |
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| 268 | #define RL5C4XX_CONFIG_IO_0_MODE 0x0100 |
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| 269 | #define RL5C4XX_CONFIG_PREFETCH 0x0001 |
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| 270 | |
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| 271 | |
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| 272 | /* Misc Control Register */ |
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| 273 | #define RL5C4XX_MISC 0x0082 /* 16 bit */ |
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| 274 | #define RL5C4XX_MISC_HW_SUSPEND_ENA 0x0002 |
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| 275 | #define RL5C4XX_MISC_VCCEN_POL 0x0100 |
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| 276 | #define RL5C4XX_MISC_VPPEN_POL 0x0200 |
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| 277 | #define RL5C46X_MISC_SUSPEND 0x0001 |
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| 278 | #define RL5C46X_MISC_PWR_SAVE_2 0x0004 |
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| 279 | #define RL5C46X_MISC_IFACE_BUSY 0x0008 |
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| 280 | #define RL5C46X_MISC_B_LOCK 0x0010 |
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| 281 | #define RL5C46X_MISC_A_LOCK 0x0020 |
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| 282 | #define RL5C46X_MISC_PCI_LOCK 0x0040 |
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| 283 | #define RL5C47X_MISC_IFACE_BUSY 0x0004 |
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| 284 | #define RL5C47X_MISC_PCI_INT_MASK 0x0018 |
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| 285 | #define RL5C47X_MISC_PCI_INT_DIS 0x0020 |
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| 286 | #define RL5C47X_MISC_SUBSYS_WR 0x0040 |
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| 287 | #define RL5C47X_MISC_SRIRQ_ENA 0x0080 |
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| 288 | #define RL5C47X_MISC_5V_DISABLE 0x0400 |
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| 289 | #define RL5C47X_MISC_LED_POL 0x0800 |
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| 290 | |
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| 291 | /* 16-bit Interface Control Register */ |
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| 292 | #define RL5C4XX_16BIT_CTL 0x0084 /* 16 bit */ |
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| 293 | #define RL5C4XX_16CTL_IO_TIMING 0x0100 |
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| 294 | #define RL5C4XX_16CTL_MEM_TIMING 0x0200 |
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| 295 | #define RL5C46X_16CTL_LEVEL_1 0x0010 |
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| 296 | #define RL5C46X_16CTL_LEVEL_2 0x0020 |
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| 297 | |
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| 298 | /* 16-bit IO and memory timing registers */ |
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| 299 | #define RL5C4XX_16BIT_IO_0 0x0088 /* 16 bit */ |
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| 300 | #define RL5C4XX_16BIT_MEM_0 0x0088 /* 16 bit */ |
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| 301 | #define RL5C4XX_SETUP_MASK 0x0007 |
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| 302 | #define RL5C4XX_SETUP_SHIFT 0 |
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| 303 | #define RL5C4XX_CMD_MASK 0x01f0 |
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| 304 | #define RL5C4XX_CMD_SHIFT 4 |
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| 305 | #define RL5C4XX_HOLD_MASK 0x1c00 |
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| 306 | #define RL5C4XX_HOLD_SHIFT 10 |
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| 307 | #define RL5C4XX_MISC_CONTROL 0x2F /* 8 bit */ |
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| 308 | #define RL5C4XX_ZV_ENABLE 0x08 |
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| 309 | |
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| 310 | #endif /* _LINUX_RICOH_H */ |
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| 311 | |
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| 312 | |
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| 313 | //***************************************************************************** |
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| 314 | //***************************************************************************** |
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| 315 | //***************************************************************************** |
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| 316 | //***************************************************************************** |
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| 317 | //***************************************************************************** |
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| 318 | // Beginning cirrus.h (CIRRUS chipsets) |
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| 319 | |
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| 320 | #ifndef _LINUX_CIRRUS_H |
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| 321 | #define _LINUX_CIRRUS_H |
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| 322 | |
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| 323 | #ifndef PCI_VENDOR_ID_CIRRUS |
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| 324 | #define PCI_VENDOR_ID_CIRRUS 0x1013 |
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| 325 | #endif |
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| 326 | #ifndef PCI_DEVICE_ID_CIRRUS_6729 |
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| 327 | #define PCI_DEVICE_ID_CIRRUS_6729 0x1100 |
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| 328 | #endif |
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| 329 | #ifndef PCI_DEVICE_ID_CIRRUS_6832 |
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| 330 | #define PCI_DEVICE_ID_CIRRUS_6832 0x1110 |
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| 331 | #endif |
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| 332 | |
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| 333 | #define PD67_MISC_CTL_1 0x16 /* Misc control 1 */ |
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| 334 | #define PD67_FIFO_CTL 0x17 /* FIFO control */ |
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| 335 | #define PD67_MISC_CTL_2 0x1E /* Misc control 2 */ |
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| 336 | #define PD67_CHIP_INFO 0x1f /* Chip information */ |
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| 337 | #define PD67_ATA_CTL 0x026 /* 6730: ATA control */ |
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| 338 | #define PD67_EXT_INDEX 0x2e /* Extension index */ |
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| 339 | #define PD67_EXT_DATA 0x2f /* Extension data */ |
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| 340 | |
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| 341 | /* PD6722 extension registers -- indexed in PD67_EXT_INDEX */ |
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| 342 | #define PD67_DATA_MASK0 0x01 /* Data mask 0 */ |
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| 343 | #define PD67_DATA_MASK1 0x02 /* Data mask 1 */ |
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| 344 | #define PD67_DMA_CTL 0x03 /* DMA control */ |
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| 345 | |
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| 346 | /* PD6730 extension registers -- indexed in PD67_EXT_INDEX */ |
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| 347 | #define PD67_EXT_CTL_1 0x03 /* Extension control 1 */ |
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| 348 | #define PD67_MEM_PAGE(n) ((n)+5) /* PCI window bits 31:24 */ |
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| 349 | #define PD67_EXTERN_DATA 0x0a |
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| 350 | #define PD67_MISC_CTL_3 0x25 |
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| 351 | #define PD67_SMB_PWR_CTL 0x26 |
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| 352 | |
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| 353 | /* I/O window address offset */ |
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| 354 | #define PD67_IO_OFF(w) (0x36+((w)<<1)) |
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| 355 | |
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| 356 | /* Timing register sets */ |
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| 357 | #define PD67_TIME_SETUP(n) (0x3a + 3*(n)) |
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| 358 | #define PD67_TIME_CMD(n) (0x3b + 3*(n)) |
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| 359 | #define PD67_TIME_RECOV(n) (0x3c + 3*(n)) |
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| 360 | |
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| 361 | /* Flags for PD67_MISC_CTL_1 */ |
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| 362 | #define PD67_MC1_5V_DET 0x01 /* 5v detect */ |
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| 363 | #define PD67_MC1_MEDIA_ENA 0x01 /* 6730: Multimedia enable */ |
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| 364 | #define PD67_MC1_VCC_3V 0x02 /* 3.3v Vcc */ |
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| 365 | #define PD67_MC1_PULSE_MGMT 0x04 |
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| 366 | #define PD67_MC1_PULSE_IRQ 0x08 |
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| 367 | #define PD67_MC1_SPKR_ENA 0x10 |
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| 368 | #define PD67_MC1_INPACK_ENA 0x80 |
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| 369 | |
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| 370 | /* Flags for PD67_FIFO_CTL */ |
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| 371 | #define PD67_FIFO_EMPTY 0x80 |
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| 372 | |
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| 373 | /* Flags for PD67_MISC_CTL_2 */ |
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| 374 | #define PD67_MC2_FREQ_BYPASS 0x01 |
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| 375 | #define PD67_MC2_DYNAMIC_MODE 0x02 |
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| 376 | #define PD67_MC2_SUSPEND 0x04 |
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| 377 | #define PD67_MC2_5V_CORE 0x08 |
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| 378 | #define PD67_MC2_LED_ENA 0x10 /* IRQ 12 is LED enable */ |
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| 379 | #define PD67_MC2_FAST_PCI 0x10 /* 6729: PCI bus > 25 MHz */ |
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| 380 | #define PD67_MC2_3STATE_BIT7 0x20 /* Floppy change bit */ |
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| 381 | #define PD67_MC2_DMA_MODE 0x40 |
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| 382 | #define PD67_MC2_IRQ15_RI 0x80 /* IRQ 15 is ring enable */ |
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| 383 | |
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| 384 | /* Flags for PD67_CHIP_INFO */ |
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| 385 | #define PD67_INFO_SLOTS 0x20 /* 0 = 1 slot, 1 = 2 slots */ |
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| 386 | #define PD67_INFO_CHIP_ID 0xc0 |
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| 387 | #define PD67_INFO_REV 0x1c |
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| 388 | |
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| 389 | /* Fields in PD67_TIME_* registers */ |
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| 390 | #define PD67_TIME_SCALE 0xc0 |
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| 391 | #define PD67_TIME_SCALE_1 0x00 |
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| 392 | #define PD67_TIME_SCALE_16 0x40 |
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| 393 | #define PD67_TIME_SCALE_256 0x80 |
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| 394 | #define PD67_TIME_SCALE_4096 0xc0 |
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| 395 | #define PD67_TIME_MULT 0x3f |
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| 396 | |
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| 397 | /* Fields in PD67_DMA_CTL */ |
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| 398 | #define PD67_DMA_MODE 0xc0 |
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| 399 | #define PD67_DMA_OFF 0x00 |
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| 400 | #define PD67_DMA_DREQ_INPACK 0x40 |
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| 401 | #define PD67_DMA_DREQ_WP 0x80 |
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| 402 | #define PD67_DMA_DREQ_BVD2 0xc0 |
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| 403 | #define PD67_DMA_PULLUP 0x20 /* Disable socket pullups? */ |
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| 404 | |
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| 405 | /* Fields in PD67_EXT_CTL_1 */ |
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| 406 | #define PD67_EC1_VCC_PWR_LOCK 0x01 |
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| 407 | #define PD67_EC1_AUTO_PWR_CLEAR 0x02 |
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| 408 | #define PD67_EC1_LED_ENA 0x04 |
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| 409 | #define PD67_EC1_INV_CARD_IRQ 0x08 |
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| 410 | #define PD67_EC1_INV_MGMT_IRQ 0x10 |
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| 411 | #define PD67_EC1_PULLUP_CTL 0x20 |
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| 412 | |
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| 413 | /* Fields in PD67_MISC_CTL_3 */ |
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| 414 | #define PD67_MC3_IRQ_MASK 0x03 |
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| 415 | #define PD67_MC3_IRQ_PCPCI 0x00 |
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| 416 | #define PD67_MC3_IRQ_EXTERN 0x01 |
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| 417 | #define PD67_MC3_IRQ_PCIWAY 0x02 |
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| 418 | #define PD67_MC3_IRQ_PCI 0x03 |
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| 419 | #define PD67_MC3_PWR_MASK 0x0c |
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| 420 | #define PD67_MC3_PWR_SERIAL 0x00 |
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| 421 | #define PD67_MC3_PWR_TI2202 0x08 |
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| 422 | #define PD67_MC3_PWR_SMB 0x0c |
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| 423 | |
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| 424 | /* Register definitions for Cirrus PD6832 PCI-to-CardBus bridge */ |
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| 425 | |
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| 426 | /* PD6832 extension registers -- indexed in PD67_EXT_INDEX */ |
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| 427 | #define PD68_EXT_CTL_2 0x0b |
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| 428 | #define PD68_PCI_SPACE 0x22 |
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| 429 | #define PD68_PCCARD_SPACE 0x23 |
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| 430 | #define PD68_WINDOW_TYPE 0x24 |
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| 431 | #define PD68_EXT_CSC 0x2e |
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| 432 | #define PD68_MISC_CTL_4 0x2f |
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| 433 | #define PD68_MISC_CTL_5 0x30 |
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| 434 | #define PD68_MISC_CTL_6 0x31 |
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| 435 | |
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| 436 | /* Extra flags in PD67_MISC_CTL_3 */ |
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| 437 | #define PD68_MC3_HW_SUSP 0x10 |
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| 438 | #define PD68_MC3_MM_EXPAND 0x40 |
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| 439 | #define PD68_MC3_MM_ARM 0x80 |
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| 440 | |
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| 441 | /* Bridge Control Register */ |
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| 442 | #define PD6832_BCR_MGMT_IRQ_ENA 0x0800 |
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| 443 | |
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| 444 | /* Socket Number Register */ |
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| 445 | #define PD6832_SOCKET_NUMBER 0x004c /* 8 bit */ |
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| 446 | |
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| 447 | #endif /* _LINUX_CIRRUS_H */ |
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| 448 | |
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| 449 | |
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| 450 | |
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